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msrtool: added support for Intel CPUs
Change-Id: I05f54471665aa99335a88d097c6de20174f91dc6 Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/50 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Anton Kochkov
committed by
Stefan Reinauer
Stefan Reinauer
parent
180f81e9a9
commit
7c634ae8c1
@@ -23,10 +23,10 @@ PROGRAM = msrtool
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CC = @CC@
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INSTALL = @INSTALL@
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PREFIX = @PREFIX@
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CFLAGS = @CFLAGS@
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CFLAGS = @CFLAGS@ -fno-pic
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LDFLAGS = @LDFLAGS@
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TARGETS = geodegx2.o geodelx.o cs5536.o k8.o
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TARGETS = geodegx2.o geodelx.o cs5536.o k8.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_core1.o intel_core2_early.o intel_core2_later.o
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SYSTEMS = linux.o darwin.o freebsd.o
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OBJS = $(PROGRAM).o msrutils.o sys.o $(SYSTEMS) $(TARGETS)
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@@ -0,0 +1,221 @@
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/*
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* This file is part of msrtool.
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*
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* Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "msrtool.h"
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int intel_core1_probe(const struct targetdef *target) {
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struct cpuid_t *id = cpuid();
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return ((0x6 == id->family)&(0xe == id->model));
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}
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const struct msrdef intel_core1_msrs[] = {
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{0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
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{ BITS_EOT }
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}},
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{0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
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{ BITS_EOT }
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}},
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{0xcd, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_STS", "", {
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{ BITS_EOT }
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}},
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{0xce, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_VCC", "", {
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{ BITS_EOT }
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}},
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{0xe2, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_CST_CONFIG_CONTROL", "", {
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{ BITS_EOT }
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}},
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{0xe3, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_BASE_ADDR", "", {
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{ BITS_EOT }
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}},
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{0xe4, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_CAPTURE_ADDR", "", {
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{ BITS_EOT }
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}},
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{0xee, MSRTYPE_RDWR, MSR2(0,0), "EXT_CONFIG", "", {
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{ BITS_EOT }
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}},
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{0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
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{ BITS_EOT }
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}},
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{0x194, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_FLEX_MAX", "", {
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{ BITS_EOT }
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}},
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{0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", {
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{ BITS_EOT }
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}},
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{0x1aa, MSRTYPE_RDWR, MSR2(0,0), "PIC_SENS_CFG", "", {
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{ BITS_EOT }
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}},
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{0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
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{ BITS_EOT }
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}},
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{0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
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{ BITS_EOT }
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}},
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{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
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{ BITS_EOT }
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}},
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{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
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{ BITS_EOT }
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}},
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{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
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{ BITS_EOT }
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}},
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{0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
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{ BITS_EOT }
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}},
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{0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
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{ BITS_EOT }
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}},
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{0x3f, MSRTYPE_RDWR, MSR2(0,0), "IA32_TEMPERATURE_OFFSET", "", {
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{ BITS_EOT }
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}},
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{0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
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{ BITS_EOT }
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}},
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{0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", {
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{ BITS_EOT }
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}},
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{0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", {
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{ BITS_EOT }
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}},
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{0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
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{ BITS_EOT }
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}},
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{0x15f, MSRTYPE_RDWR, MSR2(0,0), "DTS_CAL_CTRL", "", {
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{ BITS_EOT }
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}},
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{0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
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{ BITS_EOT }
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}},
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{0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", {
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{ BITS_EOT }
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}},
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{0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
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{ BITS_EOT }
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}},
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{0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
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{ BITS_EOT }
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}},
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{0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x19d, MSRTYPE_RDWR, MSR2(0,0), "GV_THERM", "", {
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{ BITS_EOT }
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}},
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{0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
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{ BITS_EOT }
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}},
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{0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
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{ BITS_EOT }
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}},
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{0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
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{ BITS_EOT }
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}},
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{0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
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{ BITS_EOT }
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}},
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{0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
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{ BITS_EOT }
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}},
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{0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
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{ BITS_EOT }
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}},
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{0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
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{ BITS_EOT }
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}},
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{0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
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{ BITS_EOT }
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}},
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{0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
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{ BITS_EOT }
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}},
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{0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
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{ BITS_EOT }
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}},
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{0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
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{ BITS_EOT }
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}},
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{0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
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{ BITS_EOT }
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}},
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{0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
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{ BITS_EOT }
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}},
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{0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
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{ BITS_EOT }
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}},
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{0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
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{ BITS_EOT }
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}},
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{0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
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{ BITS_EOT }
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}},
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{0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
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{ BITS_EOT }
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}},
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{0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
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{ BITS_EOT }
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}},
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{0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
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{ BITS_EOT }
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}},
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{0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
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{ BITS_EOT }
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}},
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{0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
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{ BITS_EOT }
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}},
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{0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
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{ BITS_EOT }
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}},
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{0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
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{ BITS_EOT }
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}},
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{0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
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{ BITS_EOT }
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}},
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{0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
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{ BITS_EOT }
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}},
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{0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
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{ BITS_EOT }
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}},
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{0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
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{ BITS_EOT }
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}},
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{0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
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{ BITS_EOT }
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}},
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{0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
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{ BITS_EOT }
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}},
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{ MSR_EOT }
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};
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@@ -0,0 +1,236 @@
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/*
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* This file is part of msrtool.
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*
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* Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "msrtool.h"
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int intel_core2_early_probe(const struct targetdef *target) {
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struct cpuid_t *id = cpuid();
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return ((0x6 == id->family)&(0xf == id->model));
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}
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const struct msrdef intel_core2_early_msrs[] = {
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{0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
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{ BITS_EOT }
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}},
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{0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
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{ BITS_EOT }
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}},
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{0x3f, MSRTYPE_RDWR, MSR2(0,0), "IA32_TEMPERATURE_OFFSET", "", {
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{ BITS_EOT }
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}},
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{0xa8, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE0", "", {
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{ BITS_EOT }
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}},
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{0xa9, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE1", "", {
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{ BITS_EOT }
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}},
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{0xaa, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE2", "", {
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{ BITS_EOT }
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}},
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{0xab, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE3", "", {
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{ BITS_EOT }
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}},
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{0xac, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE4", "", {
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{ BITS_EOT }
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}},
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{0xad, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE5", "", {
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{ BITS_EOT }
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}},
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{0xcd, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_STS", "", {
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{ BITS_EOT }
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}},
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{0xe2, MSRTYPE_RDWR, MSR2(0,0), "PMG_CST_CONFIG_CONTROL", "", {
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{ BITS_EOT }
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}},
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{0xe3, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_BASE_ADDR", "", {
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{ BITS_EOT }
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}},
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{0xe4, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_CAPTURE_ADDR", "", {
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{ BITS_EOT }
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}},
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{0xee, MSRTYPE_RDWR, MSR2(0,0), "EXT_CONFIG", "", {
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{ BITS_EOT }
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}},
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{0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
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{ BITS_EOT }
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}},
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{0x194, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_FLEX_MAX", "", {
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{ BITS_EOT }
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}},
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{0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", {
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{ BITS_EOT }
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}},
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{0x1aa, MSRTYPE_RDWR, MSR2(0,0), "PIC_SENS_CFG", "", {
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{ BITS_EOT }
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}},
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{0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
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{ BITS_EOT }
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}},
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{0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
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{ BITS_EOT }
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}},
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{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
|
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{ BITS_EOT }
|
||||
}},
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{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
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{ BITS_EOT }
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||||
}},
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{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
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{ BITS_EOT }
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}},
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{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
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{ BITS_EOT }
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}},
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{0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
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{ BITS_EOT }
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}},
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{0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
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{ BITS_EOT }
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}},
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{0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
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{ BITS_EOT }
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}},
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{0xe1, MSRTYPE_RDWR, MSR2(0,0), "SMM_CST_MISC_INFO", "", {
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{ BITS_EOT }
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}},
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{0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", {
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{ BITS_EOT }
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}},
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{0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", {
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{ BITS_EOT }
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}},
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{0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
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{ BITS_EOT }
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}},
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{0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{ MSR_EOT }
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,182 @@
|
||||
/*
|
||||
* This file is part of msrtool.
|
||||
*
|
||||
* Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include "msrtool.h"
|
||||
|
||||
int intel_pentium3_probe(const struct targetdef *target) {
|
||||
struct cpuid_t *id = cpuid();
|
||||
return ((0x6 == id->family)&((0xa == id->model)|(0xb == id->model)));
|
||||
}
|
||||
|
||||
const struct msrdef intel_pentium3_msrs[] = {
|
||||
{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x3f, MSRTYPE_RDWR, MSR2(0,0), "THERM_DIODE_OFFSET", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{ MSR_EOT }
|
||||
};
|
||||
@@ -0,0 +1,257 @@
|
||||
/*
|
||||
* This file is part of msrtool.
|
||||
*
|
||||
* Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include "msrtool.h"
|
||||
|
||||
int intel_pentium3_early_probe(const struct targetdef *target) {
|
||||
struct cpuid_t *id = cpuid();
|
||||
return ((0x6 == id->family)&((0x7 == id->model)|(0x8 == id->model)));
|
||||
}
|
||||
|
||||
const struct msrdef intel_pentium3_early_msrs[] = {
|
||||
{0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x88, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x89, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x8a, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x116, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x118, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_DECC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x119, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x11b, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_BUSY", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHFROMIP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1dc, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHTOIP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTFROMIP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTTOIP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_ROB_CR_BKUPTMPDR6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{ MSR_EOT }
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,342 @@
|
||||
/*
|
||||
* This file is part of msrtool.
|
||||
*
|
||||
* Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include "msrtool.h"
|
||||
|
||||
int intel_pentium4_later_probe(const struct targetdef *target) {
|
||||
struct cpuid_t *id = cpuid();
|
||||
return ((0xf == id->family)&((0x3 == id->model)|(0x4 == id->model)));
|
||||
}
|
||||
|
||||
const struct msrdef intel_pentium4_later_msrs[] = {
|
||||
{0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_LINE_SIZE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_HARD_POWERON", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x2b, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_SOFT_POWRON", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x2c, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_FREQUENCY_ID", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PLATFORM_BRV", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x300, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x301, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x302, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x303, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x9b, MSRTYPE_RDWR, MSR2(0,0), "IA32_SMM_MONITOR_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x180, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RAX", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x181, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBX", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x182, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RCX", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x183, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDX", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x184, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSI", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x185, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDI", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x186, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x187, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x188, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RFLAGS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x189, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RIP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x18a, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x190, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R8", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x191, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R9", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x192, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R10", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x193, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R11", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x194, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R12", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x195, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R13", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x196, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R14", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x197, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R15", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1d7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1d9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DEBUGCTLA", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x1da, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{ MSR_EOT }
|
||||
};
|
||||
|
||||
@@ -44,6 +44,13 @@ static struct targetdef alltargets[] = {
|
||||
{ "geodelx", "AMD Geode(tm) LX", geodelx_probe, geodelx_msrs },
|
||||
{ "cs5536", "AMD Geode(tm) CS5536", cs5536_probe, cs5536_msrs },
|
||||
{ "K8", "AMD K8 Family", k8_probe, k8_msrs },
|
||||
{ "intel_pentium3_early", "Intel Pentium III family", intel_pentium3_early_probe, intel_pentium3_early_msrs },
|
||||
{ "intel_pentium3", "Intel Pentium III Xeon Processor, Intel Pentium III Processor", intel_pentium3_probe, intel_pentium3_msrs },
|
||||
{ "intel_core1", "Intel Core Duo, Intel Core Solo processors", intel_core1_probe, intel_core1_msrs },
|
||||
{ "intel_core2_early", "Intel Xeon Processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad processor 6000 series, Intel Core 2 Extreme 6000 series, Intel Core 2 Duo 4000, 5000, 6000, 7000 series processors, Intel Pentium dual-core processors", intel_core2_early_probe, intel_core2_early_msrs },
|
||||
{ "intel_core2_later", "Intel Xeon Processor 5200, 5400 series, Intel Core 2 Quad processors 8000, 9000 series", intel_core2_later_probe, intel_core2_later_msrs },
|
||||
{ "intel_pentium4_early", "Intel Xeon Processor, Intel Xeon Processor MP, Intel Pentium 4 processors", intel_pentium4_early_probe, intel_pentium4_early_msrs },
|
||||
{ "intel_pentium4_later", "Intel Xeon Processor, Intel Xeon Processor MP, Intel Pentium 4, Pentium D processors", intel_pentium4_later_probe, intel_pentium4_later_msrs },
|
||||
{ TARGET_EOT }
|
||||
};
|
||||
|
||||
|
||||
@@ -214,4 +214,32 @@ extern const struct msrdef cs5536_msrs[];
|
||||
extern int k8_probe(const struct targetdef *t);
|
||||
extern const struct msrdef k8_msrs[];
|
||||
|
||||
/* intel_pentium3_early.c */
|
||||
extern int intel_pentium3_early_probe(const struct targetdef *t);
|
||||
extern const struct msrdef intel_pentium3_early_msrs[];
|
||||
|
||||
/* intel_pentium3.c */
|
||||
extern int intel_pentium3_probe(const struct targetdef *t);
|
||||
extern const struct msrdef intel_pentium3_msrs[];
|
||||
|
||||
/* intel_core1.c */
|
||||
extern int intel_core1_probe(const struct targetdef *t);
|
||||
extern const struct msrdef intel_core1_msrs[];
|
||||
|
||||
/* intel_core2_early.c */
|
||||
extern int intel_core2_early_probe(const struct targetdef *t);
|
||||
extern const struct msrdef intel_core2_early_msrs[];
|
||||
|
||||
/* intel_core2_later.c */
|
||||
extern int intel_core2_later_probe(const struct targetdef *t);
|
||||
extern const struct msrdef intel_core2_later_msrs[];
|
||||
|
||||
/* intel_pentium4_early.c */
|
||||
extern int intel_pentium4_early_probe(const struct targetdef *t);
|
||||
extern const struct msrdef intel_pentium4_early_msrs[];
|
||||
|
||||
/* intel_pentium4_later.c */
|
||||
extern int intel_pentium4_later_probe(const struct targetdef *t);
|
||||
extern const struct msrdef intel_pentium4_later_msrs[];
|
||||
|
||||
#endif /* MSRTOOL_H */
|
||||
|
||||
Reference in New Issue
Block a user