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soc/intel/quark: Drop support
As announced in the 4.20 release notes, support for the Intel Quark SoC is moved to the 4.20 branch and dropped from master. Change-Id: I8a1ca7a2092aaeaea9c72eac5a8dd8f7d72e8f09 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Felix Singer
committed by
Felix Singer
Felix Singer
parent
037c25d4dd
commit
531023285e
@@ -1,240 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config SOC_INTEL_QUARK
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bool
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help
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Intel Quark support
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if SOC_INTEL_QUARK
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_NO_CUSTOM_MADT
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select ARCH_X86
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select NO_ECAM_MMCONF_SUPPORT
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select NO_SMM
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select REG_SCRIPT
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select PLATFORM_USES_FSP2_0
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_RESET
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select SOC_SETS_MSRS
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select SPI_FLASH
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select UART_OVERRIDE_REFCLK
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select UDELAY_TSC
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select TSC_MONOTONIC_TIMER
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select UNCOMPRESSED_RAMSTAGE
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select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
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select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
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select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
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select USE_MARCH_586
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#####
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# Debug serial output
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# The following options configure the debug serial port
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#####
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config ENABLE_BUILTIN_HSUART0
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bool "Enable built-in HSUART0"
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default n
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select NO_UART_ON_SUPERIO
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select DRIVERS_UART_8250MEM_32
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help
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The Quark SoC has two HSUART. Choose this option to configure the pads
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and enable HSUART0, which can be used for the debug console.
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config ENABLE_BUILTIN_HSUART1
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bool "Enable built-in HSUART1"
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default n
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depends on ! ENABLE_BUILTIN_HSUART0
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select NO_UART_ON_SUPERIO
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select DRIVERS_UART_8250MEM_32
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help
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The Quark SoC has two HSUART. Choose this option to configure the pads
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and enable HSUART1, which can be used for the debug console.
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config TTYS0_BASE
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hex "HSUART Base Address"
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default 0xA0019000
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depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
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help
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Memory mapped MMIO of HSUART.
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config TTYS0_LCS
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int
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default 3
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depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
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#####
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# Debug support
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# The following options provide debug support for the Quark coreboot
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# code. The SD LED is used as a binary marker to determine if a
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# specific point in the execution flow has been reached.
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#####
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config ENABLE_DEBUG_LED
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bool
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default n
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help
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Enable the use of the SD LED for early debugging before serial output
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is available. Setting this LED indicates that control has reached the
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desired check point.
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config ENABLE_DEBUG_LED_ESRAM
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bool "SD LED indicates ESRAM initialized"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that ESRAM has been successfully initialized. If the SD LED
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does not light then the ESRAM initialization needs to be debugged.
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config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY
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bool "SD LED indicates bootblock.c successfully entered"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_c_entry was entered. If the SD LED does not
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light then debug the code between ESRAM and bootblock_c_entry.
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config ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY
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bool "SD LED indicates bootblock_soc_early_init successfully entered"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_soc_early_init was entered. If the SD LED
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does not light then debug the code in bootblock_main_with_timestamp.
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config ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT
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bool "SD LED indicates bootblock_soc_early_init successfully exited"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_soc_early_init exited. If the SD LED does not
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light then debug the scripts in bootblock_soc_early_init.
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config ENABLE_DEBUG_LED_SOC_INIT_ENTRY
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bool "SD LED indicates bootblock_soc_init successfully entered"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_soc_init was entered. If the SD LED does not
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light then debug the code in bootblock_mainboard_early_init and
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console_init. If the SD LED does light but there is no serial then
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debug the serial port configuration and initialization.
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#####
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# ESRAM layout
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# Specify the portion of the ESRAM for coreboot to use as its data area.
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#####
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config DCACHE_RAM_BASE
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hex
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default 0x80000000
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config DCACHE_RAM_SIZE
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hex
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default 0x40000
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config DISPLAY_ESRAM_LAYOUT
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bool "Display ESRAM layout"
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default n
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help
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Select this option to display coreboot's use of ESRAM.
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#####
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# Flash layout
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# Specify the size of the coreboot file system in the read-only
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# (recovery) portion of the flash part.
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#####
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config CBFS_SIZE
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default 0x200000
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help
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Specify the size of the coreboot file system in the read-only (recovery)
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portion of the flash part. On Quark systems the firmware image stores
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more than just coreboot, including:
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- The chipset microcode (RMU) binary file located at 0xFFF00000
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- Intel Trusted Execution Engine firmware
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#####
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# FSP binary
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# The following options control the FSP binary file placement in
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# the flash image and ESRAM. This file is required by the Quark
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# SoC code to boot coreboot and its payload.
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#####
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config FSP_ESRAM_LOC
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hex
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default 0x80040000
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help
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The location in ESRAM where a copy of the FSP binary is placed.
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config FSP_M_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd"
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config FSP_S_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd"
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#####
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# RMU binary
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# The following options control the Quark chipset microcode file
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# placement in the flash image. This file is required to bring
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# the Quark processor out of reset.
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#####
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config ADD_RMU_FILE
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bool "Should the RMU binary be added to the flash image?"
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default n
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help
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The RMU file is required to get the chip out of reset.
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config RMU_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/rmu.bin"
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depends on ADD_RMU_FILE
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help
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The path and filename of the Intel Quark RMU binary.
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config RMU_LOC
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hex
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default 0xfff00000
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depends on ADD_RMU_FILE
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help
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The location in CBFS that the RMU is located. It must match the
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strap-determined base address.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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#####
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# Test support
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#####
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config STORAGE_TEST
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bool "Test SD/MMC/eMMC card or device access"
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default n
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select COMMONLIB_STORAGE
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select SDHCI_CONTROLLER
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help
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Read block 0 from each partition of the storage device. User
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must also enable one or both of COMMONLIB_STORAGE_SD or
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COMMONLIB_STORAGE_MMC.
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config STORAGE_LOG
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bool "Log and display SD/MMC commands"
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default n
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depends on STORAGE_TEST
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#####
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# I2C debug support
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#####
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config I2C_DEBUG
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bool "Enable I2C debugging"
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default n
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help
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Display the I2C segments and controller errors
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endif # SOC_INTEL_QUARK
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@@ -1,72 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
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subdirs-y += romstage
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bootblock-y += bootblock/esram_init.S
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bootblock-y += bootblock/bootblock.c
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bootblock-y += i2c.c
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bootblock-y += reg_access.c
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bootblock-y += tsc_freq.c
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bootblock-y += uart_common.c
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verstage-y += i2c.c
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verstage-y += reg_access.c
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verstage-y += tsc_freq.c
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verstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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romstage-y += i2c.c
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romstage-y += memmap.c
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romstage-y += reg_access.c
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romstage-$(CONFIG_STORAGE_TEST) += storage_test.c
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romstage-y += tsc_freq.c
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romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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romstage-y += reset.c
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postcar-y += fsp_params.c
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postcar-y += i2c.c
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postcar-y += reg_access.c
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postcar-y += tsc_freq.c
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postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += chip.c
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ramstage-y += ehci.c
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ramstage-y += fsp_params.c
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ramstage-y += gpio_i2c.c
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ramstage-y += i2c.c
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ramstage-y += lpc.c
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ramstage-y += northcluster.c
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ramstage-y += reg_access.c
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ramstage-y += reset.c
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ramstage-y += sd.c
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ramstage-y += spi.c
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ramstage-y += spi_debug.c
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ramstage-$(CONFIG_STORAGE_TEST) += storage_test.c
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ramstage-y += tsc_freq.c
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ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
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CPPFLAGS_common += -I$(src)/soc/intel/quark
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CPPFLAGS_common += -I$(src)/soc/intel/quark/include
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# Chipset microcode path
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CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
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# Since FSP-M runs in CAR we need to relocate it to a specific address
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$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_ESRAM_LOC)
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# Add the FSP binary to the CBFS image
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cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
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fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
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fsp.bin-position := $(CONFIG_FSP_LOC)
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fsp.bin-type := raw
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# Add the chipset microcode file to the CBFS image
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cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
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rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
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rmu.bin-position := $(CONFIG_RMU_LOC)
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rmu.bin-type := raw
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endif # CONFIG_SOC_INTEL_QUARK
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@@ -1,76 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <soc/acpi.h>
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#include <soc/ramstage.h>
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC,
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PCI_FUNCTION_NUMBER_QNC_LPC);
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uint32_t gpe0_base = pci_read_config32(dev, R_QNC_LPC_GPE0BLK)
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& B_QNC_LPC_GPE0BLK_MASK;
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uint32_t pmbase = pci_read_config32(dev, R_QNC_LPC_PM1BLK)
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& B_QNC_LPC_PM1BLK_MASK;
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fadt->flags |= ACPI_FADT_PLATFORM_CLOCK;
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/* PM1 Status: ACPI 4.8.3.1.1 */
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fadt->pm1a_evt_blk = pmbase + R_QNC_PM1BLK_PM1S;
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fadt->pm1_evt_len = 2;
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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/* PM1 Control: ACPI 4.8.3.2.1 */
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fadt->pm1a_cnt_blk = pmbase + R_QNC_PM1BLK_PM1C;
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fadt->pm1_cnt_len = 2;
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fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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/* PM Timer: ACPI 4.8.3.3 */
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fadt->pm_tmr_blk = pmbase + R_QNC_PM1BLK_PM1T;
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fadt->pm_tmr_len = 4;
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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/* General-Purpose Event 0 Registers: ACPI 4.8.4.1 */
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fadt->gpe0_blk = gpe0_base;
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fadt->gpe0_blk_len = 4 * 2;
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
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fadt->x_gpe0_blk.addrh = 0x0;
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/* Display the base registers */
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printk(BIOS_SPEW, "FADT:\n");
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printk(BIOS_SPEW, " 0x%08x: GPE0_BASE\n", gpe0_base);
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printk(BIOS_SPEW, " 0x%08x: PMBASE\n", pmbase);
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printk(BIOS_SPEW, " 0x%08x: RESET\n", fadt->reset_reg.addrl);
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}
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uint16_t get_pmbase(void)
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{
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struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC,
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PCI_FUNCTION_NUMBER_QNC_LPC);
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return (uint16_t)pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK;
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}
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@@ -1,109 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <device/pci_def.h>
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#include <program_loading.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/reg_access.h>
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extern asmlinkage void light_sd_led(void);
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static const struct reg_script legacy_gpio_init[] = {
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/* Temporarily enable the legacy GPIO controller */
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REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID
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| LEGACY_GPIO_BASE_ADDRESS),
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/* Temporarily enable the GPE controller */
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REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID
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| GPE0_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO),
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REG_SCRIPT_END
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};
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static const struct reg_script i2c_gpio_controller_init[] = {
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/* Temporarily enable the GPIO controller */
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS),
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
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REG_SCRIPT_END
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};
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static const struct reg_script hsuart_init[] = {
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/* Enable the HSUART */
|
||||
REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS),
|
||||
REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static const struct reg_script mtrr_init[] = {
|
||||
/* Use write-through caching, for FSP 2.0 the cache will be invalidated
|
||||
* postchar (arch/x86/exit_car.S).
|
||||
*/
|
||||
|
||||
/* Enable the cache */
|
||||
REG_CPU_CR_AND(0, ~(CR0_CD | CR0_NW)),
|
||||
|
||||
/* Cache the SPI flash */
|
||||
REG_MSR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE)
|
||||
| MTRR_TYPE_WRTHROUGH)),
|
||||
REG_MSR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE)
|
||||
| MTRR_PHYS_MASK_VALID)),
|
||||
|
||||
/* Cache ESRAM */
|
||||
REG_MSR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000
|
||||
| MTRR_TYPE_WRTHROUGH)),
|
||||
REG_MSR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff)
|
||||
| MTRR_PHYS_MASK_VALID)),
|
||||
|
||||
/* Enable the variable MTRRs */
|
||||
REG_MSR_WRITE(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_EN
|
||||
| MTRR_TYPE_UNCACHEABLE),
|
||||
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
|
||||
{
|
||||
if (CONFIG(ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY))
|
||||
light_sd_led();
|
||||
|
||||
bootblock_main_with_basetime(base_timestamp);
|
||||
}
|
||||
|
||||
void bootblock_soc_early_init(void)
|
||||
{
|
||||
if (CONFIG(ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY))
|
||||
light_sd_led();
|
||||
|
||||
/* Initialize the MTRRs */
|
||||
reg_script_run(mtrr_init);
|
||||
|
||||
/* Initialize the controllers */
|
||||
reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
|
||||
reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
|
||||
|
||||
/* Enable the HSUART */
|
||||
if (CONFIG(ENABLE_BUILTIN_HSUART0))
|
||||
reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
|
||||
if (CONFIG(ENABLE_BUILTIN_HSUART1))
|
||||
reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
|
||||
|
||||
if (CONFIG(ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT))
|
||||
light_sd_led();
|
||||
}
|
||||
|
||||
void bootblock_soc_init(void)
|
||||
{
|
||||
if (CONFIG(ENABLE_DEBUG_LED_SOC_INIT_ENTRY))
|
||||
light_sd_led();
|
||||
|
||||
display_mtrrs();
|
||||
}
|
||||
|
||||
void platform_prog_run(struct prog *prog)
|
||||
{
|
||||
/* Display the program entry point */
|
||||
printk(BIOS_SPEW, "Calling %s, %p(%p)\n", prog->name,
|
||||
prog->entry, prog->arg);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,126 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <assert.h>
|
||||
#include <device/device.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
/* Cat Trip Clear value must be less than Cat Trip Set value */
|
||||
#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105
|
||||
#define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS 65
|
||||
|
||||
static const struct reg_script thermal_init_script[] = {
|
||||
|
||||
/* Setup RMU Thermal sensor registers for Ratiometric mode. */
|
||||
REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG,
|
||||
~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK
|
||||
| B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK
|
||||
| B_TSCGF1_CONFIG_ISNSINTERNALVREFEN
|
||||
| B_TSCGF1_CONFIG_IBGEN
|
||||
| B_TSCGF1_CONFIG_IBGCHOPEN),
|
||||
((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE
|
||||
<< B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP)
|
||||
| (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE
|
||||
<< B_TSCGF1_CONFIG_ISNSCHOPSEL_BP)
|
||||
| (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE
|
||||
<< B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP)
|
||||
| (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE
|
||||
<< B_TSCGF1_CONFIG_IBGEN_BP)
|
||||
| (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE
|
||||
<< B_TSCGF1_CONFIG_IBGCHOPEN_BP))),
|
||||
|
||||
REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2,
|
||||
~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK
|
||||
| B_TSCGF2_CONFIG2_ISPARECTRL_MASK
|
||||
| B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK),
|
||||
((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE
|
||||
<< B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP)
|
||||
| (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE
|
||||
<< B_TSCGF2_CONFIG2_ISPARECTRL_BP)
|
||||
| (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE
|
||||
<< B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))),
|
||||
|
||||
REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG,
|
||||
~(B_TSCGF2_CONFIG_IDSCONTROL_MASK
|
||||
| B_TSCGF2_CONFIG_IDSTIMING_MASK),
|
||||
((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE
|
||||
<< B_TSCGF2_CONFIG_IDSCONTROL_BP)
|
||||
| (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE
|
||||
<< B_TSCGF2_CONFIG_IDSTIMING_BP))),
|
||||
|
||||
REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG,
|
||||
~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK,
|
||||
V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE
|
||||
<< B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP),
|
||||
|
||||
/* Enable RMU Thermal sensor with a Catastrophic Trip point. */
|
||||
|
||||
/* Set up Catastrophic Trip point.
|
||||
*
|
||||
* Trip Register fields are 8-bit temperature values of granularity 1
|
||||
* degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds
|
||||
* to 205 degrees C.
|
||||
*
|
||||
* Add 50 to Celsius values to get values for register fields.
|
||||
*/
|
||||
REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP,
|
||||
~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK),
|
||||
(((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50)
|
||||
<< TS_CAT_TRIP_SET_THOLD_BP)
|
||||
| ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50)
|
||||
<< TS_CAT_TRIP_CLEAR_THOLD_BP))),
|
||||
|
||||
/* To enable the TS do the following:
|
||||
* 1) Take the TS out of reset by setting itsrst to 0x0.
|
||||
* 2) Enable the TS using RMU Thermal sensor mode register.
|
||||
*/
|
||||
REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG,
|
||||
~B_TSCGF3_CONFIG_ITSRST),
|
||||
REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE),
|
||||
|
||||
/* Lock all RMU Thermal sensor control & trip point registers. */
|
||||
REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE
|
||||
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static void chip_init(void *chip_info)
|
||||
{
|
||||
/* Validate the temperature settings */
|
||||
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255);
|
||||
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS
|
||||
> PLATFORM_CATASTROPHIC_CLEAR_CELSIUS);
|
||||
|
||||
/* Set the temperature settings */
|
||||
reg_script_run(thermal_init_script);
|
||||
|
||||
/* Verify that the thermal configuration is locked */
|
||||
ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG)
|
||||
& (TS_LOCK_THRM_CTRL_REGS_ENABLE
|
||||
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE))
|
||||
== (TS_LOCK_THRM_CTRL_REGS_ENABLE
|
||||
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
|
||||
|
||||
/* Perform silicon specific init. */
|
||||
fsp_silicon_init();
|
||||
}
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = pci_domain_read_resources,
|
||||
.set_resources = pci_domain_set_resources,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
};
|
||||
|
||||
static void chip_enable_dev(struct device *dev)
|
||||
{
|
||||
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_DOMAIN)
|
||||
dev->ops = &pci_domain_ops;
|
||||
}
|
||||
|
||||
struct chip_operations soc_intel_quark_ops = {
|
||||
CHIP_NAME("Intel Quark")
|
||||
.init = &chip_init,
|
||||
.enable_dev = chip_enable_dev,
|
||||
};
|
||||
@@ -1,101 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_CHIP_H_
|
||||
#define _SOC_CHIP_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <fsp/util.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/pm.h>
|
||||
|
||||
///
|
||||
/// MRC Flags bits
|
||||
///
|
||||
#define MRC_FLAG_ECC_EN BIT0
|
||||
#define MRC_FLAG_SCRAMBLE_EN BIT1
|
||||
#define MRC_FLAG_MEMTEST_EN BIT2
|
||||
|
||||
/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
|
||||
#define MRC_FLAG_TOP_TREE_EN BIT3
|
||||
|
||||
/* If set ODR signal is asserted to DRAM devices on writes */
|
||||
#define MRC_FLAG_WR_ODT_EN BIT4
|
||||
|
||||
struct soc_intel_quark_config {
|
||||
/*
|
||||
* MemoryInit:
|
||||
*
|
||||
* The following fields come from FspUpdVpd.h and are defined as PCDs
|
||||
* for the FSP binary. Data for these fields comes from the board's
|
||||
* devicetree.cb file which gets processed into static.c and then
|
||||
* built into the coreboot image. The fields below contain retain
|
||||
* the FSP PCD field name.
|
||||
*/
|
||||
|
||||
uint32_t FspReservedMemoryLength; /* FSP reserved memory in bytes */
|
||||
|
||||
uint32_t Flags; /* Bitmap of MRC_FLAG_XXX defs above */
|
||||
uint32_t tRAS; /* ACT to PRE command period in picoseconds */
|
||||
|
||||
/* Delay from start of internal write transaction to internal read
|
||||
* command in picoseconds
|
||||
*/
|
||||
uint32_t tWTR;
|
||||
|
||||
/* ACT to ACT command period (JESD79 specific to page size 1K/2K) in
|
||||
* picoseconds
|
||||
*/
|
||||
uint32_t tRRD;
|
||||
|
||||
/* Four activate window (JESD79 specific to page size 1K/2K) in
|
||||
* picoseconds
|
||||
*/
|
||||
uint32_t tFAW;
|
||||
uint8_t DramWidth; /* 0=x8, 1=x16, others=RESERVED */
|
||||
|
||||
/* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU
|
||||
* support 1066 memory
|
||||
*/
|
||||
uint8_t DramSpeed;
|
||||
uint8_t DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */
|
||||
|
||||
/* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */
|
||||
uint8_t RankMask;
|
||||
uint8_t ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */
|
||||
uint8_t ChanWidth; /* 1=x16, others=RESERVED */
|
||||
|
||||
/* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */
|
||||
uint8_t AddrMode;
|
||||
|
||||
/* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */
|
||||
uint8_t SrInt;
|
||||
uint8_t SrTemp; /* 0=normal, 1=extended, others=RESERVED */
|
||||
|
||||
/* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver
|
||||
* impedance control.
|
||||
*/
|
||||
uint8_t DramRonVal;
|
||||
uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RSVD */
|
||||
uint8_t DramRttWrVal; /* 0=off others=RESERVED */
|
||||
|
||||
/* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
|
||||
uint8_t SocRdOdtVal;
|
||||
uint8_t SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */
|
||||
uint8_t SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */
|
||||
|
||||
/* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */
|
||||
uint8_t DramDensity;
|
||||
uint8_t tCL; /* DRAM CAS Latency in clocks */
|
||||
|
||||
/* ECC scrub interval in milliseconds 1..255 (0 works as feature
|
||||
* disable)
|
||||
*/
|
||||
uint8_t EccScrubInterval;
|
||||
|
||||
/* Number of 32B blocks read for ECC scrub 2..16 */
|
||||
uint8_t EccScrubBlkSize;
|
||||
|
||||
uint8_t SmmTsegSize; /* SMM size in MiB */
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -1,119 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
/* USB Phy Registers */
|
||||
#define USB2_GLOBAL_PORT 0x4001
|
||||
#define USB2_PLL1 0x7F02
|
||||
#define USB2_PLL2 0x7F03
|
||||
#define USB2_COMPBG 0x7F04
|
||||
|
||||
/* EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs */
|
||||
#define EHCI_OUT_THRESHOLD_VALUE 0x7f
|
||||
#define EHCI_IN_THRESHOLD_VALUE 0x7f
|
||||
|
||||
/* Platform init USB device interrupt masks */
|
||||
#define V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG (0x0000007f)
|
||||
#define V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG \
|
||||
(B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK \
|
||||
| B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK)
|
||||
|
||||
/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL
|
||||
* reference clock and Port2 as a USB device port, the following sequence must
|
||||
* be followed
|
||||
*/
|
||||
static const struct reg_script ehci_init_script[] = {
|
||||
|
||||
/* Set packet buffer OUT/IN thresholds */
|
||||
REG_MMIO_RMW32(R_IOH_EHCI_INSNREG01,
|
||||
~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK
|
||||
| B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK),
|
||||
(EHCI_OUT_THRESHOLD_VALUE
|
||||
<< B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
|
||||
| (EHCI_IN_THRESHOLD_VALUE
|
||||
<< B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)),
|
||||
|
||||
/* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
|
||||
* For port 0 & 1 as host and port 2 as device.
|
||||
*/
|
||||
REG_USB_RXW(USB2_GLOBAL_PORT, ~(BIT8 | BIT7 | BIT1), (BIT8 | BIT7)),
|
||||
|
||||
/*
|
||||
* Sighting #4930653 Required BIOS change on Disconnect vref to change
|
||||
* to 600mV.
|
||||
*/
|
||||
REG_USB_RXW(USB2_COMPBG, ~(BIT10 | BIT9 | BIT8 | BIT7),
|
||||
(BIT10 | BIT7)),
|
||||
|
||||
/* Sideband register write to USB AFE (Phy)
|
||||
* (pllbypass) to bypass/Disable PLL before switch
|
||||
*/
|
||||
REG_USB_OR(USB2_PLL2, BIT29),
|
||||
|
||||
/* Sideband register write to USB AFE (Phy)
|
||||
* (coreclksel) to select 120MHz (ickusbcoreclk) clk source.
|
||||
* (Default 0 to select 96MHz (ickusbclk96_npad/ppad))
|
||||
*/
|
||||
REG_USB_OR(USB2_PLL1, BIT1),
|
||||
|
||||
/* Sideband register write to USB AFE (Phy)
|
||||
* (divide by 8) to achieve internal 480MHz clock
|
||||
* for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz)
|
||||
*/
|
||||
REG_USB_RXW(USB2_PLL1, ~(BIT6 | BIT5 | BIT4 | BIT3), BIT6),
|
||||
|
||||
/* Sideband register write to USB AFE (Phy)
|
||||
* Clear (pllbypass)
|
||||
*/
|
||||
REG_USB_AND(USB2_PLL2, ~BIT29),
|
||||
|
||||
/* Sideband register write to USB AFE (Phy)
|
||||
* Set (startlock) to force the PLL FSM to restart the lock
|
||||
* sequence due to input clock/freq switch.
|
||||
*/
|
||||
REG_USB_OR(USB2_PLL2, BIT24),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static const struct reg_script usb_device_port_init_script[] = {
|
||||
|
||||
/* Mask and clear controller interrupts */
|
||||
REG_MMIO_WRITE32(R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG,
|
||||
V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG),
|
||||
REG_MMIO_WRITE32(R_IOH_USBDEVICE_D_INTR_UDC_REG,
|
||||
V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG),
|
||||
|
||||
/* Mask and clear end point interrupts */
|
||||
REG_MMIO_WRITE32(R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG,
|
||||
V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG),
|
||||
REG_MMIO_WRITE32(R_IOH_USBDEVICE_EP_INTR_UDC_REG,
|
||||
V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static void init(struct device *dev)
|
||||
{
|
||||
if ((dev->path.pci.devfn & 7) == EHCI_FUNC) {
|
||||
printk(BIOS_INFO, "Initializing USB PLLs\n");
|
||||
reg_script_run_on_dev(dev, ehci_init_script);
|
||||
} else {
|
||||
printk(BIOS_INFO, "Initializing USB device port\n");
|
||||
reg_script_run_on_dev(dev, usb_device_port_init_script);
|
||||
}
|
||||
}
|
||||
|
||||
static struct device_operations device_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = init,
|
||||
};
|
||||
|
||||
static const struct pci_driver driver __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VID_INTEL,
|
||||
.device = EHCI_DEVID,
|
||||
};
|
||||
@@ -1,12 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <fsp/util.h>
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
|
||||
{
|
||||
}
|
||||
|
||||
asmlinkage void chipset_teardown_car(void)
|
||||
{
|
||||
}
|
||||
@@ -1,29 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/i2c_simple.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/i2c.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
__weak void mainboard_gpio_i2c_init(struct device *dev)
|
||||
{
|
||||
/* Initialize any of the GPIOs or I2C devices */
|
||||
printk(BIOS_SPEW, "WEAK; %s\n", __func__);
|
||||
}
|
||||
|
||||
static struct device_operations device_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = mainboard_gpio_i2c_init,
|
||||
};
|
||||
|
||||
static const struct pci_driver gfx_driver __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VID_INTEL,
|
||||
.device = I2CGPIO_DEVID,
|
||||
};
|
||||
@@ -1,357 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <assert.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <device/device.h>
|
||||
#include <device/i2c_simple.h>
|
||||
#include <device/pci.h>
|
||||
#include <soc/i2c.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <soc/reg_access.h>
|
||||
#include <timer.h>
|
||||
|
||||
static void i2c_disable(I2C_REGS *regs)
|
||||
{
|
||||
uint32_t status;
|
||||
uint32_t timeout;
|
||||
|
||||
/* Disable I2C controller */
|
||||
regs->ic_enable = 0;
|
||||
|
||||
/* Wait for the enable bit to clear */
|
||||
timeout = 1 * 1000 * 1000;
|
||||
status = regs->ic_enable_status;
|
||||
while (status & IC_ENABLE_CONTROLLER) {
|
||||
udelay(1);
|
||||
if (--timeout == 0)
|
||||
die_with_post_code(POST_HW_INIT_FAILURE,
|
||||
"ERROR - I2C failed to disable!\n");
|
||||
status = regs->ic_enable_status;
|
||||
}
|
||||
|
||||
/* Clear any pending interrupts */
|
||||
status = regs->ic_clr_intr;
|
||||
}
|
||||
|
||||
static int platform_i2c_write(uint32_t restart, uint8_t *tx_buffer, int length,
|
||||
uint32_t stop, uint8_t *rx_buffer, struct stopwatch *timeout)
|
||||
{
|
||||
int bytes_transferred;
|
||||
uint32_t cmd;
|
||||
I2C_REGS *regs;
|
||||
uint32_t status;
|
||||
|
||||
ASSERT(tx_buffer != NULL);
|
||||
ASSERT(timeout != NULL);
|
||||
regs = get_i2c_address();
|
||||
|
||||
/* Fill the FIFO with the write operation */
|
||||
bytes_transferred = 0;
|
||||
do {
|
||||
status = regs->ic_raw_intr_stat;
|
||||
|
||||
/* Check for errors */
|
||||
if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
|
||||
| IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) {
|
||||
i2c_disable(regs);
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C write error!\n",
|
||||
status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check for timeout */
|
||||
if (stopwatch_expired(timeout)) {
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C write timeout!\n",
|
||||
status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Receive any available data */
|
||||
status = regs->ic_status;
|
||||
if (rx_buffer != NULL) {
|
||||
while (status & IC_STATUS_RFNE) {
|
||||
*rx_buffer++ = (uint8_t)regs->ic_data_cmd;
|
||||
bytes_transferred++;
|
||||
status = regs->ic_status;
|
||||
}
|
||||
}
|
||||
|
||||
/* Determine if space is available in the FIFO */
|
||||
if (status & IC_STATUS_TFNF) {
|
||||
/* End of the transaction? */
|
||||
cmd = IC_DATA_CMD_WRITE | *tx_buffer++ | restart;
|
||||
if (length == 1)
|
||||
cmd |= stop;
|
||||
restart = 0;
|
||||
|
||||
/* Place a data byte into the FIFO */
|
||||
regs->ic_data_cmd = cmd;
|
||||
length--;
|
||||
bytes_transferred++;
|
||||
} else
|
||||
udelay(1);
|
||||
} while (length > 0);
|
||||
return bytes_transferred;
|
||||
}
|
||||
|
||||
static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length,
|
||||
uint32_t stop, struct stopwatch *timeout)
|
||||
{
|
||||
int bytes_transferred;
|
||||
uint32_t cmd;
|
||||
int fifo_bytes;
|
||||
I2C_REGS *regs;
|
||||
uint32_t status;
|
||||
|
||||
ASSERT(rx_buffer != NULL);
|
||||
ASSERT(timeout != NULL);
|
||||
regs = get_i2c_address();
|
||||
|
||||
/* Empty the FIFO */
|
||||
status = regs->ic_status;
|
||||
while (status & IC_STATUS_RFNE) {
|
||||
(void)regs->ic_data_cmd;
|
||||
status = regs->ic_status;
|
||||
}
|
||||
|
||||
/* Fill the FIFO with read commands */
|
||||
fifo_bytes = MIN(length, 16);
|
||||
bytes_transferred = 0;
|
||||
while (length > 0) {
|
||||
status = regs->ic_raw_intr_stat;
|
||||
|
||||
/* Check for errors */
|
||||
if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
|
||||
| IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) {
|
||||
i2c_disable(regs);
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C read error!\n",
|
||||
status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check for timeout */
|
||||
if (stopwatch_expired(timeout)) {
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C read timeout!\n",
|
||||
status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Receive any available data */
|
||||
status = regs->ic_status;
|
||||
if (status & IC_STATUS_RFNE) {
|
||||
/* Save the next data byte, removed from the RX FIFO */
|
||||
*rx_buffer++ = (uint8_t)regs->ic_data_cmd;
|
||||
bytes_transferred++;
|
||||
}
|
||||
|
||||
if ((status & IC_STATUS_TFNF)
|
||||
|| ((status & IC_STATUS_RFNE) && (fifo_bytes > 0))) {
|
||||
/* End of the transaction? */
|
||||
cmd = IC_DATA_CMD_READ | restart;
|
||||
if (length == 1)
|
||||
cmd |= stop;
|
||||
restart = 0;
|
||||
|
||||
/* Place a read command into the TX FIFO */
|
||||
regs->ic_data_cmd = cmd;
|
||||
if (fifo_bytes > 0)
|
||||
fifo_bytes--;
|
||||
length--;
|
||||
} else
|
||||
udelay(1);
|
||||
}
|
||||
return bytes_transferred;
|
||||
}
|
||||
|
||||
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment,
|
||||
int seg_count)
|
||||
{
|
||||
int bytes_transferred;
|
||||
uint8_t chip;
|
||||
uint32_t cmd;
|
||||
int data_bytes;
|
||||
int index;
|
||||
int length;
|
||||
I2C_REGS *regs;
|
||||
uint32_t restart;
|
||||
uint8_t *rx_buffer;
|
||||
uint32_t status;
|
||||
uint32_t stop;
|
||||
struct stopwatch timeout;
|
||||
int total_bytes;
|
||||
uint8_t *tx_buffer;
|
||||
int tx_bytes;
|
||||
|
||||
if (CONFIG(I2C_DEBUG)) {
|
||||
for (index = 0; index < seg_count;) {
|
||||
if (index == 0)
|
||||
printk(BIOS_ERR, "I2C Start\n");
|
||||
printk(BIOS_ERR,
|
||||
"I2C segment[%d]: %s 0x%02x %s %p, 0x%08x bytes\n",
|
||||
index,
|
||||
(segment[index].flags & I2C_M_RD) ? "Read from" : "Write to",
|
||||
segment[index].slave,
|
||||
(segment[index].flags & I2C_M_RD) ? "to " : "from",
|
||||
segment[index].buf,
|
||||
segment[index].len);
|
||||
printk(BIOS_ERR, "I2C %s\n",
|
||||
(++index >= seg_count) ? "Stop" : "Restart");
|
||||
}
|
||||
}
|
||||
|
||||
regs = get_i2c_address();
|
||||
|
||||
/* Disable the I2C controller to get access to the registers */
|
||||
i2c_disable(regs);
|
||||
|
||||
/* Set the slave address */
|
||||
ASSERT(seg_count > 0);
|
||||
ASSERT(segment != NULL);
|
||||
|
||||
/* Clear the start and stop detection */
|
||||
status = regs->ic_clr_start_det;
|
||||
status = regs->ic_clr_stop_det;
|
||||
|
||||
/* Set addressing mode to 7-bit and fast mode */
|
||||
cmd = regs->ic_con;
|
||||
cmd &= ~(IC_CON_10B | IC_CON_SPEED);
|
||||
cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_400_KHz
|
||||
| IC_CON_MASTER_MODE;
|
||||
regs->ic_con = cmd;
|
||||
|
||||
/* Set the target chip address */
|
||||
chip = segment->slave;
|
||||
regs->ic_tar = chip;
|
||||
|
||||
/* Enable the I2C controller */
|
||||
regs->ic_enable = IC_ENABLE_CONTROLLER;
|
||||
|
||||
/* Clear the interrupts */
|
||||
status = regs->ic_clr_rx_under;
|
||||
status = regs->ic_clr_rx_over;
|
||||
status = regs->ic_clr_tx_over;
|
||||
status = regs->ic_clr_tx_abrt;
|
||||
|
||||
/* Start the timeout */
|
||||
stopwatch_init_usecs_expire(&timeout, CONFIG_I2C_TRANSFER_TIMEOUT_US);
|
||||
|
||||
/* Process each of the segments */
|
||||
total_bytes = 0;
|
||||
tx_bytes = 0;
|
||||
bytes_transferred = 0;
|
||||
rx_buffer = NULL;
|
||||
restart = 0;
|
||||
index = 0;
|
||||
while (index++ < seg_count) {
|
||||
length = segment->len;
|
||||
total_bytes += length;
|
||||
ASSERT(segment->buf != NULL);
|
||||
ASSERT(length >= 1);
|
||||
ASSERT(segment->slave == chip);
|
||||
|
||||
/* Determine if this is the last segment of the transaction */
|
||||
stop = (index == seg_count) ? IC_DATA_CMD_STOP : 0;
|
||||
|
||||
/* Fill the FIFO with the necessary command bytes */
|
||||
if (segment->flags & I2C_M_RD) {
|
||||
/* Place read commands into the FIFO */
|
||||
rx_buffer = segment->buf;
|
||||
data_bytes = platform_i2c_read(restart, rx_buffer,
|
||||
length, stop, &timeout);
|
||||
|
||||
/* Return any detected error */
|
||||
if (data_bytes < 0) {
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"I2C segment[%d] failed\n",
|
||||
index);
|
||||
return data_bytes;
|
||||
}
|
||||
bytes_transferred += data_bytes;
|
||||
} else {
|
||||
/* Write the data into the FIFO */
|
||||
tx_buffer = segment->buf;
|
||||
tx_bytes += length;
|
||||
data_bytes = platform_i2c_write(restart, tx_buffer,
|
||||
length, stop, rx_buffer, &timeout);
|
||||
|
||||
/* Return any detected error */
|
||||
if (data_bytes < 0) {
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"I2C segment[%d] failed\n",
|
||||
index);
|
||||
return data_bytes;
|
||||
}
|
||||
bytes_transferred += data_bytes;
|
||||
}
|
||||
segment++;
|
||||
restart = IC_DATA_CMD_RESTART;
|
||||
}
|
||||
|
||||
/* Wait for the end of the transaction */
|
||||
if (rx_buffer != NULL)
|
||||
rx_buffer += bytes_transferred - tx_bytes;
|
||||
do {
|
||||
/* Receive any available data */
|
||||
status = regs->ic_status;
|
||||
if ((rx_buffer != NULL) && (status & IC_STATUS_RFNE)) {
|
||||
*rx_buffer++ = (uint8_t)regs->ic_data_cmd;
|
||||
bytes_transferred++;
|
||||
} else {
|
||||
status = regs->ic_raw_intr_stat;
|
||||
if ((total_bytes == bytes_transferred)
|
||||
&& (status & IC_INTR_STOP_DET))
|
||||
break;
|
||||
|
||||
/* Check for errors */
|
||||
if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
|
||||
| IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) {
|
||||
i2c_disable(regs);
|
||||
if (CONFIG(I2C_DEBUG)) {
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C read error!\n",
|
||||
status);
|
||||
printk(BIOS_ERR,
|
||||
"I2C segment[%d] failed\n",
|
||||
seg_count - 1);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check for timeout */
|
||||
if (stopwatch_expired(&timeout)) {
|
||||
if (CONFIG(I2C_DEBUG)) {
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C read timeout!\n",
|
||||
status);
|
||||
printk(BIOS_ERR,
|
||||
"I2C segment[%d] failed\n",
|
||||
seg_count - 1);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Delay for a while */
|
||||
udelay(1);
|
||||
}
|
||||
} while (1);
|
||||
i2c_disable(regs);
|
||||
regs->ic_tar = 0;
|
||||
|
||||
/* Return the number of bytes transferred */
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR, "0x%08x: bytes transferred\n",
|
||||
bytes_transferred);
|
||||
return bytes_transferred;
|
||||
}
|
||||
@@ -1,61 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
/* Some configuration of QNC Package */
|
||||
|
||||
#ifndef __INTEL_QNC_CONFIG_H__
|
||||
#define __INTEL_QNC_CONFIG_H__
|
||||
|
||||
//
|
||||
// QNC Fixed configurations.
|
||||
//
|
||||
|
||||
//
|
||||
// Memory arbiter fixed config values.
|
||||
//
|
||||
#define QNC_FIXED_CONFIG_ASTATUS ((UINT32) (\
|
||||
(ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \
|
||||
(ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \
|
||||
(ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \
|
||||
(ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \
|
||||
))
|
||||
|
||||
//
|
||||
// Memory Manager fixed config values.
|
||||
//
|
||||
#define V_DRAM_NON_HOST_RQ_LIMIT 2
|
||||
|
||||
//
|
||||
// RMU Thermal config fixed config values for TS in Vref Mode.
|
||||
//
|
||||
#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE 0x04
|
||||
#define V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE 0x01
|
||||
#define V_TSCGF1_CONFIG_IBGEN_VREF_MODE 1
|
||||
#define V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE 0x011b
|
||||
#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE 0x34
|
||||
|
||||
//
|
||||
// RMU Thermal config fixed config values for TS in Ratiometric mode.
|
||||
//
|
||||
#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE 0x04
|
||||
#define V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE 0x02
|
||||
#define V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE 1
|
||||
#define V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE 0x011f
|
||||
#define V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE 0x0001
|
||||
#define V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE 0x01
|
||||
#define V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE 0x00
|
||||
#define V_TSCGF1_CONFIG_IBGEN_RATIO_MODE 0
|
||||
#define V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE 0
|
||||
#define V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE 0xC8
|
||||
#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE 0x17
|
||||
|
||||
//
|
||||
// iCLK fixed config values.
|
||||
//
|
||||
#define V_MUXTOP_FLEX2 3
|
||||
#define V_MUXTOP_FLEX1 1
|
||||
|
||||
//
|
||||
// PCIe Root Port fixed config values.
|
||||
//
|
||||
#define V_PCIE_ROOT_PORT_SBIC_VALUE (B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER)
|
||||
|
||||
#endif
|
||||
@@ -1,244 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
#ifndef _IOH_H_
|
||||
#define _IOH_H_
|
||||
|
||||
#ifndef BIT0
|
||||
#define BIT0 0x01
|
||||
#define BIT1 0x02
|
||||
#define BIT2 0x04
|
||||
#define BIT3 0x08
|
||||
#define BIT4 0x10
|
||||
#define BIT5 0x20
|
||||
#define BIT6 0x40
|
||||
#define BIT7 0x80
|
||||
#define BIT8 0x100
|
||||
#define BIT9 0x200
|
||||
#define BIT00 0x00000001
|
||||
#define BIT01 0x00000002
|
||||
#define BIT02 0x00000004
|
||||
#define BIT03 0x00000008
|
||||
#define BIT04 0x00000010
|
||||
#define BIT05 0x00000020
|
||||
#define BIT06 0x00000040
|
||||
#define BIT07 0x00000080
|
||||
#define BIT08 0x00000100
|
||||
#define BIT09 0x00000200
|
||||
#define BIT10 0x00000400
|
||||
#define BIT11 0x00000800
|
||||
#define BIT12 0x00001000
|
||||
#define BIT13 0x00002000
|
||||
#define BIT14 0x00004000
|
||||
#define BIT15 0x00008000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT31 0x80000000
|
||||
#endif
|
||||
|
||||
#define IOH_PCI_CFG_ADDRESS(bus, dev, func, reg) \
|
||||
(((UINT32) ((((UINTN)bus) << 24) + (((UINTN)dev) << 16) + \
|
||||
(((UINTN)func) << 8) + ((UINTN)reg))) & 0x00000000ffffffff)
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
#define INTEL_VENDOR_ID 0x8086 // Intel Vendor ID
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Pci Configuration Map Register Offsets
|
||||
//----------------------------------------------------------------------------
|
||||
#define PCI_REG_VID 0x00 // Vendor ID Register
|
||||
#define PCI_REG_DID 0x02 // Device ID Register
|
||||
#define PCI_REG_PCICMD 0x04 // PCI Command Register
|
||||
#define PCI_REG_PCISTS 0x06 // PCI Status Register
|
||||
#define PCI_REG_RID 0x08 // PCI Revision ID Register
|
||||
#define PCI_REG_PI 0x09 // Programming Interface
|
||||
#define PCI_REG_SCC 0x0a // Sub Class Code Register
|
||||
#define PCI_REG_BCC 0x0b // Base Class Code Register
|
||||
#define PCI_REG_PMLT 0x0d // Primary Master Latnecy Timer
|
||||
#define PCI_REG_HDR 0x0e // Header Type Register
|
||||
#define PCI_REG_PBUS 0x18 // Primary Bus Number Register
|
||||
#define PCI_REG_SBUS 0x19 // Secondary Bus Number Register
|
||||
#define PCI_REG_SUBUS 0x1a // Subordinate Bus Number Register
|
||||
#define PCI_REG_SMLT 0x1b // Secondary Master Latnecy Timer
|
||||
#define PCI_REG_IOBASE 0x1c // I/O base Register
|
||||
#define PCI_REG_IOLIMIT 0x1d // I/O Limit Register
|
||||
#define PCI_REG_SECSTATUS 0x1e // Secondary Status Register
|
||||
#define PCI_REG_MEMBASE 0x20 // Memory Base Register
|
||||
#define PCI_REG_MEMLIMIT 0x22 // Memory Limit Register
|
||||
#define PCI_REG_PRE_MEMBASE 0x24 // Prefretchable memory Base register
|
||||
#define PCI_REG_PRE_MEMLIMIT 0x26 // Prefretchable memory Limit register
|
||||
#define PCI_REG_SVID0 0x2c // Subsystem Vendor ID low byte
|
||||
#define PCI_REG_SVID1 0x2d // Subsystem Vendor ID high byte
|
||||
#define PCI_REG_SID0 0x2e // Subsystem ID low byte
|
||||
#define PCI_REG_SID1 0x2f // Subsystem ID high byte
|
||||
#define PCI_REG_IOBASE_U 0x30 // I/O base Upper Register
|
||||
#define PCI_REG_IOLIMIT_U 0x32 // I/O Limit Upper Register
|
||||
#define PCI_REG_INTLINE 0x3c // Interrupt Line Register
|
||||
#define PCI_REG_BRIDGE_CNTL 0x3e // Bridge Control Register
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// QuarkSCSocId Packet Hub definitions
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define PCIE_BRIDGE_VID_DID 0x88008086
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster definitions.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define IOH_BUS 0
|
||||
#define IOH_PCI_IOSF2AHB_0_DEV_NUM 0x14
|
||||
#define IOH_PCI_IOSF2AHB_0_MAX_FUNCS 7
|
||||
#define IOH_PCI_IOSF2AHB_1_DEV_NUM 0x15
|
||||
#define IOH_PCI_IOSF2AHB_1_MAX_FUNCS 3
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster USB definitions.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define IOH_USB_BUS_NUMBER IOH_BUS
|
||||
#define IOH_USB_CONTROLLER_MMIO_RANGE 0x1000
|
||||
#define IOH_MAX_OHCI_USB_CONTROLLERS 1
|
||||
#define IOH_MAX_EHCI_USB_CONTROLLERS 1
|
||||
#define IOH_MAX_USBDEVICE_USB_CONTROLLERS 1
|
||||
|
||||
#define R_IOH_USB_VENDOR_ID 0x00
|
||||
#define V_IOH_USB_VENDOR_ID INTEL_VENDOR_ID
|
||||
#define R_IOH_USB_DEVICE_ID 0x02
|
||||
#define R_IOH_USB_COMMAND 0x04
|
||||
#define B_IOH_USB_COMMAND_BME BIT2
|
||||
#define B_IOH_USB_COMMAND_MSE BIT1
|
||||
#define B_IOH_USB_COMMAND_ISE BIT0
|
||||
#define R_IOH_USB_MEMBAR 0x10
|
||||
#define B_IOH_USB_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].
|
||||
#define R_IOH_USB_OHCI_HCCABAR 0x18
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster OHCI definitions
|
||||
//---------------------------------------------------------------------------
|
||||
#define IOH_USB_OHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
|
||||
#define IOH_OHCI_FUNCTION_NUMBER 0x04
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster EHCI definitions
|
||||
//---------------------------------------------------------------------------
|
||||
#define IOH_USB_EHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
|
||||
#define IOH_EHCI_FUNCTION_NUMBER 0x03
|
||||
|
||||
//
|
||||
// EHCI memory mapped registers offset from memory BAR0.
|
||||
//
|
||||
#define R_IOH_EHCI_CAPLENGTH 0x00
|
||||
#define R_IOH_EHCI_INSNREG01 0x94
|
||||
#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP (16)
|
||||
#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK \
|
||||
(0xff << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
|
||||
#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP (0)
|
||||
#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK \
|
||||
(0xff << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)
|
||||
|
||||
//
|
||||
// EHCI memory mapped registers offset from memory BAR0 + Cap length value.
|
||||
//
|
||||
#define R_IOH_EHCI_CONFIGFLAGS 0x40
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster USB Device definitions
|
||||
//---------------------------------------------------------------------------
|
||||
#define IOH_USBDEVICE_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
|
||||
#define IOH_USBDEVICE_FUNCTION_NUMBER 0x02
|
||||
|
||||
//
|
||||
// USB Device memory mapped registers offset from memory BAR0.
|
||||
//
|
||||
#define R_IOH_USBDEVICE_D_INTR_UDC_REG 0x40c
|
||||
#define R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG 0x410
|
||||
#define B_IOH_USBDEVICE_D_INTR_MSK_UDC_REG_MASK1_MASK 0xff
|
||||
#define R_IOH_USBDEVICE_EP_INTR_UDC_REG 0x414
|
||||
#define R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG 0x418
|
||||
#define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK 0x000f0000
|
||||
#define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK 0x0000000f
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster 10/100 Mbps Ethernet Device definitions.
|
||||
//---------------------------------------------------------------------------
|
||||
#define IOH_MAC0_BUS_NUMBER IOH_BUS
|
||||
#define IOH_MAC0_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
|
||||
#define IOH_MAC0_FUNCTION_NUMBER 0x06
|
||||
#define IOH_MAC1_BUS_NUMBER IOH_BUS
|
||||
#define IOH_MAC1_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
|
||||
#define IOH_MAC1_FUNCTION_NUMBER 0x07
|
||||
|
||||
//
|
||||
// MAC Device PCI config registers.
|
||||
//
|
||||
#define R_IOH_MAC_DEVICE_ID 0x02
|
||||
#define V_IOH_MAC_VENDOR_ID INTEL_VENDOR_ID
|
||||
#define R_IOH_MAC_DEVICE_ID 0x02
|
||||
#define V_IOH_MAC_DEVICE_ID 0x0937
|
||||
#define R_IOH_MAC_COMMAND 0x04
|
||||
#define B_IOH_MAC_COMMAND_BME BIT2
|
||||
#define B_IOH_MAC_COMMAND_MSE BIT1
|
||||
#define B_IOH_MAC_COMMAND_ISE BIT0
|
||||
#define R_IOH_MAC_MEMBAR 0x10
|
||||
#define B_IOH_MAC_MEMBAR_ADDRESS_MASK 0xFFFFF000
|
||||
|
||||
//
|
||||
// LAN Device memory mapped registers offset from memory BAR0.
|
||||
//
|
||||
#define R_IOH_MAC_GMAC_REG_8 0x20
|
||||
#define B_IOH_MAC_USERVER_MASK 0x0000FF00
|
||||
#define B_IOH_MAC_SNPSVER_MASK 0x000000FF
|
||||
#define R_IOH_MAC_GMAC_REG_16 0x40
|
||||
#define B_IOH_MAC_ADDRHI_MASK 0x0000FFFF
|
||||
#define B_IOH_MAC_AE BIT31
|
||||
#define R_IOH_MAC_GMAC_REG_17 0x44
|
||||
#define B_IOH_MAC_ADDRLO_MASK 0xFFFFFFFF
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark I2C / GPIO definitions
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define V_IOH_I2C_GPIO_VENDOR_ID INTEL_VENDOR_ID
|
||||
#define V_IOH_I2C_GPIO_DEVICE_ID 0x0934
|
||||
|
||||
#define R_IOH_I2C_MEMBAR 0x10
|
||||
#define B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK 0xFFFFF000 // [31:12].
|
||||
|
||||
#define GPIO_SWPORTA_DR 0x00
|
||||
#define GPIO_SWPORTA_DDR 0x04
|
||||
#define GPIO_INTEN 0x30
|
||||
#define GPIO_INTMASK 0x34
|
||||
#define GPIO_INTTYPE_LEVEL 0x38
|
||||
#define GPIO_INT_POLARITY 0x3C
|
||||
#define GPIO_INTSTATUS 0x40
|
||||
#define GPIO_RAW_INTSTATUS 0x44
|
||||
#define GPIO_DEBOUNCE 0x48
|
||||
#define GPIO_PORTA_EOI 0x4C
|
||||
#define GPIO_EXT_PORTA 0x50
|
||||
#define GPIO_EXT_PORTB 0x54
|
||||
#define GPIO_LS_SYNC 0x60
|
||||
#define GPIO_CONFIG_REG2 0x70
|
||||
#define GPIO_CONFIG_REG1 0x74
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster UART definitions.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define R_IOH_UART_MEMBAR 0x10
|
||||
#define B_IOH_UART_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,9 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_ACPI_H_
|
||||
#define _SOC_ACPI_H_
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
#include <acpi/acpigen.h>
|
||||
|
||||
#endif /* _SOC_ACPI_H_ */
|
||||
@@ -1,16 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_CAR_H_
|
||||
#define _SOC_CAR_H_
|
||||
|
||||
#include <fsp/util.h>
|
||||
|
||||
/* Mainboard and SoC initialization prior to console. */
|
||||
void car_mainboard_pre_console_init(void);
|
||||
void car_soc_pre_console_init(void);
|
||||
|
||||
/* Mainboard and SoC initialization post console initialization. */
|
||||
void car_mainboard_post_console_init(void);
|
||||
void car_soc_post_console_init(void);
|
||||
|
||||
#endif /* _SOC_CAR_H_ */
|
||||
@@ -1,11 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _QUARK_CPU_H_
|
||||
#define _QUARK_CPU_H_
|
||||
|
||||
#include <device/device.h>
|
||||
|
||||
/* Supported CPUIDs */
|
||||
#define CPUID_QUARK_X1000 0x590
|
||||
|
||||
#endif /* _QUARK_CPU_H_ */
|
||||
@@ -1,120 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _QUARK_I2C_H_
|
||||
#define _QUARK_I2C_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct _I2C_REGS {
|
||||
volatile uint32_t ic_con; /* 00: Control Register */
|
||||
volatile uint32_t ic_tar; /* 04: Master Target Address */
|
||||
uint32_t reserved_08[2];
|
||||
volatile uint32_t ic_data_cmd; /* 10: Data Buffer & Command */
|
||||
uint32_t ic_ss_scl_hcnt; /* 14: Standard Speed Clock SCL High Count */
|
||||
uint32_t ic_ss_scl_lcnt; /* 18: Standard Speed Clock SCL Low Count */
|
||||
uint32_t ic_fs_scl_hcnt; /* 1c: Fast Speed Clock SCL High Count */
|
||||
uint32_t ic_fs_scl_lcnt; /* 20: Fast Speed Clock SCL Low Count */
|
||||
uint32_t reserved_24[2];
|
||||
volatile uint32_t ic_intr_stat; /* 2c: Interrupt Status */
|
||||
uint32_t ic_intr_mask; /* 30: Interrupt Mask */
|
||||
uint32_t ic_raw_intr_stat; /* 34: Raw Interrupt Status */
|
||||
uint32_t ic_rx_tl; /* 38: Receive FIFO Threshold Level */
|
||||
uint32_t ic_tx_tl; /* 3c: Transmit FIFO Threshold Level */
|
||||
uint32_t ic_clr_intr; /* 40: Clear Combined/Individual Interrupt */
|
||||
uint32_t ic_clr_rx_under; /* 44: Clear RX_UNDER Interrupt */
|
||||
uint32_t ic_clr_rx_over; /* 48: Clear RX_OVER Interrupt */
|
||||
uint32_t ic_clr_tx_over; /* 4c: Clear TX_OVER Interrupt */
|
||||
uint32_t ic_clr_rd_req; /* 50: Clear RD_REQ Interrupt */
|
||||
uint32_t ic_clr_tx_abrt; /* 54: Clear TX_ABRT Interrupt */
|
||||
uint32_t reserved_58;
|
||||
uint32_t ic_clr_activity; /* 5c: Clear ACTIVITY Interrupt */
|
||||
uint32_t ic_clr_stop_det; /* 60: Clear STOP_DET Interrupt */
|
||||
uint32_t ic_clr_start_det; /* 64: Clear START_DET Interrupt */
|
||||
uint32_t reserved_68;
|
||||
volatile uint32_t ic_enable; /* 6c: Enable */
|
||||
volatile uint32_t ic_status; /* 70: Status */
|
||||
uint32_t ic_txflr; /* 74: Transmit FIFO Level */
|
||||
uint32_t ic_rxflr; /* 78: Receive FIFO Level */
|
||||
uint32_t ic_sda_hold; /* 7c: SDA Hold */
|
||||
volatile uint32_t ic_tx_abrt_source; /* 80: Transmit Abort Source */
|
||||
uint32_t reserved_84[6];
|
||||
volatile uint32_t ic_enable_status; /* 9c: Enable Status */
|
||||
uint32_t ic_fs_spklen; /* a0: SS and FS Spike Suppression Limit */
|
||||
} I2C_REGS;
|
||||
|
||||
#define IC_CON offsetof(I2C_REGS, ic_con)
|
||||
#define IC_TAR offsetof(I2C_REGS, ic_tar)
|
||||
#define IC_DATA_CMD offsetof(I2C_REGS, ic_data_cmd)
|
||||
#define IC_SS_SCL_HCNT offsetof(I2C_REGS, ic_ss_scl_hcnt)
|
||||
#define IC_SS_SCL_LCNT offsetof(I2C_REGS, ic_ss_scl_lcnt)
|
||||
#define IC_FS_SCL_HCNT offsetof(I2C_REGS, ic_fs_scl_hcnt)
|
||||
#define IC_FS_SCL_LCNT offsetof(I2C_REGS, ic_fs_scl_lcnt)
|
||||
#define IC_INTR_STAT offsetof(I2C_REGS, ic_intr_stat)
|
||||
#define IC_INTR_MASK offsetof(I2C_REGS, ic_intr_mask)
|
||||
#define IC_RAW_INTR_STAT offsetof(I2C_REGS, ic_raw_intr_stat)
|
||||
#define IC_RX_TL offsetof(I2C_REGS, ic_rx_tl)
|
||||
#define IC_TX_TL offsetof(I2C_REGS, ic_tx_tl)
|
||||
#define IC_CLR_INTR offsetof(I2C_REGS, ic_clr_intr)
|
||||
#define IC_CLR_RX_UNDER offsetof(I2C_REGS, ic_clr_rx_under)
|
||||
#define IC_CLR_RX_OVER offsetof(I2C_REGS, ic_clr_rx_over)
|
||||
#define IC_CLR_TX_OVER offsetof(I2C_REGS, ic_clr_tx_over)
|
||||
#define IC_CLR_RD_REQ offsetof(I2C_REGS, ic_clr_rd_req)
|
||||
#define IC_CLR_TX_ABRT offsetof(I2C_REGS, ic_clr_tx_abrt)
|
||||
#define IC_CLR_ACTIVITY offsetof(I2C_REGS, ic_clr_activity)
|
||||
#define IC_CLR_STOP_DET offsetof(I2C_REGS, ic_clr_stop_det)
|
||||
#define IC_CLR_START_DET offsetof(I2C_REGS, ic_clr_start_det)
|
||||
#define IC_ENABLE offsetof(I2C_REGS, ic_enable)
|
||||
#define IC_STATUS offsetof(I2C_REGS, ic_status)
|
||||
#define IC_TXFLR offsetof(I2C_REGS, ic_txflr)
|
||||
#define IC_RXFLR offsetof(I2C_REGS, ic_rxflr)
|
||||
#define IC_SDA_HOLD offsetof(I2C_REGS, ic_sda_hold)
|
||||
#define IC_TX_ABRT_SOURCE offsetof(I2C_REGS, ic_tx_abrt_source)
|
||||
#define IC_ENABLE_STATUS offsetof(I2C_REGS, ic_enable_status)
|
||||
#define IC_FS_SPKLEN offsetof(I2C_REGS, ic_fs_spklen)
|
||||
|
||||
/* 0x00: ic_con */
|
||||
#define IC_CON_RESTART_EN 0x00000020 /* Enable start/restart */
|
||||
#define IC_CON_10B 0x00000010 /* 10-bit addressing */
|
||||
#define IC_CON_7B 0 /* 7-bit addressing */
|
||||
#define IC_CON_SPEED 0x00000006 /* I2C bus speed */
|
||||
#define IC_CON_SPEED_400_KHz 0x00000004 /* Fast mode */
|
||||
#define IC_CON_SPEED_100_KHz 0x00000002 /* Standard mode */
|
||||
#define IC_CON_MASTER_MODE 0x00000001 /* Enable master mode */
|
||||
|
||||
/* 0x10: ic_data_cmd */
|
||||
#define IC_DATA_CMD_RESTART 0x00000400 /* Send restart before byte */
|
||||
#define IC_DATA_CMD_STOP 0x00000200 /* Send stop after byte */
|
||||
#define IC_DATA_CMD_CMD 0x00000100 /* Type of transaction */
|
||||
#define IC_DATA_CMD_READ IC_DATA_CMD_CMD
|
||||
#define IC_DATA_CMD_WRITE 0
|
||||
#define IC_DATA_CMD_DATA 0x000000ff /* Data byte */
|
||||
|
||||
/* 0x2c: ic_intr_stat
|
||||
* 0x30: ic_intr_mask
|
||||
* 0x34: ic_raw_intr_stat
|
||||
*/
|
||||
#define IC_INTR_START_DET 0x00000400 /* Start bit detected */
|
||||
#define IC_INTR_STOP_DET 0x00000200 /* Stop bit detected */
|
||||
#define IC_INTR_ACTIVITY 0x00000100 /* Activity detected */
|
||||
#define IC_INTR_TX_ABRT 0x00000040 /* Transmit abort */
|
||||
#define IC_INTR_RD_REQ 0x00000020 /* Read request */
|
||||
#define IC_INTR_TX_EMPTY 0x00000010 /* TX FIFO is empty */
|
||||
#define IC_INTR_TX_OVER 0x00000008 /* TX FIFO overflow */
|
||||
#define IC_INTR_RX_FULL 0x00000004 /* Receive FIFO is full */
|
||||
#define IC_INTR_RX_OVER 0x00000002 /* Receive FIFO overflow */
|
||||
#define IC_INTR_RX_UNDER 0x00000001 /* Receive FIFO underflow */
|
||||
|
||||
/* 0x6c: ic_enable
|
||||
* 0x9c: ic_enable_status
|
||||
*/
|
||||
#define IC_ENABLE_CONTROLLER 0x00000001 /* Enable the I2C controller */
|
||||
|
||||
/* 0x70: ic_status */
|
||||
#define IC_STATUS_MST_ACTIVITY 0x00000020 /* Master FSM activity */
|
||||
#define IC_STATUS_RFF 0x00000010 /* Receive FIFO completely full */
|
||||
#define IC_STATUS_RFNE 0x00000008 /* Receive FIFO not empty */
|
||||
#define IC_STATUS_TFE 0x00000004 /* Transmit FIFO completely empty */
|
||||
#define IC_STATUS_TFNF 0x00000002 /* Transmit FIFO not full */
|
||||
#define IC_STATUS_ACTIVITY 0x00000001 /* Activity */
|
||||
|
||||
#endif /* _QUARK_I2C_H_ */
|
||||
@@ -1,34 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _QUARK_IOMAP_H_
|
||||
#define _QUARK_IOMAP_H_
|
||||
|
||||
/*
|
||||
* Memory Mapped IO base addresses.
|
||||
*/
|
||||
|
||||
/* UART MMIO */
|
||||
#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE
|
||||
|
||||
/* I2C/GPIO Controller */
|
||||
#define I2C_BASE_ADDRESS 0xa0020000
|
||||
#define GPIO_BASE_ADDRESS 0xa0021000
|
||||
|
||||
/* Temporary BAR for SD controller */
|
||||
#define SD_BASE_ADDRESS 0xa0022000
|
||||
|
||||
/*
|
||||
* I/O port address space
|
||||
*/
|
||||
#define GPE0_BASE_ADDRESS 0x2000
|
||||
#define GPE0_SIZE 0x40
|
||||
|
||||
#define PM1BLK_BASE_ADDRESS 0x2040
|
||||
#define PM1BLK_SIZE 0x10
|
||||
|
||||
#define LEGACY_GPIO_BASE_ADDRESS 0x2080
|
||||
#define LEGACY_GPIO_SIZE 0x80
|
||||
|
||||
#define IO_ADDRESS_VALID 0x80000000
|
||||
|
||||
#endif /* _QUARK_IOMAP_H_ */
|
||||
@@ -1,17 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef SOC_INTEL_QUARK_NVS_H
|
||||
#define SOC_INTEL_QUARK_NVS_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
struct __packed global_nvs {
|
||||
uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
|
||||
uint8_t unused_was_pwrs; /* 0x4 - Power state (AC = 1) */
|
||||
|
||||
/* Required for future unified acpi_save_wake_source. */
|
||||
uint32_t pm1i;
|
||||
uint32_t gpei;
|
||||
};
|
||||
|
||||
#endif /* SOC_INTEL_QUARK_NVS_H */
|
||||
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Reference in New Issue
Block a user