diff --git a/FW/PlatformBuildLab/BaseToolsMax.tar.gz b/FW/PlatformBuildLab/BaseTools.tar.gz similarity index 100% rename from FW/PlatformBuildLab/BaseToolsMax.tar.gz rename to FW/PlatformBuildLab/BaseTools.tar.gz diff --git a/FW/PlatformBuildLab/Max/Max_Version_98.txt b/FW/PlatformBuildLab/Max/Max_Version_99.txt similarity index 67% rename from FW/PlatformBuildLab/Max/Max_Version_98.txt rename to FW/PlatformBuildLab/Max/Max_Version_99.txt index 6f69e990..b8796649 100644 --- a/FW/PlatformBuildLab/Max/Max_Version_98.txt +++ b/FW/PlatformBuildLab/Max/Max_Version_99.txt @@ -9,31 +9,24 @@ iii) Run the command "git checkout vUDK2017" iv) Enter folder "C:\MyWorkspace" - CryptoPkg Download: - - Follow the instructions found in the file "OpenSSL-HOWTO.txt" located in your - workspace (e.g. "C:\MyWorkspace\edk2\CryptoPkg\Library\OpensslLib\OpenSSL-HOWTO.txt") - to install the Openssl source code. - - 3) Checkout MinnowBoard Max Branch from GitHub with the following command. i) Run "git clone https://github.com/tianocore/edk2-platforms.git -b devel-MinnowBoardMax-UDK2017" ii) Enter folder edk2-platforms - iii) Run the command "git checkout 89b9edaa048fe6d39d53ca2a09d0ea87726f230e" + iii) Run the command "git checkout 423105b15de6dfd769eed56026fa3bc28eb349ef" iv) Enter folder "C:\MyWorkspace" - + 4) Checkout BaseTools binaries and copy them to BaseTools binary folder. i) Run "git clone https://github.com/tianocore/edk2-BaseTools-win32.git" ii) Enter folder edk2-BaseTools-win32 - iii) Run the command "git checkout 0e088c19ab31fccd1d2f55d9e4fe0314b57c0097" + iii) Run the command "git checkout 0e088c19ab31fccd1d2f55d9e4fe0314b57c0097" -5) Download MinnowBoard MAX 0.98 Binary Object Modules from http://firmware.intel.com/projects/minnowboard-max. - The "MinnowBoard_MAX-0.98-Binary.Objects.zip" file contains three additional +5) Download MinnowBoard MAX 0.99 Binary Object Modules from http://firmware.intel.com/projects/minnowboard-max. + The "MinnowBoard_MAX-0.99-Binary.Objects.zip" file contains three additional folders required for the full source tree. - IA32FamilyCpuPkg - Vlv2BinaryPkg - Vlv2MiscBinariesPkg + IA32FamilyCpuPkg + Vlv2BinaryPkg + Vlv2MiscBinariesPkg Create a new directory named "silicon" below WORKSPACE (e.g. "C:\MyWorkspace\silicon"). Unzip and copy the three folders to the "silicon" directory (e.g. "C:\MyWorkspace\silicon\"). @@ -43,13 +36,13 @@ SUMMARY Directory structure will be as follows after downloading source: C:/MyWorkspace --- \edk2 - (directories from vUDK2017) + (directories from vUDK2017) --- \edk2-platforms - Vlv2DeviceRefCodePkg - Vlv2TbltDeviceePkg <-------- invoke Build script Here + Vlv2DeviceRefCodePkg + Vlv2TbltDeviceePkg <-------- invoke Build script Here --- \edk2-BaseTools-win32 - (Windows Binary Base Tools) + (Windows Binary Base Tools) --- \silicon - (Step 5. above) + (Step 5. above) diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/AutoPlatformCFG.txt b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/AutoPlatformCFG.txt new file mode 100644 index 00000000..d5a3029d --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/AutoPlatformCFG.txt @@ -0,0 +1,2 @@ +DEFINE X64_CONFIG = TRUE +DEFINE ENBDT_PF_BUILD = TRUE diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosId.env b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosId.env index 0a826b30..35314db7 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosId.env +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosId.env @@ -24,6 +24,6 @@ BOARD_ID = MNW2MAX BOARD_REV = 1 BUILD_TYPE = D -VERSION_MAJOR = 0098 +VERSION_MAJOR = 0099 VERSION_MINOR = 01 BOARD_EXT = X64 diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdD.env b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdD.env index 2a36a93d..0e8f680a 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdD.env +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdD.env @@ -35,5 +35,5 @@ OEM_ID = I32 BUILD_TYPE = D BOARD_ID = BLAKCRB -VERSION_MAJOR = 0098 +VERSION_MAJOR = 0099 VERSION_MINOR = 01 diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdR.env b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdR.env index 82197634..1ba47cbc 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdR.env +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdR.env @@ -35,5 +35,5 @@ OEM_ID = I32 BUILD_TYPE = R BOARD_ID = BLAKCRB -VERSION_MAJOR = 0098 +VERSION_MAJOR = 0099 VERSION_MINOR = 01 diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdx64D.env b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdx64D.env index bfcefd64..ba9ce76f 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdx64D.env +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdx64D.env @@ -25,6 +25,6 @@ BOARD_REV = 1 OEM_ID = X64 BUILD_TYPE = D -VERSION_MAJOR = 0098 +VERSION_MAJOR = 0099 VERSION_MINOR = 01 BOARD_ID = BBAYCRB diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdx64R.env b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdx64R.env index 14266c54..4ccb2a05 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdx64R.env +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/BiosIdx64R.env @@ -25,6 +25,6 @@ BOARD_REV = 1 OEM_ID = X64 BUILD_TYPE = R -VERSION_MAJOR = 0098 +VERSION_MAJOR = 0099 VERSION_MINOR = 01 BOARD_ID = BBAYCRB diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h index f0319b6c..1490f761 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h @@ -1311,6 +1311,7 @@ typedef struct { UINT8 RtcBattery; UINT8 LpeAudioReportedByDSDT; UINT8 Uart1Int3511Com; // Report UART1 as COM with _HID INT3511 + CHAR16 SystemUuid[37]; } SYSTEM_CONFIGURATION; #pragma pack() diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsule - Copy.dsc b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsule - Copy.dsc new file mode 100644 index 00000000..eeb529e8 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsule - Copy.dsc @@ -0,0 +1,44 @@ +#/** @file +# Platform capsule description. +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + PLATFORM_NAME = Vlv2TbltDevicePkg + PLATFORM_GUID = EE87F258-6ECC-4415-B1D8-23771BEE26E7 + PLATFORM_VERSION = 0.1 + FLASH_DEFINITION = Vlv2TbltDevicePkg/PlatformCapsule.fdf + OUTPUT_DIRECTORY = Build/Vlv2TbltDevicePkg + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + +################################################################################################### +# +# Components Section - list of the modules and components that will be processed by compilation +# tools and the EDK II tools to generate PE32/PE32+/Coff image files. +# +# Note: The EDK II DSC file is not used to specify how compiled binary images get placed +# into firmware volume images. This section is just a list of modules to compile from +# source into UEFI-compliant binaries. +# It is the FDF file that contains information on combining binary files into firmware +# volume images, whose concept is beyond UEFI and is described in PI specification. +# Binary modules do not need to be listed in this section, as they should be +# specified in the FDF file. For example: Shell binary, FAT binary (Fat.efi), +# Logo (Logo.bmp), and etc. +# There may also be modules listed in this section that are not required in the FDF file, +# When a module listed here is excluded from FDF file, then UEFI-compliant binary will be +# generated for it, but the binary will not be put into any firmware volume. +# +################################################################################################### diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsule - Copy.fdf b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsule - Copy.fdf new file mode 100644 index 00000000..e126286e --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsule - Copy.fdf @@ -0,0 +1,63 @@ +## @file +# FDF file of Platform capsule. +# +# Copyright (c) 2018 Intel Corporation. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[FV.SystemFirmwareUpdateCargo] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE RAW = 14D83A59-A810-4556-8192-1C0A593C065C { # PcdEdkiiSystemFirmwareFileGuid + $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/Vlv.ROM + } + +FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid + $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/CAPSULEDISPATCHFV.Fv + } + +FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid + Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini + } + +[FmpPayload.FmpPayloadSystemFirmwareRsa2048] +IMAGE_HEADER_INIT_VERSION = 0x02 +IMAGE_TYPE_ID = 4096267b-da0a-42eb-b5eb-fef31d207cb4 # PcdSystemFmpCapsuleImageTypeIdGuid +IMAGE_INDEX = 0x1 +HARDWARE_INSTANCE = 0x0 +MONOTONIC_COUNT = 0x2 +CERTIFICATE_GUID = A7717414-C616-4977-9420-844712A735BF # RSA2048SHA256 + +FILE DATA = $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/SYSTEMFIRMWAREUPDATECARGO.Fv + +[Capsule.Vlv2] +CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid +CAPSULE_FLAGS = PersistAcrossReset,InitiateReset +CAPSULE_HEADER_SIZE = 0x20 +CAPSULE_HEADER_INIT_VERSION = 0x1 + +FMP_PAYLOAD = FmpPayloadSystemFirmwareRsa2048 + diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsuleGcc - Copy.dsc b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsuleGcc - Copy.dsc new file mode 100644 index 00000000..d5d72f44 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsuleGcc - Copy.dsc @@ -0,0 +1,44 @@ +#/** @file +# Platform capsule description. +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + PLATFORM_NAME = Vlv2TbltDevicePkg + PLATFORM_GUID = EE87F258-6ECC-4415-B1D8-23771BEE26E7 + PLATFORM_VERSION = 0.1 + FLASH_DEFINITION = Vlv2TbltDevicePkg/PlatformCapsuleGcc.fdf + OUTPUT_DIRECTORY = Build/Vlv2TbltDevicePkg + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + +################################################################################################### +# +# Components Section - list of the modules and components that will be processed by compilation +# tools and the EDK II tools to generate PE32/PE32+/Coff image files. +# +# Note: The EDK II DSC file is not used to specify how compiled binary images get placed +# into firmware volume images. This section is just a list of modules to compile from +# source into UEFI-compliant binaries. +# It is the FDF file that contains information on combining binary files into firmware +# volume images, whose concept is beyond UEFI and is described in PI specification. +# Binary modules do not need to be listed in this section, as they should be +# specified in the FDF file. For example: Shell binary, FAT binary (Fat.efi), +# Logo (Logo.bmp), and etc. +# There may also be modules listed in this section that are not required in the FDF file, +# When a module listed here is excluded from FDF file, then UEFI-compliant binary will be +# generated for it, but the binary will not be put into any firmware volume. +# +################################################################################################### diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsuleGcc - Copy.fdf b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsuleGcc - Copy.fdf new file mode 100644 index 00000000..98133015 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformCapsuleGcc - Copy.fdf @@ -0,0 +1,63 @@ +## @file +# FDF file of Platform capsule. +# +# Copyright (c) 2018 Intel Corporation. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[FV.SystemFirmwareUpdateCargo] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE RAW = 14D83A59-A810-4556-8192-1C0A593C065C { # PcdEdkiiSystemFirmwareFileGuid + $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/VLV.fd + } + +FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid + $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/CAPSULEDISPATCHFV.Fv + } + +FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid + Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfigGcc.ini + } + +[FmpPayload.FmpPayloadSystemFirmwareRsa2048] +IMAGE_HEADER_INIT_VERSION = 0x02 +IMAGE_TYPE_ID = 4096267b-da0a-42eb-b5eb-fef31d207cb4 # PcdSystemFmpCapsuleImageTypeIdGuid +IMAGE_INDEX = 0x1 +HARDWARE_INSTANCE = 0x0 +MONOTONIC_COUNT = 0x2 +CERTIFICATE_GUID = A7717414-C616-4977-9420-844712A735BF # RSA2048SHA256 + +FILE DATA = $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/SYSTEMFIRMWAREUPDATECARGO.Fv + +[Capsule.Vlv2] +CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid +CAPSULE_FLAGS = PersistAcrossReset,InitiateReset +CAPSULE_HEADER_SIZE = 0x20 +CAPSULE_HEADER_INIT_VERSION = 0x1 + +FMP_PAYLOAD = FmpPayloadSystemFirmwareRsa2048 + diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkg - Copy.dec b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkg - Copy.dec new file mode 100644 index 00000000..f0bcf081 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkg - Copy.dec @@ -0,0 +1,242 @@ +#/** @file +# Platform Package +# +# This package provides platform specific modules. +# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +# +#**/ + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = PlatformPkg + PACKAGE_GUID = 463B3B00-0D18-4a5f-90C0-D5B851D2574B + PACKAGE_VERSION = 0.1 + +[Includes] + . + Include + Include/Library + +[Ppis] + gPeiSpeakerInterfacePpiGuid = { 0x30ac275e, 0xbb30, 0x4b84, { 0xa1, 0xcd, 0x0a, 0xf1, 0x32, 0x2c, 0x89, 0xc0 }} + gPeiUsbControllerPpiGuid = { 0x3BC1F6DE, 0x693E, 0x4547, { 0xA3, 0x00, 0x21, 0x82, 0x3C, 0xA4, 0x20, 0xB2 }} + gPeiMfgMemoryTestPpiGuid = { 0xab294a92, 0xeaf5, 0x4cf3, { 0xab, 0x2b, 0x2d, 0x4b, 0xed, 0x4d, 0xb6, 0x3d }} + gPeiSha256HashPpiGuid = { 0x950e191b, 0x8524, 0x4f51, { 0x80, 0xa1, 0x5c, 0x4f, 0x1b, 0x03, 0xf3, 0x5c }} + +[Guids] + gEfiPlatformBootModeGuid = { 0xce845704, 0x1683, 0x4d38, { 0xa4, 0xf9, 0x7d, 0x0b, 0x50, 0x77, 0x57, 0x93 } } + gEfiPlatformInfoGuid = { 0x1e2acc41, 0xe26a, 0x483d, { 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x08, 0x7b } } + gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 } } + gPlatformModuleTokenSpaceGuid = { 0x69d13bf0, 0xaf91, 0x4d96, { 0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0 } } + gEfiSerialPortTokenSpaceGuid = { 0x5fad2389, 0x2bc7, 0x4bd2, { 0x83, 0xd3, 0x42, 0x9f, 0xb6, 0xae, 0xa3, 0x3f } } + gEfiIchTokenSpaceGuid = { 0xe38c11e3, 0x968f, 0x47b8, { 0xac, 0xef, 0xac, 0xc0, 0x69, 0x3d, 0xb9, 0xff } } + gEfiPchTokenSpaceGuid = { 0x89a1b278, 0xa1a1, 0x4df7, { 0xb1, 0x37, 0xde, 0x5a, 0xd7, 0xc4, 0x79, 0x13 } } + gEfiSioVariableGuid = { 0x560bf58a, 0x1e0d, 0x4d7e, { 0x95, 0x3f, 0x29, 0x80, 0xa2, 0x61, 0xe0, 0x31 } } + gProcessorProducerGuid = { 0x1bf06aea, 0x5bec, 0x4a8d, { 0x95, 0x76, 0x74, 0x9b, 0x09, 0x56, 0x2d, 0x30 } } + gEfiPowerOnHobGuid = { 0x0468a601, 0xc535, 0x46fd, { 0xa9, 0x5d, 0xbb, 0xab, 0x99, 0x1b, 0x17, 0x8c } } + gEfiPlatformCpuInfoGuid = { 0xbb9c7ab7, 0xb8d9, 0x4bf3, { 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc } } + gEfiBiosIdGuid = { 0xC3E36D09, 0x8294, 0x4b97, { 0xA8, 0x57, 0xD5, 0x28, 0x8F, 0xE3, 0x3E, 0x28 } } + gEfiPlatformBootModeGuid = { 0xce845704, 0x1683, 0x4d38, { 0xa4, 0xf9, 0x7d, 0x0b, 0x50, 0x77, 0x57, 0x93 } } + gEfiBoardFeaturesGuid = { 0x94b9e8ae, 0x8877, 0x479a, { 0x98, 0x42, 0xf5, 0x97, 0x4b, 0x82, 0xce, 0xd3 } } + gItkDataVarGuid = { 0x3812723d, 0x7e48, 0x4e29, { 0xbc, 0x27, 0xf5, 0xa3, 0x9a, 0xc9, 0x4e, 0xf1 } } + gDmiDataGuid = { 0x70e56c5e, 0x280c, 0x44b0, { 0xa4, 0x97, 0x09, 0x68, 0x1a, 0xbc, 0x37, 0x5e } } + gIdccDataHubGuid = { 0x788e1d9f, 0x1eab, 0x47d2, { 0xa2, 0xf3, 0x78, 0xca, 0xe8, 0x7d, 0x60, 0x12 } } + gEfiSetupVariableGuid = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } } + gEfiPlatformInfoGuid = { 0x1e2acc41, 0xe26a, 0x483d, { 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x08, 0x7b } } + gMfgModeVariableGuid = { 0xEF14FD78, 0x0793, 0x4e2b, { 0xAC, 0x6D, 0x06, 0x28, 0x47, 0xE0, 0x17, 0x91 } } + gEfiAcpiTableStorageGuid = { 0x7e374e25, 0x8e01, 0x4fee, { 0x87, 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd } } + gACPIOSFRMfgStringVariableGuid = { 0x72234213, 0x0fd7, 0x48a1, { 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x07, 0xfb, 0xcd } } + gACPIOSFRRefDataBlockVariableGuid = { 0x72234213, 0x0fd7, 0x48a1, { 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x07, 0xfb, 0xcd } } + gACPIOSFRModelStringVariableGuid = { 0xca1bcad9, 0xe021, 0x4547, { 0xa1, 0xb0, 0x5b, 0x22, 0xc7, 0xf6, 0x87, 0xf4 } } + gEfiAcpiTableStorageGuid = { 0x7e374e25, 0x8e01, 0x4fee, { 0x87, 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd } } + gEfiPciLanInfoGuid = { 0x0d9a1427, 0xe02a, 0x437d, { 0x92, 0x6b, 0xaa, 0x52, 0x1f, 0xd7, 0x22, 0xba } } + gEfiNormalSetupGuid = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } } + gFirmwareIdGuid = { 0x5e559c23, 0x1faa, 0x4ae1, { 0x8d, 0x4a, 0xc6, 0xcf, 0x02, 0x6c, 0x76, 0x6f } } + gBmpImageGuid = { 0x878AC2CC, 0x5343, 0x46F2, { 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } } + gOsSelectionVariableGuid = { 0x86843f56, 0x675d, 0x40a5, { 0x95, 0x30, 0xbc, 0x85, 0x83, 0x72, 0xf1, 0x03 } } + gFMPSampleUpdateImageInfoGuid = { 0xb9847c4e, 0xf5b6, 0x42dc, { 0xb6, 0xf4, 0xed, 0x44, 0x7, 0xb0, 0x67, 0x4c }} + gSystemFwClassGuid = { 0x819b858e, 0xc52c, 0x402f, { 0x80, 0xe1, 0x5b, 0x31, 0x1b, 0x6c, 0x19, 0x59 } } + gSystemRtcTimeVariableGuid = { 0x64c9937c, 0x2c8f, 0x4bd7, { 0xbf, 0x25, 0x83, 0x22, 0x34, 0xa2, 0xaf, 0xa1 } } + +[Protocols] + gEfiActiveBiosProtocolGuid = { 0xebbe2d1b, 0x1647, 0x4bda, { 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a } } + gEfiPlatformCpuProtocolGuid = { 0xbd26cdc9, 0xa092, 0x462a, { 0x87, 0x7a, 0x5a, 0xb6, 0xad, 0xce, 0x48, 0x12 } } + gDxePchPlatformPolicyProtocolGuid = { 0x4b0165a9, 0x61d6, 0x4e23, { 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 } } + gEfiTpmMpDriverProtocolGuid = { 0xde161cfe, 0x1e60, 0x42a1, { 0x8c, 0xc3, 0xee, 0x7e, 0xf0, 0x73, 0x52, 0x12 } } + gEfiLpcWpce791PolicyProtocolGuid = { 0xab2bee2f, 0xc1a6, 0x4399, { 0x85, 0x3d, 0xc0, 0x7c, 0x77, 0x4f, 0xfd, 0x0d } } + gUsbPolicyGuid = { 0xf617b358, 0x12cf, 0x414a, { 0xa0, 0x69, 0x60, 0x67, 0x7b, 0xda, 0x13, 0xb4 } } + gEfiSpeakerInterfaceProtocolGuid = { 0x400b4476, 0x3081, 0x11d6, { 0x87, 0xed, 0x00, 0x06, 0x29, 0x45, 0xc3, 0xb9 } } + gDxeVlvPlatformPolicyGuid = { 0x5bab88ba, 0xe0e2, 0x4674, { 0xb6, 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c, 0xd6 } } + gEfiSmbiosSlotPopulationGuid = { 0xef7bf7d6, 0xf8ff, 0x4a76, { 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 } } + gObservableProtocolGuid = { 0xe227c522, 0xd5fe, 0x4a53, { 0x87, 0xb1, 0x0f, 0xbe, 0x57, 0x0f, 0x98, 0xe9 } } + gEfiCk505ClockPlatformInfoGuid = { 0x3c485ea4, 0x449a, 0x46ce, { 0xbb, 0x08, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e } } + gEfiLpcWpc83627PolicyProtocolGuid = { 0xd3ecc567, 0x9fd5, 0x44c1, { 0x86, 0xcf, 0x5d, 0xa7, 0xa2, 0x4f, 0x4b, 0x5d } } + gEfiTcoResetProtocolGuid = { 0xa6a79162, 0xe325, 0x4c30, { 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3 } } + gEfiWatchdogTimerDriverProtocolGuid = { 0xd5b06d16, 0x2ea1, 0x4def, { 0x98, 0xd0, 0xa0, 0x5d, 0x40, 0x72, 0x84, 0x17 } } + gEfiPlatformIdeInitProtocolGuid = { 0x377c66a3, 0x8fe7, 0x4ee8, { 0x85, 0xb8, 0xf1, 0xa2, 0x82, 0x56, 0x9e, 0x3b } } + gEfiPciPlatformProtocolGuid = { 0x07d75280, 0x27d4, 0x4d69, { 0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41 } } + gEnhancedSpeedstepProtocolGuid = { 0x91a1ddcf, 0x5374, 0x4939, { 0x89, 0x51, 0xd7, 0x29, 0x3f, 0x1a, 0x78, 0x6f } } + gEfiAcpiSupportProtocolGuid = { 0xdbff9d55, 0x89b7, 0x46da, { 0xbd, 0xdf, 0x67, 0x7d, 0x3d, 0xc0, 0x24, 0x1d } } + gEfiAcpiS3SaveProtocolGuid = { 0x125f2de1, 0xfb85, 0x440c, { 0xa5, 0x4c, 0x4d, 0x99, 0x35, 0x8a, 0x8d, 0x38 } } + gEfiCpuIoProtocolGuid = { 0xB0732526, 0x38C8, 0x4b40, { 0x88, 0x77, 0x61, 0xC7, 0xB0, 0x6A, 0xAC, 0x45 } } + gPlatformGOPPolicyGuid = { 0xec2e931b, 0x3281, 0x48a5, { 0x81, 0x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d } } + gEfiGopDisplayBrightnessProtocolGuid = { 0x6ff23f1d, 0x877c, 0x4b1b, { 0x93, 0xfc, 0xf1, 0x42, 0xb2, 0xee, 0xa6, 0xa7 } } + gEfiUsbKeyboardConnectGuid = { 0xad9c4381, 0x1ede, 0x430c, { 0x8d, 0x42, 0x23, 0x76, 0x7c, 0x46, 0x5d, 0x52 } } + + +[PcdsFixedAtBuild] + gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageBase|0xFFF60000|UINT32|0x20000007 + gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageSize|0x00010000|UINT32|0x20000008 + gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageEventLogBase|0xFFF6C000|UINT32|0x30000007 + gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageEventLogSize|0x00002000|UINT32|0x30000008 + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|0xFFF80000|UINT32|0x20000004 + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize|0x00080000|UINT32|0x20000005 + gPlatformModuleTokenSpaceGuid.PcdFlashFvShellBase|0xFFF50000|UINT32|0x20000009 + gPlatformModuleTokenSpaceGuid.PcdFlashFvShellSize|0x00000000|UINT32|0x20000010 + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|0xFF800000|UINT32|0x20000001 + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize|0x00500000|UINT32|0x20000002 + gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x10000001 + gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x10000002 + gPlatformModuleTokenSpaceGuid.PcdFlashTestMenuBase|0xFF000000|UINT32|0x20000011 + gPlatformModuleTokenSpaceGuid.PcdFlashTestMenuSize|0x00010000|UINT32|0x20000012 + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|0xFFFA0000|UINT32|0x20000013 + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size|0x00040000|UINT32|0x20000014 + gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|0xFFF90000|UINT32|0x20000015 + gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize|0x00002000|UINT32|0x20000016 + gPlatformModuleTokenSpaceGuid.PcdFlashMicroCode2Address|0xFFF92000|UINT32|0x20000017 + gPlatformModuleTokenSpaceGuid.PcdFlashMicroCode2Size|0x0000C800|UINT32|0x20000018 + gPlatformModuleTokenSpaceGuid.PcdIFWISigBaseAddress|0x0F00|UINT32|0x20000019 + gPlatformModuleTokenSpaceGuid.PcdPBTNDisableInterval|0x01F4|UINT32|0x2000001A + gPlatformModuleTokenSpaceGuid.PcdTouchAttributes|2|UINT32|0x20000020 + gPlatformModuleTokenSpaceGuid.PcdTouchCIDString|"I2C05\\S004A"|VOID*|0x20000021 + gPlatformModuleTokenSpaceGuid.PcdFullIconFile |{ 0x69, 0x00, 0x39, 0x82, 0x30, 0xa6, 0x4b, 0x4c, 0x85, 0xfc, 0x95, 0xe9, 0x49, 0xc9, 0xf0, 0x76 }|VOID*|0x20000022 + gPlatformModuleTokenSpaceGuid.PcdSimpleIconFile |{ 0x4b, 0xf7, 0xee, 0x4b, 0x30, 0xa3, 0x49, 0x67, 0xa4, 0xad, 0xa4, 0xb1, 0xca, 0xe4, 0x4b, 0x0d }|VOID*|0x20000023 + gPlatformModuleTokenSpaceGuid.PcdCapitalLetterKeyboardFile|{ 0x82, 0x38, 0x75, 0xd8, 0x83, 0xa2, 0x4c, 0x37, 0xb6, 0xea, 0x04, 0xac, 0xc3, 0x06, 0x0f, 0x07 }|VOID*|0x20000024 + gPlatformModuleTokenSpaceGuid.PcdSmallLetterKeyboardFile |{ 0x4c, 0x66, 0x39, 0xa2, 0x09, 0x0e, 0x4d, 0xc9, 0x9f, 0x55, 0x0f, 0xcb, 0x72, 0x60, 0x26, 0x11 }|VOID*|0x20000025 + gPlatformModuleTokenSpaceGuid.PcdDigitKeyboardFile |{ 0x3f, 0xfe, 0x2c, 0x17, 0x92, 0x5d, 0x49, 0x7d, 0x87, 0x0a, 0x46, 0x14, 0xe4, 0x58, 0xd8, 0x5e }|VOID*|0x20000026 + gPlatformModuleTokenSpaceGuid.PcdSimpleKeyboardFile |{ 0x5c, 0xd4, 0xfc, 0x98, 0xbf, 0x79, 0x41, 0x10, 0xa2, 0xd3, 0x87, 0xbe, 0x82, 0xd0, 0x90, 0x52 }|VOID*|0x20000027 + + gPlatformModuleTokenSpaceGuid.PcdFlashSpidOffset|0x1000|UINT32|0x2000002A + gPlatformModuleTokenSpaceGuid.PcdFlashSpidSize|0x00001000|UINT32|0x2000002B + gPlatformModuleTokenSpaceGuid.PcdFlashEmOffset|0x3000|UINT32|0x2000002C + gPlatformModuleTokenSpaceGuid.PcdFlashEmSize|0x1000|UINT32|0x2000002D + + gEfiSerialPortTokenSpaceGuid.PcdSerialRegisterBase|0x3f8|UINT64|0x00000001 + gEfiSerialPortTokenSpaceGuid.PcdSerialBoudRate|115200|UINT32|0x00000002 + + gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress|0x400|UINT16|0x0000000B + + ## FFS filename to find the shell application. + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 0xC5, 0x15, 0x05, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }|VOID*|0x40000004 + + gEfiIchTokenSpaceGuid.PcdPeiIchUhciControllerIoPortBaseAddress|0x4000|UINT16|0x30000017 + gEfiIchTokenSpaceGuid.PcdPeiIchEhciControllerMemoryBaseAddress|0xFD000000|UINT32|0x30000019 + + + gPlatformModuleTokenSpaceGuid.PcdRamLogBaseAddress|0x20000|UINT32|0x00000013 + gPlatformModuleTokenSpaceGuid.PcdRamLogBaseLength|0x80000|UINT32|0x00000014 + gPlatformModuleTokenSpaceGuid.PcdRamLogBaseCarAddress|0xFEF86000|UINT32|0x00000015 + gPlatformModuleTokenSpaceGuid.PcdRamLogBaseCarLength|0x2000|UINT32|0x00000016 + + + #Pcd for Flash Update tool + gPlatformModuleTokenSpaceGuid.PcdFlashChipBase|0xFF800000|UINT32|0x40000001 + gPlatformModuleTokenSpaceGuid.PcdFlashChipSize|0x00800000|UINT32|0x40000002 + gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase|0xFF800000|UINT32|0x40000003 + gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize|0x00001000|UINT32|0x40000004 + gPlatformModuleTokenSpaceGuid.PcdTxeRomBase|0xFF801000|UINT32|0x40000009 + gPlatformModuleTokenSpaceGuid.PcdTxeRomSize|0x003FF000|UINT32|0x4000000A + gPlatformModuleTokenSpaceGuid.PcdBiosRomBase|0xFFC00000|UINT32|0x4000000B + gPlatformModuleTokenSpaceGuid.PcdBiosRomSize|0x00400000|UINT32|0x4000000C + gPlatformModuleTokenSpaceGuid.PcdFlashMinEraseSize|0x1000|UINT32|0x70000007 + +[PcdsPatchableInModule] + ## Provides the memory mapped base address of the BIOS Image Area. This area + # must be within the memory mapped region defined by the BIOS Flash Device + # Base Address and the BIOS Flash Device Size.

+ # The address must be within the BIOS Flash Device address space.
+ # + # @Prompt BIOS Image Area Base Address + # + # @Expression 0x80000011 | gPlatformModuleTokenSpaceGuid.PcdBiosImageBase >= gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress + # + gPlatformModuleTokenSpaceGuid.PcdBiosImageBase|0xFF800000|UINT32|0x20000050 + ## Provides the size of the BIOS Image Area.

+ # Valid size values must not exceed the BIOS Flash Device address space.
+ # + # @Prompt BIOS Image Area Size + # + # @Expression 0x80000012 | gPlatformModuleTokenSpaceGuid.PcdBiosImageSize <= gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize + # + gPlatformModuleTokenSpaceGuid.PcdBiosImageSize|0x800000|UINT32|0x20000051 + + + +[PcdsFeatureFlag] + ## This PCD specifies whether StatusCode is reported via ISA Serial port. + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|TRUE|BOOLEAN|0x00000020 + + ## This PCD specifies whether StatusCode is reported via USB Serial port. + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|TRUE|BOOLEAN|0x00000021 + + ## This PCD specifies whether StatusCode is reported via RAM. + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|FALSE|BOOLEAN|0x00000022 + + ## Platform BDS PCD to control whether to dispatch additional option rom, e.g.: PXE, AHCI + gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|TRUE|BOOLEAN|0x00000024 + + #new added feature for BIOS usb recovery + gEfiIchTokenSpaceGuid.PcdEhciRecoveryEnabled|TRUE|BOOLEAN|0x00000026 + + gPlatformModuleTokenSpaceGuid.PcdFeatureRecoveryDisabled|FALSE|BOOLEAN|0x20005004 + +[PcdsDynamic,PcdsDynamicEx] + gPlatformModuleTokenSpaceGuid.PcdInConfigMode|FALSE|BOOLEAN|0x80000001 + gPlatformModuleTokenSpaceGuid.PcdConnectUSBKeyboardonWaitForKeyStroke|FALSE|BOOLEAN|0x80000002 + gPlatformModuleTokenSpaceGuid.PcdEnableWatchdogSwSmiInputValue|0|UINT8|0x80000003 + ## Indicates platform to sync ESRT repository from FMP instances + gPlatformModuleTokenSpaceGuid.PcdEsrtSyncFmp|TRUE|BOOLEAN|0x80000004 + gPlatformModuleTokenSpaceGuid.PcdRtcPowerFailure|FALSE|BOOLEAN|0x80000005 + +# +#device firmware update support +# +#I2C and SPI support +[Protocols] + + gEfiMmioDeviceProtocolGuid = { 0x24486226, 0xf8c2, 0x41f5, { 0xb9, 0xdd, 0x78, 0x3e, 0x9e, 0x56, 0xde, 0xa0 } } + gEfiI2cBusConfigurationManagementProtocolGuid = { 0x75032015, 0xd156, 0x423e, { 0xbf, 0xa3, 0x7a, 0x65, 0xab, 0xa4, 0x71, 0x5 } } + gEfiI2cAcpiProtocolGuid = { 0xf30c2915, 0x5782, 0x4e6a, { 0xa8, 0x46, 0x5, 0xba, 0xbc, 0xe7, 0xb6, 0xa0 } } + gEfiI2cMasterProtocolGuid = { 0x578c315a, 0x68cf, 0x4e81, { 0xb5, 0xc6, 0x22, 0xdb, 0x40, 0xd0, 0x10, 0xbc } } + gEfiI2cHostProtocolGuid = { 0x70b221af, 0xfdff, 0x4fde, { 0x99, 0x68, 0x1a, 0xf6, 0x23, 0xa9, 0x56, 0xd9 } } + gEfiI2cBusProtocolGuid = { 0x9fa1b225, 0x3346, 0x461b, { 0xa0, 0x69, 0xed, 0x1, 0xb6, 0x73, 0xd2, 0x40 } } + gEfiI2cSlaveProtocolGuid = { 0xf2c1910e, 0xf5c9, 0x4b72, { 0xb2, 0x43, 0x6d, 0x59, 0x9, 0x6a, 0x79, 0xf0 } } + +# gEfiSpiAcpiProtocolGuid = { 0x9f49a879, 0x3d71, 0x42b3, { 0xa0, 0xad, 0xdd, 0xb1, 0xf3, 0x30, 0x10, 0xa3 } } +# gEfiSpiHostProtocolGuid = { 0x951b65e5, 0x8872, 0x41ed, { 0xad, 0x1d, 0xd5, 0x68, 0x1f, 0x4a, 0xf0, 0x33 } } +# gEfiSpiBusProtocolGuid = { 0x137b3044, 0xf6d7, 0x473e, { 0xa6, 0x25, 0x9f, 0xb9, 0x25, 0x5, 0xc1, 0x80 } } + +# gLpssDummyProtocolGuid = { 0xaf4cc162, 0xd41c, 0x455a, { 0xab, 0x45, 0x6d, 0xbc, 0xc1, 0xcd, 0x32, 0xf3 } } + gEfiSpiProtocolGuid = { 0x1156efc6, 0xea32, 0x4396, { 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 }} + gEfiGpioOperationProtocolGuid = { 0x38DDFE8F, 0x8991, 0x44AA, { 0x98, 0x89, 0x83, 0xF4, 0x91, 0x84, 0x65, 0xB0 }} + gEfiEsrtOperationProtocolGuid = { 0x4549AB47, 0x6E60, 0x4293, { 0xB9, 0x1D, 0x31, 0xB6, 0x10, 0xAD, 0x80, 0x56 }} + gExitPmAuthProtocolGuid = { 0xd088a413, 0xa70 , 0x4217, {0xba, 0x55, 0x9a, 0x3c, 0xb6, 0x5c, 0x41, 0xb3}} + +[Guids] + gEfiFwDisplayCapsuleGuid = { 0x3b8c8162, 0x188c, 0x46a4, { 0xae, 0xc9, 0xbe, 0x43, 0xf1, 0xd6, 0x56, 0x97 } } + gEfiFirmwareClassGuid = { 0xb122a262, 0x3551, 0x4f48, { 0x88, 0x92, 0x55, 0xf6, 0xc0, 0x61, 0x42, 0x90 } } + gEfiDFUVerGuid = { 0x0dc73aed, 0xcbf6, 0x4a25, { 0xa6, 0x8d, 0x59, 0xc8, 0x0f, 0x44, 0xc7, 0xc3 } } + gEfiEsrtTableGuid = { 0xb122a263, 0x3661, 0x4f68, { 0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80 } } + gEfiCapsuleCrashLogVarGuid = { 0xf3ff1468, 0x04ba, 0x4966, { 0x9f, 0xb2, 0xe4, 0xa7, 0x90, 0x05, 0x46, 0x50 } } + gEfiCapsuleCrashGuid = { 0x0e1d2972, 0x65af, 0x4ac1, { 0xbf, 0xa3, 0xce, 0xf4, 0xab, 0x0c, 0x38, 0xfe } } + gTpmDeviceInstanceTpm20PttPtpGuid = { 0x93d66f66, 0x55da, 0x4f03, { 0x9b, 0x5f, 0x32, 0xcf, 0x9e, 0x54, 0x3b, 0x3a } } \ No newline at end of file diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkg.fdf b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkg.fdf index f8f056b8..2d5d73a9 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkg.fdf +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkg.fdf @@ -1,1120 +1,1120 @@ -#/** @file -# FDF file of Platform. -# +#/** @file +# FDF file of Platform. +# # Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
-# -# This program and the accompanying materials are licensed and made available under -# the terms and conditions of the BSD License that accompanies this distribution. -# The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# -#**/ - -[Defines] -DEFINE FLASH_BASE = 0xFFC00000 #The base address of the 4Mb FLASH Device. -DEFINE FLASH_SIZE = 0x00400000 #The flash size in bytes of the 4Mb FLASH Device. -DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 4Mb FLASH Device. -DEFINE FLASH_NUM_BLOCKS = 0x400 #The number of blocks in 4Mb FLASH Device. -DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000 -DEFINE FLASH_AREA_SIZE = 0x00800000 - -DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000 -DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00040000 -DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFC00000 - -DEFINE FLASH_REGION_VPD_OFFSET = 0x00040000 -DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000 - -DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0007E000 -DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000 - - -DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00080000 -DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000 - -!if $(MINNOW2_FSP_BUILD) == TRUE -DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x000C0000 -DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000 -DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFCC0000 - -DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x00108000 -DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000 -DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFD08000 - -!endif - -DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00110000 -DEFINE FLASH_REGION_FVMAIN_SIZE = 0x00210000 - -DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x00320000 -DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x00070000 - -DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x00390000 -DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x00070000 - -################################################################################ -# -# FD Section -# The [FD] Section is made up of the definition statements and a -# description of what goes into the Flash Device Image. Each FD section -# defines one flash "device" image. A flash device image may be one of -# the following: Removable media bootable image (like a boot floppy -# image,) an Option ROM image (that would be "flashed" into an add-in -# card,) a System "Flash" image (that would be burned into a system's -# flash) or an Update ("Capsule") image that will be used to update and -# existing system flash. -# -################################################################################ -[FD.Vlv] -BaseAddress = $(FLASH_BASE)|gPlatformModuleTokenSpaceGuid.PcdBiosImageBase #The base address of the 3Mb FLASH Device. -Size = $(FLASH_SIZE)|gPlatformModuleTokenSpaceGuid.PcdBiosImageSize #The flash size in bytes of the 3Mb FLASH Device. -ErasePolarity = 1 -BlockSize = $(FLASH_BLOCK_SIZE) #The block size in bytes of the 3Mb FLASH Device. -NumBlocks = $(FLASH_NUM_BLOCKS) #The number of blocks in 3Mb FLASH Device. - -# -#Flash location override based on actual flash map -# -SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress = $(FLASH_AREA_BASE_ADDRESS) -SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize = $(FLASH_AREA_SIZE) - -!if $(MINNOW2_FSP_BUILD) == TRUE -# put below PCD value setting into dsc file -#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(FLASH_REGION_VLVMICROCODE_BASE) -#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(FLASH_REGION_VLVMICROCODE_SIZE) -#SET gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset = 0x60 -#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = $(FLASH_AREA_BASE_ADDRESS) -#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize = $(FLASH_AREA_SIZE) -#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase = $(FLASH_REGION_FSPBIN_BASE) -#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize = $(FLASH_REGION_FSPBIN_SIZE) - -!endif -################################################################################ -# -# Following are lists of FD Region layout which correspond to the locations of different -# images within the flash device. -# -# Regions must be defined in ascending order and may not overlap. -# -# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by -# the pipe "|" character, followed by the size of the region, also in hex with the leading -# "0x" characters. Like: -# Offset|Size -# PcdOffsetCName|PcdSizeCName -# RegionType -# Fv Size can be adjusted; FVMAIN_COMPACT can be reduced to 0x120000, and FV_RECOVERY can be enlarged to 0x80000 -# -################################################################################ - # - # CPU Microcodes - # - -$(FLASH_REGION_VLVMICROCODE_OFFSET)|$(FLASH_REGION_VLVMICROCODE_SIZE) -gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize -FV = MICROCODE_FV -$(FLASH_REGION_VPD_OFFSET)|$(FLASH_REGION_VPD_SIZE) -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize -#NV_VARIABLE_STORE -DATA = { - ## This is the EFI_FIRMWARE_VOLUME_HEADER - # ZeroVector [] - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - # FileSystemGuid: gEfiSystemNvDataFvGuid = - # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} - 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, - 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, - # FvLength: 0x80000 - 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, - #Signature "_FVH" #Attributes - 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, - #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision - 0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02, - #Blockmap[0]: 7 Blocks * 0x10000 Bytes / Block - 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, - #Blockmap[1]: End - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - ## This is the VARIABLE_STORE_HEADER -!if $(SECURE_BOOT_ENABLE) == TRUE - #Signature: gEfiAuthenticatedVariableGuid = - # { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} - 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, - 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, -!else - #Signature: gEfiVariableGuid = - # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} - 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, - 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, -!endif - #Size: 0x3E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x03DFB8 - # This can speed up the Variable Dispatch a bit. - 0xB8, 0xDF, 0x03, 0x00, - #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 - 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -} - - -$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE) -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize -#NV_FTW_WORKING -DATA = { - # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = - # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} - 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49, - 0xA0, 0xCE, 0x65, 0x0, 0xFD, 0x9F, 0x1B, 0x95, - - # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved - 0xE2, 0x33, 0xF2, 0x3, 0xFE, 0xFF, 0xFF, 0xFF, - # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 - 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -} - -$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE) -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize - -!if $(MINNOW2_FSP_BUILD) == TRUE - - $(FLASH_REGION_FSPBIN_OFFSET)|$(FLASH_REGION_FSPBIN_SIZE) - gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize - FILE = Vlv2MiscBinariesPkg/FspBinary/FvFsp.bin - - - $(FLASH_REGION_AZALIABIN_OFFSET)|$(FLASH_REGION_AZALIABIN_SIZE) - FILE = Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin - -!endif - - # - # Main Block - # -$(FLASH_REGION_FVMAIN_OFFSET)|$(FLASH_REGION_FVMAIN_SIZE) -gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize -FV = FVMAIN_COMPACT - - # - # FV Recovery#2 - # -$(FLASH_REGION_FV_RECOVERY2_OFFSET)|$(FLASH_REGION_FV_RECOVERY2_SIZE) -gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size -FV = FVRECOVERY2 - - # - # FV Recovery - # -$(FLASH_REGION_FV_RECOVERY_OFFSET)|$(FLASH_REGION_FV_RECOVERY_SIZE) -gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize -FV = FVRECOVERY - -################################################################################ -# -# FV Section -# -# [FV] section is used to define what components or modules are placed within a flash -# device file. This section also defines order the components and modules are positioned -# within the image. The [FV] section consists of define statements, set statements and -# module statements. -# -################################################################################ -[FV.MICROCODE_FV] -BlockSize = $(FLASH_BLOCK_SIZE) -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = FALSE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - -FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 { - $(OUTPUT_DIRECTORY)\$(TARGET)_$(TOOL_CHAIN_TAG)\$(DXE_ARCHITECTURE)\MicrocodeUpdates.bin -} - -################################################################################ -# -# FV Section -# -# [FV] section is used to define what components or modules are placed within a flash -# device file. This section also defines order the components and modules are positioned -# within the image. The [FV] section consists of define statements, set statements and -# module statements. -# -################################################################################ -[FV.FVRECOVERY2] -BlockSize = $(FLASH_BLOCK_SIZE) -FvAlignment = 16 #FV alignment and FV attributes setting. -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE -FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092 - - - -INF $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf - -!if $(MINNOW2_FSP_BUILD) == FALSE -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSmbusArpDisabled.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/VlvInitPeim.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchInitPeim.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSpiPeim.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmAccess.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmControl.inf -INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MpS3.inf -INF EdkCompatibilityPkg/Compatibility/AcpiVariableHobOnSmramReserveHobThunk/AcpiVariableHobOnSmramReserveHobThunk.inf -!endif - -INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf -!if $(TPM_ENABLED) == TRUE -INF SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf -INF SecurityPkg/Tcg/TcgPei/TcgPei.inf -INF SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf -!endif -!if $(FTPM_ENABLE) == TRUE -INF SecurityPkg/Tcg/TrEEPei/TrEEPei.inf #use PCD config -!endif -INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf - -!if $(ACPI50_ENABLE) == TRUE - INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf -!endif -!if $(PERFORMANCE_ENABLE) == TRUE -INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf -!endif - -[FV.FVRECOVERY] -BlockSize = $(FLASH_BLOCK_SIZE) -FvAlignment = 16 #FV alignment and FV attributes setting. -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE -FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270091 - - -!if $(MINNOW2_FSP_BUILD) == TRUE -INF IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf -!else -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SecCore.inf -!endif - -INF MdeModulePkg/Core/Pei/PeiMain.inf -!if $(MINNOW2_FSP_BUILD) == TRUE -INF Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf -INF IntelFspWrapperPkg/FspInitPei/FspInitPei.inf -!endif -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/CpuPeim.inf -INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf -INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf - +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] +DEFINE FLASH_BASE = 0xFFC00000 #The base address of the 4Mb FLASH Device. +DEFINE FLASH_SIZE = 0x00400000 #The flash size in bytes of the 4Mb FLASH Device. +DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 4Mb FLASH Device. +DEFINE FLASH_NUM_BLOCKS = 0x400 #The number of blocks in 4Mb FLASH Device. +DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000 +DEFINE FLASH_AREA_SIZE = 0x00800000 + +DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000 +DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00040000 +DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFC00000 + +DEFINE FLASH_REGION_VPD_OFFSET = 0x00040000 +DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000 + +DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0007E000 +DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000 + + +DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00080000 +DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000 + +!if $(MINNOW2_FSP_BUILD) == TRUE +DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x000C0000 +DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000 +DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFCC0000 + +DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x00108000 +DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000 +DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFD08000 + +!endif + +DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00110000 +DEFINE FLASH_REGION_FVMAIN_SIZE = 0x00210000 + +DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x00320000 +DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x00070000 + +DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x00390000 +DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x00070000 + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.Vlv] +BaseAddress = $(FLASH_BASE)|gPlatformModuleTokenSpaceGuid.PcdBiosImageBase #The base address of the 3Mb FLASH Device. +Size = $(FLASH_SIZE)|gPlatformModuleTokenSpaceGuid.PcdBiosImageSize #The flash size in bytes of the 3Mb FLASH Device. +ErasePolarity = 1 +BlockSize = $(FLASH_BLOCK_SIZE) #The block size in bytes of the 3Mb FLASH Device. +NumBlocks = $(FLASH_NUM_BLOCKS) #The number of blocks in 3Mb FLASH Device. + +# +#Flash location override based on actual flash map +# +SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress = $(FLASH_AREA_BASE_ADDRESS) +SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize = $(FLASH_AREA_SIZE) + +!if $(MINNOW2_FSP_BUILD) == TRUE +# put below PCD value setting into dsc file +#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(FLASH_REGION_VLVMICROCODE_BASE) +#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(FLASH_REGION_VLVMICROCODE_SIZE) +#SET gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset = 0x60 +#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = $(FLASH_AREA_BASE_ADDRESS) +#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize = $(FLASH_AREA_SIZE) +#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase = $(FLASH_REGION_FSPBIN_BASE) +#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize = $(FLASH_REGION_FSPBIN_SIZE) + +!endif +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# Fv Size can be adjusted; FVMAIN_COMPACT can be reduced to 0x120000, and FV_RECOVERY can be enlarged to 0x80000 +# +################################################################################ + # + # CPU Microcodes + # + +$(FLASH_REGION_VLVMICROCODE_OFFSET)|$(FLASH_REGION_VLVMICROCODE_SIZE) +gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize +FV = MICROCODE_FV +$(FLASH_REGION_VPD_OFFSET)|$(FLASH_REGION_VPD_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x80000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 7 Blocks * 0x10000 Bytes / Block + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if $(SECURE_BOOT_ENABLE) == TRUE + #Signature: gEfiAuthenticatedVariableGuid = + # { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + #Signature: gEfiVariableGuid = + # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + #Size: 0x3E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x03DFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xDF, 0x03, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + + +$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49, + 0xA0, 0xCE, 0x65, 0x0, 0xFD, 0x9F, 0x1B, 0x95, + + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x3, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +!if $(MINNOW2_FSP_BUILD) == TRUE + + $(FLASH_REGION_FSPBIN_OFFSET)|$(FLASH_REGION_FSPBIN_SIZE) + gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize + FILE = Vlv2MiscBinariesPkg/FspBinary/FvFsp.bin + + + $(FLASH_REGION_AZALIABIN_OFFSET)|$(FLASH_REGION_AZALIABIN_SIZE) + FILE = Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin + +!endif + + # + # Main Block + # +$(FLASH_REGION_FVMAIN_OFFSET)|$(FLASH_REGION_FVMAIN_SIZE) +gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize +FV = FVMAIN_COMPACT + + # + # FV Recovery#2 + # +$(FLASH_REGION_FV_RECOVERY2_OFFSET)|$(FLASH_REGION_FV_RECOVERY2_SIZE) +gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size +FV = FVRECOVERY2 + + # + # FV Recovery + # +$(FLASH_REGION_FV_RECOVERY_OFFSET)|$(FLASH_REGION_FV_RECOVERY_SIZE) +gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize +FV = FVRECOVERY + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.MICROCODE_FV] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = FALSE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 { + $(OUTPUT_DIRECTORY)\$(TARGET)_$(TOOL_CHAIN_TAG)\$(DXE_ARCHITECTURE)\MicrocodeUpdates.bin +} + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.FVRECOVERY2] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092 + + + +INF $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf + +!if $(MINNOW2_FSP_BUILD) == FALSE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSmbusArpDisabled.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/VlvInitPeim.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchInitPeim.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSpiPeim.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmAccess.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmControl.inf +INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MpS3.inf +INF EdkCompatibilityPkg/Compatibility/AcpiVariableHobOnSmramReserveHobThunk/AcpiVariableHobOnSmramReserveHobThunk.inf +!endif + +INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf +!if $(TPM_ENABLED) == TRUE +INF SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf +INF SecurityPkg/Tcg/TcgPei/TcgPei.inf +INF SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf +!endif +!if $(FTPM_ENABLE) == TRUE +INF SecurityPkg/Tcg/TrEEPei/TrEEPei.inf #use PCD config +!endif +INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + +!if $(ACPI50_ENABLE) == TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf +!endif +!if $(PERFORMANCE_ENABLE) == TRUE +INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf +!endif + +[FV.FVRECOVERY] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270091 + + +!if $(MINNOW2_FSP_BUILD) == TRUE +INF IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf +!else +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SecCore.inf +!endif + +INF MdeModulePkg/Core/Pei/PeiMain.inf +!if $(MINNOW2_FSP_BUILD) == TRUE +INF Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf +INF IntelFspWrapperPkg/FspInitPei/FspInitPei.inf +!endif +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/CpuPeim.inf +INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf +INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf -INF $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf - -!if $(MINNOW2_FSP_BUILD) == FALSE -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SeCUma.inf -!endif - -!if $(FTPM_ENABLE) == TRUE -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fTPMInitPeim.inf -!endif - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - INF SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf -!endif - -INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf - -!if $(CAPSULE_ENABLE) == TRUE -!if $(DXE_ARCHITECTURE) == X64 -INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf -INF MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf -!else -INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf -!endif -!endif - -!if $(MINNOW2_FSP_BUILD) == FALSE -!if $(PCIESC_ENABLE) == TRUE -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchEarlyInitPeim.inf -!endif -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MemoryInit.inf -!endif - -!if $(CAPSULE_ENABLE) - # FMP image decriptor -INF RuleOverride = FMP_IMAGE_DESC Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf -!endif - -[FV.FVMAIN] -BlockSize = $(FLASH_BLOCK_SIZE) -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE -FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5 - -APRIORI DXE { - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf - INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf - } - -FILE FREEFORM = C3E36D09-8294-4b97-A857-D5288FE33E28 { - SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITECTURE)/BiosId.bin - } +INF $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf + +!if $(MINNOW2_FSP_BUILD) == FALSE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SeCUma.inf +!endif + +!if $(FTPM_ENABLE) == TRUE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fTPMInitPeim.inf +!endif + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + INF SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf +!endif + +INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf + +!if $(CAPSULE_ENABLE) == TRUE +!if $(DXE_ARCHITECTURE) == X64 +INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf +INF MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf +!else +INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf +!endif +!endif + +!if $(MINNOW2_FSP_BUILD) == FALSE +!if $(PCIESC_ENABLE) == TRUE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchEarlyInitPeim.inf +!endif +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MemoryInit.inf +!endif + +!if $(CAPSULE_ENABLE) + # FMP image decriptor +INF RuleOverride = FMP_IMAGE_DESC Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +!endif + +[FV.FVMAIN] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5 + +APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + } + +FILE FREEFORM = C3E36D09-8294-4b97-A857-D5288FE33E28 { + SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITECTURE)/BiosId.bin + } FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) { SECTION RAW = MdeModulePkg/Logo/Logo.bmp } - - # - # EDK II Related Platform codes - # - - !if $(MINNOW2_FSP_BUILD) == TRUE - INF IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf - !endif - -INF MdeModulePkg/Core/Dxe/DxeMain.inf -INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf -!if $(ACPI50_ENABLE) == TRUE -INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf -INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf + + # + # EDK II Related Platform codes + # + + !if $(MINNOW2_FSP_BUILD) == TRUE + INF IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf + !endif + +INF MdeModulePkg/Core/Dxe/DxeMain.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf +!if $(ACPI50_ENABLE) == TRUE +INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf +INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf -!endif - - -INF IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf -INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf -INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf -INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf -INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf -INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MpCpu.inf -INF $(PLATFORM_PACKAGE)/Metronome/Metronome.inf -!if $(HTTP_BOOT_SUPPORT) == TRUE -INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf -INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf -INF MdeModulePkg/Application/UiApp/UiApp.inf -!else -INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf -!endif -INF MdeModulePkg/Universal/LoadFileOnFv2/LoadFileOnFv2.inf -INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf -INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf -INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf -INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf -INF IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf - -INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf -INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf -INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf -INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf -!if $(SECURE_BOOT_ENABLE) -INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf -!endif - -INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - -INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf -INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf -INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf -INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf - - -INF $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf - -!if $(DATAHUB_ENABLE) == TRUE -INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf -!endif -INF IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandlerDxe/DatahubStatusCodeHandlerDxe.inf -INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf - -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Dptf.inf - - # - # EDK II Related Silicon codes - # -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchS3SupportDxe.inf - -!if $(USE_HPET_TIMER) == TRUE -INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf -!else -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmartTimer.inf -!endif -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmControl.inf - -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmbusDxe.inf - -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/IntelPchLegacyInterrupt.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchReset.inf - -!if $(MINNOW2_FSP_BUILD) == FALSE -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitDxe.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitSmm.inf -!endif -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmiDispatcher.inf -!if $(PCIESC_ENABLE) == TRUE -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPcieSmm.inf -!endif - -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiRuntime.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPolicyInitDxe.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchBiosWriteProtect.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmAccess.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PciHostBridge.inf -!if $(MINNOW2_FSP_BUILD) == FALSE -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/VlvInitDxe.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/GraphicDxeInitSmm.inf -!else -INF IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.inf -INF Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf -!endif -!if $(MINNOW2_FSP_BUILD) == FALSE - !if $(SEC_ENABLE) == TRUE - INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/HeciDrv.inf - INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SeCPolicyInitDxe.inf - !endif -!endif -!if $(TPM_ENABLED) == TRUE -INF SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf -INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf -INF RuleOverride = DRIVER_ACPITABLE SecurityPkg/Tcg/TcgSmm/TcgSmm.inf -!endif -!if $(FTPM_ENABLE) == TRUE -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Tpm2DeviceSeCPei.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Tpm2DeviceSeCDxe.inf -INF SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf -INF SecurityPkg/Tcg/MemoryOverwriteRequestControlLock/TcgMorLockSmm.inf -INF SecurityPkg/Tcg/TrEEDxe/TrEEDxe.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/FtpmSmm.inf -!endif - -# -# EDK II Related Platform codes -# -INF $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf -INF $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf -INF $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf -INF $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf +!endif + + +INF IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf +INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MpCpu.inf +INF $(PLATFORM_PACKAGE)/Metronome/Metronome.inf +!if $(HTTP_BOOT_SUPPORT) == TRUE +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf +INF MdeModulePkg/Application/UiApp/UiApp.inf +!else +INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf +!endif +INF MdeModulePkg/Universal/LoadFileOnFv2/LoadFileOnFv2.inf +INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf +INF IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf + +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf +INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf +!if $(SECURE_BOOT_ENABLE) +INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf +!endif + +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf +INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf + + +INF $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf + +!if $(DATAHUB_ENABLE) == TRUE +INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf +!endif +INF IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandlerDxe/DatahubStatusCodeHandlerDxe.inf +INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Dptf.inf + + # + # EDK II Related Silicon codes + # +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchS3SupportDxe.inf + +!if $(USE_HPET_TIMER) == TRUE +INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf +!else +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmartTimer.inf +!endif +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmControl.inf + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmbusDxe.inf + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/IntelPchLegacyInterrupt.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchReset.inf + +!if $(MINNOW2_FSP_BUILD) == FALSE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitDxe.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitSmm.inf +!endif +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmiDispatcher.inf +!if $(PCIESC_ENABLE) == TRUE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPcieSmm.inf +!endif + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiRuntime.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPolicyInitDxe.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchBiosWriteProtect.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmAccess.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PciHostBridge.inf +!if $(MINNOW2_FSP_BUILD) == FALSE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/VlvInitDxe.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/GraphicDxeInitSmm.inf +!else +INF IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.inf +INF Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf +!endif +!if $(MINNOW2_FSP_BUILD) == FALSE + !if $(SEC_ENABLE) == TRUE + INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/HeciDrv.inf + INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SeCPolicyInitDxe.inf + !endif +!endif +!if $(TPM_ENABLED) == TRUE +INF SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf +INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf +INF RuleOverride = DRIVER_ACPITABLE SecurityPkg/Tcg/TcgSmm/TcgSmm.inf +!endif +!if $(FTPM_ENABLE) == TRUE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Tpm2DeviceSeCPei.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Tpm2DeviceSeCDxe.inf +INF SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf +INF SecurityPkg/Tcg/MemoryOverwriteRequestControlLock/TcgMorLockSmm.inf +INF SecurityPkg/Tcg/TrEEDxe/TrEEDxe.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/FtpmSmm.inf +!endif + +# +# EDK II Related Platform codes +# +INF $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf +INF $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf +INF $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf +INF $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf INF $(PLATFORM_PACKAGE)/PlatformRtcRuntimeDxe/PlatformRtcRuntimeDxe.inf -INF $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf -INF $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PlatformCpuPolicy.inf -INF $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf -INF $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf -!if $(GOP_DRIVER_ENABLE) == TRUE - INF $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf - FILE DRIVER = FF0C8745-3270-4439-B74F-3E45F8C77064 { - SECTION DXE_DEPEX_EXP = {gPlatformGOPPolicyGuid} - SECTION PE32 = Vlv2MiscBinariesPkg/GOP/7.2.1011/RELEASE_VS2008x86/$(DXE_ARCHITECTURE)/IntelGopDriver.efi - SECTION UI = "IntelGopDriver" -} -!endif - -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PnpDxe.inf - # - # SMM - # -INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf -INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf -INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf -INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf -INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf -INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf -INF $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PowerManagement2.inf -# INF Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/Smm/DigitalThermalSensor.inf -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/DigitalThermalSensor.inf - # - # ACPI - # -INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf -INF $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf -INF IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDxe.inf -INF RuleOverride = ACPITABLE2 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf - -INF RuleOverride = ACPITABLE $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf - -INF $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf - -INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf -INF MdeModulePkg/Universal/Acpi/SmmS3SaveState/SmmS3SaveState.inf - - # - # PCI - # -INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/ISPDxe.inf - - -# -# ISA -# -INF $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf -INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf -INF IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf -!if $(SOURCE_DEBUG_ENABLE) != TRUE -INF IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf -!endif -#INF IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf -#INF IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf - -# -# eMMC/SD Card -# -INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf -INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf -INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf - -# -# IDE/SCSI/AHCI -# -INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - -INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - -INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf -!if $(SATA_ENABLE) == TRUE -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SataController.inf -# - -# -INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf -INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf -!if $(SCSI_ENABLE) == TRUE -INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf -INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf -!endif -# -!endif -# Console -# -INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf -INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf -INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf -INF IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf -INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf -INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf -INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf -INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - # - # USB - # -!if $(USB_ENABLE) == TRUE -INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf -INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf -INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf -INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf -INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf -INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf -INF Vlv2TbltDevicePkg/Override/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf -!endif - - # - # ECP - # -INF EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf -INF EdkCompatibilityPkg/Compatibility/SmmBaseOnSmmBase2Thunk/SmmBaseOnSmmBase2Thunk.inf -INF EdkCompatibilityPkg/Compatibility/SmmBaseHelper/SmmBaseHelper.inf -INF EdkCompatibilityPkg/Compatibility/SmmAccess2OnSmmAccessThunk/SmmAccess2OnSmmAccessThunk.inf -INF EdkCompatibilityPkg/Compatibility/SmmControl2OnSmmControlThunk/SmmControl2OnSmmControlThunk.inf -INF EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf - # - # SMBIOS - # -INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf -INF $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf - -INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmbiosMemory.inf - - # - # Legacy Modules - # -INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf - -# -# FAT file system -# -FILE DRIVER = 961578FE-B6B7-44c3-AF35-6BC705CD2B1F { - SECTION PE32 = FatBinPkg/EnhancedFatDxe/$(EDK_DXE_ARCHITECTURE)/Fat.efi - } -# -# UEFI Shell And /or HTTP Boot -# -!if $(HTTP_BOOT_SUPPORT) == TRUE -FILE APPLICATION = 7C04A583-9E3E-4f1c-AD65-E05268D0B4D1 { -# SECTION PE32 = EdkShellBinPkg/FullShell/$(EDK_DXE_ARCHITECTURE)/Shell_Full.efi - SECTION PE32 = ShellBinPkg/UefiShell/$(EDK_DXE_ARCHITECTURE)/Shell.efi - } -!else -!if $(BUILD_NEW_SHELL) == TRUE -# FILE APPLICATION = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile) { -# SECTION PE32 = $(OUTPUT_DIRECTORY)/DEBUG_VS2010x86/X64/shell.efi -# } - INF ShellPkg/Application/Shell/Shell.inf - -!else -FILE APPLICATION = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile) { -# SECTION PE32 = EdkShellBinPkg/FullShell/$(EDK_DXE_ARCHITECTURE)/Shell_Full.efi - SECTION PE32 = ShellBinPkg/UefiShell/$(EDK_DXE_ARCHITECTURE)/Shell.efi - } - -!endif -!endif - - -!if $(GOP_DRIVER_ENABLE) == TRUE -FILE FREEFORM = 878AC2CC-5343-46F2-B563-51F89DAF56BA { - SECTION RAW = Vlv2MiscBinariesPkg/GOP/7.2.1011/VBT/MNW2/Vbt.bin - SECTION UI = "IntelGopVbt" -} -!endif - -# -# Network Modules -# -!if $(NETWORK_ENABLE) == TRUE - FILE DRIVER = 22DE1691-D65D-456a-993E-A253DD1F308C { - SECTION PE32 = Vlv2MiscBinariesPkg/UNDI/RtkUndiDxe/$(DXE_ARCHITECTURE)/RtkUndiDxe.efi - SECTION UI = "UNDI" - } - # 32-bit E7006X3.EFI UNDI driver is not available. - !if $(DXE_ARCHITECTURE) == X64 - FILE DRIVER = 0270D660-E7E2-4C6B-94B1-16B7FCD49351 { - SECTION PE32 = Vlv2MiscBinariesPkg/UNDI/I211PcieUndiDxe/$(DXE_ARCHITECTURE)/E7006X3.EFI - SECTION UI = "UNDI" - } - !endif - INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf - INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf - INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf - INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf - INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf - INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf - INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf - INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf - !if $(HTTP_BOOT_SUPPORT) == TRUE - INF NetworkPkg/HttpDxe/HttpDxe.inf - INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf - INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf - INF NetworkPkg/DnsDxe/DnsDxe.inf - !if $(NETWORK_TLS_ENABLE) == TRUE - INF NetworkPkg/TlsDxe/TlsDxe.inf - INF NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf - !endif - INF RuleOverride = DRIVER_ACPITABLE MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf - !endif - !if $(NETWORK_IP6_ENABLE) == TRUE - INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf - INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf - INF NetworkPkg/IpSecDxe/IpSecDxe.inf - INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf - INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf - !endif - !if $(NETWORK_IP6_ENABLE) == TRUE - INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf - INF NetworkPkg/TcpDxe/TcpDxe.inf - !else - INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf - INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf - !endif - !if $(NETWORK_VLAN_ENABLE) == TRUE - INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf - !endif - !if $(NETWORK_ISCSI_ENABLE) == TRUE - !if $(NETWORK_IP6_ENABLE) == TRUE - INF NetworkPkg/IScsiDxe/IScsiDxe.inf - !else - INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf - !endif - !endif -!endif - -!if $(CAPSULE_ENABLE) -INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf -!endif -!if $(CAPSULE_ENABLE) -INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf -!endif - -!if $(CAPSULE_ENABLE) -FILE FREEFORM = PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiRsa2048Sha256TestPublicKeyFileGuid) { - SECTION RAW = BaseTools/Source/Python/Rsa2048Sha256Sign/TestSigningPublicKey.bin - SECTION UI = "Rsa2048Sha256TestSigningPublicKey" - } -!endif - -[FV.FVMAIN_COMPACT] -BlockSize = $(FLASH_BLOCK_SIZE) -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - -FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { -!if $(LZMA_ENABLE) == TRUE -# LZMA Compress - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { - SECTION FV_IMAGE = FVMAIN - } -!else -!if $(DXE_COMPRESS_ENABLE) == TRUE -# Tiano Compress - SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { - SECTION FV_IMAGE = FVMAIN - } -!else -# No Compress - SECTION COMPRESS PI_NONE { - SECTION FV_IMAGE = FVMAIN - } -!endif -!endif - } - -[FV.SETUP_DATA] -BlockSize = $(FLASH_BLOCK_SIZE) -#NumBlocks = 0x10 -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - -!if $(CAPSULE_ENABLE) -[FV.CapsuleDispatchFv] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - -INF FILE_GUID=232393E2-185F-4212-A986-2B01F529EED9 USE=IA32 SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf -INF FILE_GUID=F1E68873-DA37-4AA0-A12F-F0F8EBA2B24E USE=X64 SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf - - -!endif - -################################################################################ -# -# Rules are use with the [FV] section's module INF type to define -# how an FFS file is created for a given INF file. The following Rule are the default -# rules for the different module type. User can add the customized rules to define the -# content of the FFS file. -# -################################################################################ -[Rule.Common.SEC] - FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { - PE32 PE32 Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi - RAW BIN Align = 16 |.com - } - -[Rule.Common.SEC.BINARY] - FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { - PE32 PE32 Align = 8 |.efi - RAW BIN Align = 16 |.com - } - -[Rule.Common.PEI_CORE] - FILE PEI_CORE = $(NAMED_GUID) { - PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.PEIM] - FILE PEIM = $(NAMED_GUID) { - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.PEIM.BINARY] - FILE PEIM = $(NAMED_GUID) { - PEI_DEPEX PEI_DEPEX Optional |.depex - PE32 PE32 Align = Auto |.efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.PEIM.BIOSID] - FILE PEIM = $(NAMED_GUID) { - RAW BIN BiosId.bin - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.USER_DEFINED.APINIT] - FILE RAW = $(NAMED_GUID) Fixed Align=4K { - RAW SEC_BIN |.com - } -#cjia 2011-07-21 -[Rule.Common.USER_DEFINED.LEGACY16] - FILE FREEFORM = $(NAMED_GUID) { - UI STRING="$(MODULE_NAME)" Optional - RAW BIN |.bin - } -#cjia - -[Rule.Common.USER_DEFINED.ASM16] - FILE FREEFORM = $(NAMED_GUID) { - UI STRING="$(MODULE_NAME)" Optional - RAW BIN |.com - } - -[Rule.Common.DXE_CORE] - FILE DXE_CORE = $(NAMED_GUID) { - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.UEFI_DRIVER] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.UEFI_DRIVER.BINARY] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional |.depex - PE32 PE32 |.efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.UEFI_DRIVER.NATIVE_BINARY] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.depex - PE32 PE32 |.efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.DXE_DRIVER] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.DXE_DRIVER.BINARY] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional |.depex - PE32 PE32 |.efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.DXE_DRIVER.DRIVER_ACPITABLE] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - RAW ACPI Optional |.acpi - RAW ASL Optional |.aml - } - -[Rule.Common.DXE_RUNTIME_DRIVER] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.DXE_RUNTIME_DRIVER.BINARY] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional |.depex - PE32 PE32 |.efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.DXE_SMM_DRIVER] - FILE SMM = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.DXE_SMM_DRIVER.BINARY] - FILE SMM = $(NAMED_GUID) { - SMM_DEPEX SMM_DEPEX |.depex - PE32 PE32 |.efi - RAW BIN Optional |.aml +INF $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf +INF $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PlatformCpuPolicy.inf +INF $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf +INF $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf +!if $(GOP_DRIVER_ENABLE) == TRUE + INF $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf + FILE DRIVER = FF0C8745-3270-4439-B74F-3E45F8C77064 { + SECTION DXE_DEPEX_EXP = {gPlatformGOPPolicyGuid} + SECTION PE32 = Vlv2MiscBinariesPkg/GOP/7.2.1011/RELEASE_VS2008x86/$(DXE_ARCHITECTURE)/IntelGopDriver.efi + SECTION UI = "IntelGopDriver" +} +!endif + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PnpDxe.inf + # + # SMM + # +INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf +INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf +INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf +INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf +INF $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PowerManagement2.inf +# INF Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/Smm/DigitalThermalSensor.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/DigitalThermalSensor.inf + # + # ACPI + # +INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf +INF $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf +INF IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDxe.inf +INF RuleOverride = ACPITABLE2 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf + +INF RuleOverride = ACPITABLE $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf + +INF $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf + +INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf +INF MdeModulePkg/Universal/Acpi/SmmS3SaveState/SmmS3SaveState.inf + + # + # PCI + # +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/ISPDxe.inf + + +# +# ISA +# +INF $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf +INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf +INF IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf +!if $(SOURCE_DEBUG_ENABLE) != TRUE +INF IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf +!endif +#INF IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf +#INF IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf + +# +# eMMC/SD Card +# +INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf +INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf +INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + +# +# IDE/SCSI/AHCI +# +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf +!if $(SATA_ENABLE) == TRUE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SataController.inf +# + +# +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf +!if $(SCSI_ENABLE) == TRUE +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf +!endif +# +!endif +# Console +# +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf +INF IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + # + # USB + # +!if $(USB_ENABLE) == TRUE +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF Vlv2TbltDevicePkg/Override/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf +!endif + + # + # ECP + # +INF EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf +INF EdkCompatibilityPkg/Compatibility/SmmBaseOnSmmBase2Thunk/SmmBaseOnSmmBase2Thunk.inf +INF EdkCompatibilityPkg/Compatibility/SmmBaseHelper/SmmBaseHelper.inf +INF EdkCompatibilityPkg/Compatibility/SmmAccess2OnSmmAccessThunk/SmmAccess2OnSmmAccessThunk.inf +INF EdkCompatibilityPkg/Compatibility/SmmControl2OnSmmControlThunk/SmmControl2OnSmmControlThunk.inf +INF EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf + # + # SMBIOS + # +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf +INF $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmbiosMemory.inf + + # + # Legacy Modules + # +INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf + +# +# FAT file system +# +FILE DRIVER = 961578FE-B6B7-44c3-AF35-6BC705CD2B1F { + SECTION PE32 = FatBinPkg/EnhancedFatDxe/$(EDK_DXE_ARCHITECTURE)/Fat.efi + } +# +# UEFI Shell And /or HTTP Boot +# +!if $(HTTP_BOOT_SUPPORT) == TRUE +FILE APPLICATION = 7C04A583-9E3E-4f1c-AD65-E05268D0B4D1 { +# SECTION PE32 = EdkShellBinPkg/FullShell/$(EDK_DXE_ARCHITECTURE)/Shell_Full.efi + SECTION PE32 = ShellBinPkg/UefiShell/$(EDK_DXE_ARCHITECTURE)/Shell.efi + } +!else +!if $(BUILD_NEW_SHELL) == TRUE +# FILE APPLICATION = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile) { +# SECTION PE32 = $(OUTPUT_DIRECTORY)/DEBUG_VS2010x86/X64/shell.efi +# } + INF ShellPkg/Application/Shell/Shell.inf + +!else +FILE APPLICATION = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile) { +# SECTION PE32 = EdkShellBinPkg/FullShell/$(EDK_DXE_ARCHITECTURE)/Shell_Full.efi + SECTION PE32 = ShellBinPkg/UefiShell/$(EDK_DXE_ARCHITECTURE)/Shell.efi + } + +!endif +!endif + + +!if $(GOP_DRIVER_ENABLE) == TRUE +FILE FREEFORM = 878AC2CC-5343-46F2-B563-51F89DAF56BA { + SECTION RAW = Vlv2MiscBinariesPkg/GOP/7.2.1011/VBT/MNW2/Vbt.bin + SECTION UI = "IntelGopVbt" +} +!endif + +# +# Network Modules +# +!if $(NETWORK_ENABLE) == TRUE + FILE DRIVER = 22DE1691-D65D-456a-993E-A253DD1F308C { + SECTION PE32 = Vlv2MiscBinariesPkg/UNDI/RtkUndiDxe/$(DXE_ARCHITECTURE)/RtkUndiDxe.efi + SECTION UI = "UNDI" + } + # 32-bit E7006X3.EFI UNDI driver is not available. + !if $(DXE_ARCHITECTURE) == X64 + FILE DRIVER = 0270D660-E7E2-4C6B-94B1-16B7FCD49351 { + SECTION PE32 = Vlv2MiscBinariesPkg/UNDI/I211PcieUndiDxe/$(DXE_ARCHITECTURE)/E7006X3.EFI + SECTION UI = "UNDI" + } + !endif + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + !if $(HTTP_BOOT_SUPPORT) == TRUE + INF NetworkPkg/HttpDxe/HttpDxe.inf + INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf + INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + INF NetworkPkg/DnsDxe/DnsDxe.inf + !if $(NETWORK_TLS_ENABLE) == TRUE + INF NetworkPkg/TlsDxe/TlsDxe.inf + INF NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf + !endif + INF RuleOverride = DRIVER_ACPITABLE MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + !endif + !if $(NETWORK_IP6_ENABLE) == TRUE + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + INF NetworkPkg/IpSecDxe/IpSecDxe.inf + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + !endif + !if $(NETWORK_IP6_ENABLE) == TRUE + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF NetworkPkg/TcpDxe/TcpDxe.inf + !else + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + !endif + !if $(NETWORK_VLAN_ENABLE) == TRUE + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + !endif + !if $(NETWORK_ISCSI_ENABLE) == TRUE + !if $(NETWORK_IP6_ENABLE) == TRUE + INF NetworkPkg/IScsiDxe/IScsiDxe.inf + !else + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf + !endif + !endif +!endif + +!if $(CAPSULE_ENABLE) +INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf +!endif +!if $(CAPSULE_ENABLE) +INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf +!endif + +!if $(CAPSULE_ENABLE) +FILE FREEFORM = PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiRsa2048Sha256TestPublicKeyFileGuid) { + SECTION RAW = BaseTools/Source/Python/Rsa2048Sha256Sign/TestSigningPublicKey.bin + SECTION UI = "Rsa2048Sha256TestSigningPublicKey" + } +!endif + +[FV.FVMAIN_COMPACT] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { +!if $(LZMA_ENABLE) == TRUE +# LZMA Compress + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } +!else +!if $(DXE_COMPRESS_ENABLE) == TRUE +# Tiano Compress + SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } +!else +# No Compress + SECTION COMPRESS PI_NONE { + SECTION FV_IMAGE = FVMAIN + } +!endif +!endif + } + +[FV.SETUP_DATA] +BlockSize = $(FLASH_BLOCK_SIZE) +#NumBlocks = 0x10 +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + +!if $(CAPSULE_ENABLE) +[FV.CapsuleDispatchFv] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +INF FILE_GUID=232393E2-185F-4212-A986-2B01F529EED9 USE=IA32 SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf +INF FILE_GUID=F1E68873-DA37-4AA0-A12F-F0F8EBA2B24E USE=X64 SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf + + +!endif + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + PE32 PE32 Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi + RAW BIN Align = 16 |.com + } + +[Rule.Common.SEC.BINARY] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + PE32 PE32 Align = 8 |.efi + RAW BIN Align = 16 |.com + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.PEIM.BINARY] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional |.depex + PE32 PE32 Align = Auto |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.PEIM.BIOSID] + FILE PEIM = $(NAMED_GUID) { + RAW BIN BiosId.bin + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED.APINIT] + FILE RAW = $(NAMED_GUID) Fixed Align=4K { + RAW SEC_BIN |.com + } +#cjia 2011-07-21 +[Rule.Common.USER_DEFINED.LEGACY16] + FILE FREEFORM = $(NAMED_GUID) { + UI STRING="$(MODULE_NAME)" Optional + RAW BIN |.bin + } +#cjia + +[Rule.Common.USER_DEFINED.ASM16] + FILE FREEFORM = $(NAMED_GUID) { + UI STRING="$(MODULE_NAME)" Optional + RAW BIN |.com + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.NATIVE_BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER.DRIVER_ACPITABLE] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_SMM_DRIVER] + FILE SMM = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_SMM_DRIVER.BINARY] + FILE SMM = $(NAMED_GUID) { + SMM_DEPEX SMM_DEPEX |.depex + PE32 PE32 |.efi + RAW BIN Optional |.aml RAW ASL Optional |.aml - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.DXE_SMM_DRIVER.DRIVER_ACPITABLE] - FILE SMM = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - RAW ACPI Optional |.acpi - RAW ASL Optional |.aml - } - -[Rule.Common.SMM_CORE] - FILE SMM_CORE = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.SMM_CORE.BINARY] - FILE SMM_CORE = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional |.depex - PE32 PE32 |.efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.UEFI_APPLICATION] - FILE APPLICATION = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.UEFI_APPLICATION.UI] - FILE APPLICATION = $(NAMED_GUID) { - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="Enter Setup" - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.USER_DEFINED] - FILE FREEFORM = $(NAMED_GUID) { - UI STRING="$(MODULE_NAME)" Optional - RAW BIN |.bin - } - -[Rule.Common.USER_DEFINED.ACPITABLE] - FILE FREEFORM = $(NAMED_GUID) { - RAW ACPI Optional |.acpi - RAW ASL Optional |.aml - } - -[Rule.Common.USER_DEFINED.ACPITABLE2] - FILE FREEFORM = $(NAMED_GUID) { - RAW ASL Optional |.aml - } - + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_SMM_DRIVER.DRIVER_ACPITABLE] + FILE SMM = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.SMM_CORE] + FILE SMM_CORE = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.SMM_CORE.BINARY] + FILE SMM_CORE = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.UI] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="Enter Setup" + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED] + FILE FREEFORM = $(NAMED_GUID) { + UI STRING="$(MODULE_NAME)" Optional + RAW BIN |.bin + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.USER_DEFINED.ACPITABLE2] + FILE FREEFORM = $(NAMED_GUID) { + RAW ASL Optional |.aml + } + [Rule.Common.USER_DEFINED.LOGO] FILE FREEFORM = $(NAMED_GUID) { RAW BIN |.bmp } -[Rule.Common.ACPITABLE] - FILE FREEFORM = $(NAMED_GUID) { - RAW ACPI Optional |.acpi - RAW ASL Optional |.aml - } - -[Rule.Common.PEIM.FMP_IMAGE_DESC] - FILE PEIM = $(NAMED_GUID) { - RAW BIN |.acpi - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } +[Rule.Common.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.PEIM.FMP_IMAGE_DESC] + FILE PEIM = $(NAMED_GUID) { + RAW BIN |.acpi + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgConfig.dsc b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgConfig.dsc index 2119e67d..598568d4 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgConfig.dsc +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgConfig.dsc @@ -1,105 +1,106 @@ -#/** @file -# platform configuration file. -# -# Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
-# -# This program and the accompanying materials are licensed and made available under -# the terms and conditions of the BSD License that accompanies this distribution. -# The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# -#**/ - -# -# TRUE is ENABLE. FASLE is DISABLE. -# - -# -# FSP selection -# -DEFINE MINNOW2_FSP_BUILD = FALSE - - -DEFINE SCSI_ENABLE = TRUE - - -# -# To enable extra configuration for clk gen -# -DEFINE CLKGEN_CONFIG_EXTRA_ENABLE=TRUE - -# -# Feature selection -# - -# -# Select system timer which is used to produce Timer Arch Protocol: -# TRUE - HPET timer is used. -# FALSE - 8254 timer is used. -# -DEFINE USE_HPET_TIMER = FALSE - - -# -# Feature selection -# - -DEFINE TPM_ENABLED = FALSE - -DEFINE ACPI50_ENABLE = TRUE -DEFINE PERFORMANCE_ENABLE = FALSE - - -DEFINE LFMA_ENABLE = FALSE # Load module at fixed address feature -DEFINE DXE_COMPRESS_ENABLE = TRUE -DEFINE DXE_CRC32_SECTION_ENABLE = TRUE -DEFINE SSE2_ENABLE = FALSE - -DEFINE SECURE_BOOT_ENABLE = TRUE -DEFINE USER_IDENTIFICATION_ENABLE = FALSE -DEFINE VARIABLE_INFO_ENABLE = FALSE -DEFINE S3_ENABLE = TRUE - -### Enable only if SOURCE_DEBUG_ENABLE = FALSE otherwise the flash space will overload. -### DEFINE CAPSULE_ENABLE = TRUE -DEFINE CAPSULE_ENABLE = FALSE -DEFINE CAPSULE_RESET_ENABLE = TRUE - -DEFINE GOP_DRIVER_ENABLE = TRUE -DEFINE DATAHUB_ENABLE = TRUE -DEFINE DATAHUB_STATUS_CODE_ENABLE = TRUE -DEFINE USB_ENABLE = TRUE - -DEFINE ISA_SERIAL_STATUS_CODE_ENABLE = TRUE -DEFINE USB_SERIAL_STATUS_CODE_ENABLE = FALSE -DEFINE RAM_SERIAL_STATUS_CODE_ENABLE = FALSE - -DEFINE ENBDT_S3_SUPPORT = TRUE - -DEFINE LZMA_ENABLE = TRUE -DEFINE S4_ENABLE = TRUE -DEFINE NETWORK_ENABLE = TRUE -DEFINE NETWORK_IP6_ENABLE = TRUE -DEFINE NETWORK_ISCSI_ENABLE = FALSE -DEFINE NETWORK_VLAN_ENABLE = FALSE - -DEFINE SATA_ENABLE = TRUE -DEFINE PCIESC_ENABLE = TRUE -DEFINE ESRT_ENABLE = TRUE - -# -# Enable source level debug default only if CAPSULE_ENABLE == FALSE -# - DEFINE SOURCE_DEBUG_ENABLE = FALSE -!if $(CAPSULE_ENABLE) == FALSE -!if $(SYMBOLIC_DEBUG) == TRUE - DEFINE SOURCE_DEBUG_ENABLE = TRUE -!endif -!endif - -DEFINE HTTP_BOOT_SUPPORT = FALSE -DEFINE NETWORK_TLS_ENABLE = FALSE +#/** @file +# platform configuration file. +# +# Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +# +# TRUE is ENABLE. FASLE is DISABLE. +# + +# +# FSP selection +# +DEFINE MINNOW2_FSP_BUILD = FALSE + + +DEFINE SCSI_ENABLE = TRUE + + +# +# To enable extra configuration for clk gen +# +DEFINE CLKGEN_CONFIG_EXTRA_ENABLE=TRUE + +# +# Feature selection +# + +# +# Select system timer which is used to produce Timer Arch Protocol: +# TRUE - HPET timer is used. +# FALSE - 8254 timer is used. +# +DEFINE USE_HPET_TIMER = FALSE + + +# +# Feature selection +# + +DEFINE TPM_ENABLED = FALSE + +DEFINE ACPI50_ENABLE = TRUE +DEFINE PERFORMANCE_ENABLE = FALSE + + +DEFINE LFMA_ENABLE = FALSE # Load module at fixed address feature +DEFINE DXE_COMPRESS_ENABLE = TRUE +DEFINE DXE_CRC32_SECTION_ENABLE = TRUE +DEFINE SSE2_ENABLE = FALSE + +DEFINE SECURE_BOOT_ENABLE = TRUE +DEFINE USER_IDENTIFICATION_ENABLE = FALSE +DEFINE VARIABLE_INFO_ENABLE = FALSE +DEFINE S3_ENABLE = TRUE + +### Enable only if SOURCE_DEBUG_ENABLE = FALSE otherwise the flash space will overload. +### DEFINE CAPSULE_ENABLE = TRUE +DEFINE CAPSULE_ENABLE = FALSE +DEFINE CAPSULE_RESET_ENABLE = TRUE + +DEFINE GOP_DRIVER_ENABLE = TRUE +DEFINE DATAHUB_ENABLE = TRUE +DEFINE DATAHUB_STATUS_CODE_ENABLE = TRUE +DEFINE USB_ENABLE = TRUE + +DEFINE ISA_SERIAL_STATUS_CODE_ENABLE = TRUE +DEFINE USB_SERIAL_STATUS_CODE_ENABLE = FALSE +DEFINE RAM_SERIAL_STATUS_CODE_ENABLE = FALSE + +DEFINE ENBDT_S3_SUPPORT = TRUE + +DEFINE LZMA_ENABLE = TRUE +DEFINE S4_ENABLE = TRUE +DEFINE NETWORK_ENABLE = TRUE +DEFINE NETWORK_IP6_ENABLE = TRUE +DEFINE NETWORK_ISCSI_ENABLE = FALSE +DEFINE NETWORK_VLAN_ENABLE = FALSE + +DEFINE SATA_ENABLE = TRUE +DEFINE PCIESC_ENABLE = TRUE +DEFINE ESRT_ENABLE = TRUE + +# +# Enable source level debug default only if CAPSULE_ENABLE == FALSE +# + DEFINE SOURCE_DEBUG_ENABLE = FALSE +!if $(CAPSULE_ENABLE) == FALSE +!if $(SYMBOLIC_DEBUG) == TRUE + DEFINE SOURCE_DEBUG_ENABLE = TRUE +!endif +!endif + +DEFINE HTTP_BOOT_SUPPORT = FALSE +DEFINE NETWORK_TLS_ENABLE = FALSE + diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgConfigCapsule.dsc b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgConfigCapsule.dsc deleted file mode 100644 index 0aa3a58f..00000000 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgConfigCapsule.dsc +++ /dev/null @@ -1,106 +0,0 @@ -#/** @file -# platform configuration file. -# -# Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
-# -# This program and the accompanying materials are licensed and made available under -# the terms and conditions of the BSD License that accompanies this distribution. -# The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# -#**/ - -# -# TRUE is ENABLE. FASLE is DISABLE. -# - -# -# FSP selection -# -DEFINE MINNOW2_FSP_BUILD = FALSE - - -DEFINE SCSI_ENABLE = TRUE - - -# -# To enable extra configuration for clk gen -# -DEFINE CLKGEN_CONFIG_EXTRA_ENABLE=TRUE - -# -# Feature selection -# - -# -# Select system timer which is used to produce Timer Arch Protocol: -# TRUE - HPET timer is used. -# FALSE - 8254 timer is used. -# -DEFINE USE_HPET_TIMER = FALSE - - -# -# Feature selection -# - -DEFINE TPM_ENABLED = FALSE - -DEFINE ACPI50_ENABLE = TRUE -DEFINE PERFORMANCE_ENABLE = FALSE - - -DEFINE LFMA_ENABLE = FALSE # Load module at fixed address feature -DEFINE DXE_COMPRESS_ENABLE = TRUE -DEFINE DXE_CRC32_SECTION_ENABLE = TRUE -DEFINE SSE2_ENABLE = FALSE - -DEFINE SECURE_BOOT_ENABLE = TRUE -DEFINE USER_IDENTIFICATION_ENABLE = FALSE -DEFINE VARIABLE_INFO_ENABLE = FALSE -DEFINE S3_ENABLE = TRUE - -### Enable only if SOURCE_DEBUG_ENABLE = FALSE otherwise the flash space will overload. -### DEFINE CAPSULE_ENABLE = TRUE -DEFINE CAPSULE_ENABLE = TRUE -DEFINE CAPSULE_RESET_ENABLE = TRUE - -DEFINE GOP_DRIVER_ENABLE = TRUE -DEFINE DATAHUB_ENABLE = TRUE -DEFINE DATAHUB_STATUS_CODE_ENABLE = TRUE -DEFINE USB_ENABLE = TRUE - -DEFINE ISA_SERIAL_STATUS_CODE_ENABLE = TRUE -DEFINE USB_SERIAL_STATUS_CODE_ENABLE = FALSE -DEFINE RAM_SERIAL_STATUS_CODE_ENABLE = FALSE - -DEFINE ENBDT_S3_SUPPORT = TRUE - -DEFINE LZMA_ENABLE = TRUE -DEFINE S4_ENABLE = TRUE -DEFINE NETWORK_ENABLE = TRUE -DEFINE NETWORK_IP6_ENABLE = TRUE -DEFINE NETWORK_ISCSI_ENABLE = FALSE -DEFINE NETWORK_VLAN_ENABLE = FALSE - -DEFINE SATA_ENABLE = TRUE -DEFINE PCIESC_ENABLE = TRUE -DEFINE ESRT_ENABLE = TRUE - -# -# Enable source level debug default only if CAPSULE_ENABLE == FALSE -# - DEFINE SOURCE_DEBUG_ENABLE = FALSE -!if $(CAPSULE_ENABLE) == FALSE -!if $(SYMBOLIC_DEBUG) == TRUE - DEFINE SOURCE_DEBUG_ENABLE = TRUE -!endif -!endif - -DEFINE HTTP_BOOT_SUPPORT = FALSE -DEFINE NETWORK_TLS_ENABLE = FALSE - diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgX64.dsc b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgX64.dsc index db44c648..68ffbe7e 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgX64.dsc +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgX64.dsc @@ -1,1881 +1,1882 @@ -#/** @file -# Platform description. -# -# Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
-# -# This program and the accompanying materials are licensed and made available under -# the terms and conditions of the BSD License that accompanies this distribution. -# The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# -#**/ - -################################################################################ -# -# Defines Section - statements that will be processed to create a Makefile. -# -################################################################################ -[Defines] - PLATFORM_NAME = Vlv2TbltDevicePkg - PLATFORM_GUID = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90 - PLATFORM_VERSION = 0.1 - DSC_SPECIFICATION = 0x00010005 - - # - # Set platform specific package/folder name, same as passed from PREBUILD script. - # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package build folder - # DEFINE only takes effect at R9 DSC and FDF. - # - DEFINE PLATFORM_PACKAGE = Vlv2TbltDevicePkg - DEFINE PLATFORM_RC_PACKAGE = Vlv2DeviceRefCodePkg - DEFINE PLATFORM_BINARY_PACKAGE = Vlv2BinaryPkg - OUTPUT_DIRECTORY = Build/$(PLATFORM_PACKAGE) - SUPPORTED_ARCHITECTURES = IA32|X64 - BUILD_TARGETS = DEBUG|RELEASE - SKUID_IDENTIFIER = DEFAULT - - DEFINE CPU_ARCH =ValleyView2 - DEFINE PROJECT_SC_FAMILY =IntelPch - DEFINE PROJECT_SC_ROOT =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/SouthCluster - DEFINE PROJECT_VLV_ROOT =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/NorthCluster - - DEFINE RC_BINARY_RELEASE = TRUE - # - # Platform On/Off features are defined here - # - # - # Platform Support:: Set only one token except Crestview Hills - # - # 3.BayleyBay - # ENBDT_PF_ENABLE = TRUE - # - !include $(PLATFORM_PACKAGE)/AutoPlatformCFG.txt - !include $(PLATFORM_PACKAGE)/PlatformPkgConfig.dsc - -!if $(X64_CONFIG) == TRUE - DEFINE DXE_ARCHITECTURE = X64 - DEFINE EDK_DXE_ARCHITECTURE = X64 - DEFINE UNDI_DXE_ARCHITECTURE = 64 -!else - DEFINE DXE_ARCHITECTURE = IA32 - DEFINE EDK_DXE_ARCHITECTURE = Ia32 - DEFINE UNDI_DXE_ARCHITECTURE = 32 -!endif - - FLASH_DEFINITION = $(PLATFORM_PACKAGE)/PlatformPkg.fdf -!if $(LFMA_ENABLE) == TRUE - FIX_LOAD_TOP_MEMORY_ADDRESS = 0xFFFFFFFFFFFFFFFF - DEFINE TOP_MEMORY_ADDRESS = 0xFFFFFFFFFFFFFFFF -!else - FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0 - DEFINE TOP_MEMORY_ADDRESS = 0x0 -!endif - - DEFINE PLATFORM_PCIEXPRESS_BASE = 0E0000000 - - DEFINE SEC_ENABLE = FALSE - DEFINE SEC_DEBUG_INFO_ENABLE = FALSE - DEFINE FTPM_ENABLE = FALSE - -################################################################################ -# -# SKU Identification section - list of all SKU IDs supported by this -# Platform. -# -################################################################################ -[SkuIds] - 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required. - -################################################################################ -# -# Library Class section - list of all Library Classes needed by this Platform. -# -################################################################################ -[LibraryClasses.common] - # - # Entry point - # - PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf - PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf - DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf - UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf - UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf - DxeSmmDriverEntryPoint|IntelFrameworkPkg/Library/DxeSmmDriverEntryPoint/DxeSmmDriverEntryPoint.inf -!if $(HTTP_BOOT_SUPPORT) == TRUE - TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf - Tcg2PhysicalPresenceLib|SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.inf - TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull.inf - Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibNull.inf - Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.inf - TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf -!endif - - # - # Basic - # - BaseLib|MdePkg/Library/BaseLib/BaseLib.inf -!if $(SSE2_ENABLE) == TRUE - BaseMemoryLib|MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2.inf -!else - BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf -!endif - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf - IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf - PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf - PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf - CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf - PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf - PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf -!if $(RC_BINARY_RELEASE) == TRUE - PchPlatformLib|Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf -!endif - PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf - # - # UEFI & PI - # - UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf - UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf - UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf - UefiLib|MdePkg/Library/UefiLib/UefiLib.inf - HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf - UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf - DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf - UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf - PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf - PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf - UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf - UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf - GenericBdsLib|$(PLATFORM_PACKAGE)/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf - PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf - NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf - DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf - FlashDeviceLib|$(PLATFORM_PACKAGE)/Library/FlashDeviceLib/FlashDeviceLib.inf - # - # Framework - # -!if $(S3_ENABLE) == TRUE - S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf -!else - S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf -!endif - S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf - S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf - SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf - - # - # Generic Modules - # -!if $(USB_ENABLE) == TRUE - UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf -!endif -!if $(SCSI_ENABLE) == TRUE - UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf -!endif -!if $(NETWORK_ENABLE) == TRUE - NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf - IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf - UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf - TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf - DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf -!if $(HTTP_BOOT_SUPPORT) == TRUE - HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf - PlatformBootManagerLib | $(PLATFORM_PACKAGE)/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf - BootLogoLib | MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf -!endif -!endif -!if $(S3_ENABLE) == TRUE - S3Lib|IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf -!endif - - OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf - -!if $(CAPSULE_ENABLE) == TRUE - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf -!else - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf -!endif - - EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf - FmpAuthenticationLib|MdeModulePkg/Library/FmpAuthenticationLibNull/FmpAuthenticationLibNull.inf - IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf - PlatformFlashAccessLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.inf - - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf - - LanguageLib|EdkCompatibilityPkg/Compatibility/Library/UefiLanguageLib/UefiLanguageLib.inf - SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf - SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf - IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf - DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf - - # - # CPU - # - MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf - LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf - CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf - - # - # ICH - # - SmbusLib|$(PLATFORM_PACKAGE)/Library/SmbusLib/SmbusLib.inf - SmmLib|$(PLATFORM_PACKAGE)/Library/PchSmmLib/PchSmmLib.inf - - # - # Platform - # - TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf - ResetSystemLib|$(PLATFORM_PACKAGE)/Library/ResetSystemLib/ResetSystemLib.inf - - PlatformCmosLib|$(PLATFORM_PACKAGE)/Library/PlatformCmosLib/PlatformCmosLib.inf - - # - # Misc - # - MonoStatusCodeLib|$(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf -!if $(TARGET) == RELEASE - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf -!else - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf -!endif - - PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf -!if $(TPM_ENABLED) == TRUE - TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf - Tpm12CommandLib|SecurityPkg/Library/Tpm12CommandLib/Tpm12CommandLib.inf - Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm.inf - -!endif - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf - DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf - PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf - SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf - DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf -!else - PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf - DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf -!endif - - # - # CryptLib - # -!if $(TPM_ENABLED) == TRUE - IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf - OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf -!endif - - BiosIdLib|$(PLATFORM_PACKAGE)/Library/BiosIdLib/BiosIdLib.inf - CpuIA32Lib|$(PLATFORM_PACKAGE)/Library/CpuIA32Lib/CpuIA32Lib.inf - - StallSmmLib|$(PLATFORM_PACKAGE)/Library/StallSmmLib/StallSmmLib.inf - -!if $(SECURE_BOOT_ENABLE) == TRUE - OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf - IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf - PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf - TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf - AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf -!else - TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf - AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf -!endif - VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf -!if $(RC_BINARY_RELEASE) == TRUE - I2cLib|Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf -!endif - ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf - ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf - FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf -!if $(FTPM_ENABLE) == TRUE - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf - OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf - IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf -!endif - TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf - TrEEPhysicalPresenceLib|Vlv2TbltDevicePkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.inf -!if $(FTPM_ENABLE) == TRUE - TrEEPpVendorLib|SecurityPkg/Library/TrEEPpVendorLibNull/TrEEPpVendorLibNull.inf -!endif - - - Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf -!if $(MINNOW2_FSP_BUILD) == TRUE - FspApiLib|IntelFspWrapperPkg/Library/BaseFspApiLib/BaseFspApiLib.inf - FspPlatformInfoLib|IntelFspWrapperPkg/Library/BaseFspPlatformInfoLibSample/BaseFspPlatformInfoLibSample.inf - FspPlatformSecLib|Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf - FspHobProcessLib|Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf -!endif - -[LibraryClasses.IA32.SEC] -!if $(PERFORMANCE_ENABLE) == TRUE - PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf -!endif - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - -[LibraryClasses.IA32.PEIM, LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.SEC] - # - # PEI phase common - # - - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf - MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf - ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf - MultiPlatformLib|$(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPlatformLib.inf - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf - - -!if $(PERFORMANCE_ENABLE) == TRUE - PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf - TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf -!endif - -!if $(TARGET) == RELEASE - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf -!else - DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf - SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf -!endif - - LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf - HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterPei.inf -!if $(SOURCE_DEBUG_ENABLE) == TRUE - PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf - DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf - SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf - DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf -!else - PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf - DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf -!endif - - !if $(MINNOW2_FSP_BUILD) == TRUE - PlatformFspLib|Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf - !endif -!if $(FTPM_ENABLE) == TRUE - Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2DeviceLibSeC.inf -!endif - -[LibraryClasses.IA32] - HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - !if $(TPM_ENABLED) == TRUE - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf - !endif - - !if $(SECURE_BOOT_ENABLE) == TRUE - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf - !endif - -[LibraryClasses.X64] - # - # DXE phase common - # - HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf - - TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf -!if $(TPM_ENABLED) == TRUE - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf -!endif - - LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf - EfiRegTableLib|$(PLATFORM_PACKAGE)/Library/EfiRegTableLib/EfiRegTableLib.inf - -!if $(SECURE_BOOT_ENABLE) == TRUE - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf -!endif - - HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterDxe.inf - -[LibraryClasses.X64.DXE_DRIVER] - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf - CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf -!if $(PERFORMANCE_ENABLE) == TRUE - PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf - TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf -!endif - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf -!endif - -[LibraryClasses.X64.DXE_CORE] - HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf - MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf -!if $(PERFORMANCE_ENABLE) == TRUE - PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf - TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf -!endif - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf -!endif - -[LibraryClasses.X64.DXE_SMM_DRIVER] - SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf - MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf - LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf - PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf - SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf - SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf - - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf - !if $(TARGET) != RELEASE - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - !endif - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf - TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf -!endif - CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf - -[LibraryClasses.X64.SMM_CORE] - MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf - SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf - SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf - SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf - -!if $(TPM_ENABLED) == TRUE - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf -!endif - - PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf - -!if $(TARGET) != RELEASE - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf -!endif - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf - TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf -!endif - -[LibraryClasses.X64.DXE_RUNTIME_DRIVER] - ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf -!if $(SECURE_BOOT_ENABLE) == TRUE - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf -!endif -!if $(TPM_ENABLED) == TRUE - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf -!endif - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf -!endif - -!if $(CAPSULE_ENABLE) == TRUE - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf -!endif - -[LibraryClasses.common.UEFI_DRIVER] - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf -!endif - -[LibraryClasses.X64.UEFI_APPLICATION] - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf -!endif - - -################################################################################ -# -# Library Section - list of all EDK/Framework libraries -# -################################################################################ -[Libraries.common] - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/BaseLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseMemoryLib/BaseMemoryLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePrintLib/BasePrintLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseDebugLibNull/BaseDebugLibNull.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciCf8Lib/BasePciCf8Lib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciExpressLib/BasePciExpressLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibCf8/BasePciLibCf8.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffLib/BasePeCoffLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/SmmRuntimeDxeReportStatusCodeLib/SmmRuntimeDxeReportStatusCodeLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiHobLib/PeiHobLib.inf - EdkCompatibilityPkg/Foundation/Ppi/EdkPpiLib.inf - EdkCompatibilityPkg/Foundation/Library/Pei/PeiLib/PeiLib.inf - EdkCompatibilityPkg/Compatibility/Library/UefiLanguageLib/UefiLanguageLib.inf - EdkCompatibilityPkg/Foundation/Guid/EdkGuidLib.inf - EdkCompatibilityPkg/Foundation/Efi/Protocol/EfiProtocolLib.inf - EdkCompatibilityPkg/Foundation/Library/Dxe/EfiDriverLib/EfiDriverLib.inf - EdkCompatibilityPkg/Foundation/Protocol/EdkProtocolLib.inf - EdkCompatibilityPkg/Foundation/Framework/Protocol/EdkFrameworkProtocolLib.inf -[Libraries.IA32] - EdkCompatibilityPkg/Foundation/Efi/Guid/EfiGuidLib.inf - EdkCompatibilityPkg/Foundation/Framework/Guid/EdkFrameworkGuidLib.inf - EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/EfiCommonLib.inf - EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/CpuIA32Lib.inf - EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib.inf - EdkCompatibilityPkg/Foundation/Framework/Ppi/EdkFrameworkPpiLib.inf - EdkCompatibilityPkg/Foundation/Library/Pei/Hob/PeiHobLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesTablePointerLibMm7/PeiServicesTablePointerLibMm7.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesLib/PeiServicesLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf - EdkCompatibilityPkg/Foundation/Core/Dxe/ArchProtocol/ArchProtocolLib.inf - - $(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPlatformLib.inf -[Libraries.X64] - - EdkCompatibilityPkg/Foundation/Efi/Guid/EfiGuidLib.inf - EdkCompatibilityPkg/Foundation/Framework/Guid/EdkFrameworkGuidLib.inf - EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/EfiCommonLib.inf - EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/CpuIA32Lib.inf - EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib.inf - EdkCompatibilityPkg/Foundation/Framework/Ppi/EdkFrameworkPpiLib.inf - EdkCompatibilityPkg/Foundation/Core/Dxe/ArchProtocol/ArchProtocolLib.inf - EdkCompatibilityPkg/Foundation/Library/Dxe/Hob/HobLib.inf - EdkCompatibilityPkg/Foundation/Library/RuntimeDxe/EfiRuntimeLib/EfiRuntimeLib.inf - EdkCompatibilityPkg/Foundation/Library/Dxe/EfiIfrSupportLib/EfiIfrSupportLib.inf - EdkCompatibilityPkg/Foundation/Library/Dxe/Print/PrintLib.inf - EdkCompatibilityPkg/Foundation/Library/Dxe/EfiScriptLib/EfiScriptLib.inf - EdkCompatibilityPkg/Foundation/Library/Dxe/PrintLite/PrintLib.inf - EdkCompatibilityPkg/Foundation/Library/Dxe/GraphicsLite/Graphics.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeMemoryAllocationLib/DxeMemoryAllocationLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiLib/UefiLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeHobLib/DxeHobLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/HiiLib/HiiLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiDevicePathLib/UefiDevicePathLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiDriverModelLib/UefiDriverModelLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeServicesTableLib/DxeServicesTableLib.inf - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/EdkDxeRuntimeDriverLib/EdkDxeRuntimeDriverLib.inf - - -################################################################################ -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -################################################################################ -[PcdsFeatureFlag.common] -!if $(MINI_BIOS_ENABLE) == FALSE - gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|TRUE -!else - gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|FALSE -!endif -# -# If PcdDxeIplSwitchToLongMode is TRUE, DxeIpl will load a 64-bit DxeCore and switch to long mode to hand over to DxeCore. -# - gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE - - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserGrayOutTextStatement|TRUE - -!if $(CAPSULE_RESET_ENABLE) == TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE -!else - gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE -!endif - gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE - gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE -!if $(DATAHUB_STATUS_CODE_ENABLE) == TRUE - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|TRUE -!else - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|FALSE -!endif - gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE -!if $(TARGET) == RELEASE - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE -!else - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE -!endif - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE -!if $(ISA_SERIAL_STATUS_CODE_ENABLE) == TRUE - gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|TRUE -!else - gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|FALSE -!endif -!if $(USB_SERIAL_STATUS_CODE_ENABLE) == TRUE - gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|TRUE -!else - gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|FALSE -!endif -!if $(RAM_SERIAL_STATUS_CODE_ENABLE) == TRUE - gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|TRUE -!else - gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|FALSE -!endif - - - ## This PCD specifies whether PS2 keyboard does a extended verification during start. - gEfiMdeModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|FALSE - - ## This PCD specifies whether PS2 mouse does a extended verification during start. - gEfiMdeModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|FALSE - -!if $(VARIABLE_INFO_ENABLE) == TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|TRUE -!else - gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|FALSE -!endif - - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE - -[PcdsFixedAtBuild.common] -!if $(HTTP_BOOT_SUPPORT) == TRUE - gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE -!endif -!if $(BUILD_NEW_SHELL) == TRUE - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } -!endif - -!if $(MINNOW2_FSP_BUILD) == TRUE -# $(FLASH_REGION_VLVMICROCODE_BASE) - gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000 -# $(FLASH_REGION_VLVMICROCODE_SIZE) - gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000 - gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60 -# $(FLASH_AREA_BASE_ADDRESS) - gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000 -# $(FLASH_AREA_SIZE) - gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00800000 -# $(FLASH_REGION_FSPBIN_BASE) - gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFCC0000 -!endif - -!if $(PERFORMANCE_ENABLE) == TRUE -!if $(MINNOW2_FSP_BUILD) == TRUE - # in FSP, when this got used, the memory already is up - gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000 -!else - gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 -!endif - gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000 - -!else - !if $(MINNOW2_FSP_BUILD) == TRUE - gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000 - !else - gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 - !endif - gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000 - gEfiCpuTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x3C00 -!endif - - -!if $(SECURE_BOOT_ENABLE) == TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x22000 -!else - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000 -!endif - gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 - gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000 - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x10000 - gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|50 - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPpiSupported|128 - gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000 -!if $(S4_ENABLE) == TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE -!else - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE -!endif -!if $(TARGET) == RELEASE - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 -!else - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 -!endif -!if $(PERFORMANCE_ENABLE) == TRUE - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|60 -!endif - - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x10000 - gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS) - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 - gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|FALSE - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000 - -[PcdsFixedAtBuild.X64] -gEfiMdeModulePkgTokenSpaceGuid.PcdSystemRebootAfterCapsuleProcessFlag|0x0001 - -[PcdsFixedAtBuild.IA32.PEIM, PcdsFixedAtBuild.IA32.PEI_CORE, PcdsFixedAtBuild.IA32.SEC] -!if $(TARGET) == RELEASE - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 -!else - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 -!endif - -[PcdsPatchableInModule.common] - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6 - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x$(PLATFORM_PCIEXPRESS_BASE) - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|FALSE - - ## This PCD specifies whether to use the optimized timing for best PS2 detection performance. - # Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility. - gEfiMdeModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE - - ####################################################################################################### - # - # Begin of MRC parameters - # - - ## Memory Parameter Patchable. - # FALSE - MRC Parameters are fixed for MinnowBoard Max
- # TRUE - MRC Parameters are patchable by following PCDs
- # @Prompt Memory Parameter Patchable. - # @ValidList 0x80000001 | 0, 1 - gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|FALSE - - ## Memory Down or DIMM slot. - # 0 - DIMM
- # 1 - Memory Down
- # @Prompt Enable Memory Down - # @ValidList 0x80000001 | 0, 1 - gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|1 - - ## The speed of DRAM. - # 0 - 800 MHz
- # 1 - 1066 MHz
- # 2 - 1333 MHz
- # 3 - 1600 MHz
- # @Prompt DRAM Speed - # @ValidList 0x80000001 | 0, 1, 2, 3 - gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|1 - - ## DRAM Type. - # 0 - DDR3
- # 1 - DDR3L
- # 2 - DDR3U
- # 3 - DDR3All
- # 4 - LPDDR2
- # 5 - LPDDR3
- # 6 - DDR4
- # @Prompt DRAM Type - # @ValidList 0x80000001 | 0, 1, 2, 3, 4, 5, 6 - gVlvRefCodePkgTokenSpaceGuid.PcdDramType|1 - - ## Please populate DIMM slot 0 if only one DIMM is supported. - # 0 - Disable
- # 1 - Enable
- # @Prompt DIMM 0 Enable - # @ValidList 0x80000001 | 0, 1 - gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|1 - - ## DIMM 1 has to be identical to DIMM 0. - # 0 - Disable
- # 1 - Enable
- # @Prompt DIMM 1 Enable Type - # @ValidList 0x80000001 | 0, 1 - gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0 - - ## DRAM device data width. - # 0 - x8
- # 1 - x16
- # 2 - x32
- # @Prompt DIMM_DWIDTH - # @ValidList 0x80000001 | 0, 1, 2 - gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|1 - - ## DRAM device data density. - # 0 - 1 Gbit
- # 1 - 2 Gbit
- # 2 - 4 Gbit
- # 3 - 8 Gbit
- # @Prompt DIMM_Density - # @ValidList 0x80000001 | 0, 1, 2, 3 - gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|2 - - ## DRAM device data bus width. - # 0 - 8 bits
- # 1 - 16 bits
- # 2 - 32 bits
- # 3 - 64 bits
- # @Prompt DIMM_BusWidth - # @ValidList 0x80000001 | 0, 1, 2, 3 - gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|3 - - ## Ranks Per DIMM or Sides Per DIMM. - # 0 - 1 Rank
- # 1 - 2 Ranks
- # @Prompt DIMM_Sides - # @ValidList 0x80000001 | 0, 1 - gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0 - - ## tCL.

- # @Prompt tCL - gVlvRefCodePkgTokenSpaceGuid.PcdTcl|11 - - ## tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. - # @Prompt tRP_tRCD - gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|11 - - ## tWR in DRAM clk. - # @Prompt tWR - gVlvRefCodePkgTokenSpaceGuid.PcdTwr|12 - - ## tWTR in DRAM clk. - # @Prompt tWTR - gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|6 - - ## tRRD in DRAM clk. - # @Prompt tRRD - gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|6 - - ## tRTP in DRAM clk. - # @Prompt tRTP - gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|6 - - ## tFAW in DRAM clk. - # @Prompt tFAW - gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|32 - - # - # End of MRC parameters. - # - ############################################################################################### - -[PcdsDynamicHii.common.DEFAULT] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout" - gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gEfiBootStateGuid|0x0|TRUE - - -[PcdsDynamicDefault.common.DEFAULT] - gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 - !if $(TPM_ENABLED) == TRUE - gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd, 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13} - !endif - !if $(FTPM_ENABLE) == TRUE - gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd, 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13} - !endif - - ## This PCD defines the video horizontal resolution. - # This PCD could be set to 0 then video resolution could be at highest resolution. - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 - ## This PCD defines the video vertical resolution. - # This PCD could be set to 0 then video resolution could be at highest resolution. - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 - - ## This PCD defines the Console output column and the default value is 25 according to UEFI spec. - # This PCD could be set to 0 then console output could be at max column and max row. - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 - ## This PCD defines the Console output row and the default value is 80 according to UEFI spec. - # This PCD could be set to 0 then console output could be at max column and max row. - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100 - - ## The PCD is used to specify the video horizontal resolution of text setup. - gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800 - ## The PCD is used to specify the video vertical resolution of text setup. - gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600 - ## The PCD is used to specify the console output column of text setup. - gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100 - ## The PCD is used to specify the console output column of text setup. - gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|31 - -!if $(TPM_ENABLED) == TRUE - gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 - gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1 -!endif - - gPlatformModuleTokenSpaceGuid.PcdRtcPowerFailure|FALSE - -[PcdsDynamicExDefault.common.DEFAULT] - gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040 - gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId|0 - gEfiVLVTokenSpaceGuid.PcdProductSerialNumber|0 - gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable|TRUE - gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur|FALSE - gEfiVLVTokenSpaceGuid.PcdFTPMErrorSkip|FALSE - gEfiVLVTokenSpaceGuid.PcdFTPMCommand|0 - gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0 - gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE - gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0 - gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr|0 - gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0 - gEfiCpuTokenSpaceGuid.PcdCpuS3DataAddress|0 - gEfiCpuTokenSpaceGuid.PcdCpuHotPlugDataAddress|0 - gEfiCpuTokenSpaceGuid.PcdCpuCallbackSignal|0 - gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer|0 - gEfiVLVTokenSpaceGuid.PcdCpuLockBoxDataAddress|0 - gEfiVLVTokenSpaceGuid.PcdCpuSmramCpuDataAddress|0 - gEfiVLVTokenSpaceGuid.PcdCpuLockBoxSize|0 - gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE - -!if $(CAPSULE_ENABLE) - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100 - gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x7b, 0x26, 0x96, 0x40, 0x0a, 0xda, 0xeb, 0x42, 0xb5, 0xeb, 0xfe, 0xf3, 0x1d, 0x20, 0x7c, 0xb4} - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0x59, 0x3A, 0xD8, 0x14, 0x10, 0xA8, 0x56, 0x45, 0x81, 0x92, 0x1C, 0x0A, 0x59, 0x3C, 0x06, 0x5C} -!endif - - -[Components.IA32] - -!if $(CAPSULE_ENABLE) - # FMP image decriptor - Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf { - - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - } -!endif - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SecCore.inf - - !if $(MINNOW2_FSP_BUILD) == TRUE - IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf { - !if $(TARGET) == DEBUG - - - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - !endif - } - Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf - IntelFspWrapperPkg/FspInitPei/FspInitPei.inf { - !if $(TARGET) == DEBUG - - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - !endif - } - !endif - - MdeModulePkg/Core/Pei/PeiMain.inf { -!if $(TARGET) == DEBUG - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E -!endif - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 - } - - $(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf { -!if $(TARGET) == DEBUG - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E -!endif - } - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MemoryInit.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 - - !if $(FTPM_ENABLE)==TRUE - *_*_IA32_CC_FLAGS = /D FTPM_ENABLE - !endif - } - -!if $(RC_BINARY_RELEASE) == TRUE - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SeCUma.inf -!endif - -!if $(FTPM_ENABLE) == TRUE -$(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fTPMInitPeim.inf -!endif - -!if $(RC_BINARY_RELEASE) == TRUE - $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf { - - *_*_IA32_CC_FLAGS = /DRC_BINARY_RELEASE - !if $(TARGET) == DEBUG - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E - !endif - - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - } -!endif - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf{ - - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf - PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf - SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf - } -!endif - -!if $(FTPM_ENABLE) == TRUE - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Tpm2DeviceSeCPei.inf -!endif - -!if $(TPM_ENABLED) == TRUE - SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf - SecurityPkg/Tcg/TcgPei/TcgPei.inf { - - NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf - NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf -} -!endif - - $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6 - -!if $(TARGET) != RELEASE - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf -!endif - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - } - $(PLATFORM_PACKAGE)/FvInfoPei/FvInfoPei.inf - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/VlvInitPeim.inf -!if $(PCIESC_ENABLE) == TRUE - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchEarlyInitPeim.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 - } -!endif - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchInitPeim.inf - - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSmbusArpDisabled.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSpiPeim.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmAccess.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmControl.inf - MdeModulePkg/Universal/PCD/Pei/Pcd.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/CpuPeim.inf - UefiCpuPkg/CpuIoPei/CpuIoPei.inf - UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MpS3.inf - EdkCompatibilityPkg/Compatibility/AcpiVariableHobOnSmramReserveHobThunk/AcpiVariableHobOnSmramReserveHobThunk.inf - UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf -!if $(CAPSULE_ENABLE) == TRUE - MdeModulePkg/Universal/CapsulePei/CapsulePei.inf -!endif - MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { - -!if $(LZMA_ENABLE) == TRUE - NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf -!endif - } - - - MdeModulePkg/Universal/Variable/Pei/VariablePei.inf - MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf - -!if $(FTPM_ENABLE) == TRUE - SecurityPkg/Tcg/TrEEPei/TrEEPei.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 - - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf - NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - } -!endif -!if $(TPM_ENABLED) == TRUE - SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf { - - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - } -!endif -!if $(ACPI50_ENABLE) == TRUE - MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf{ - - TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf - } - -!endif -!if $(PERFORMANCE_ENABLE) == TRUE - MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf -!endif -[Components.X64] - !if $(MINNOW2_FSP_BUILD) == TRUE - IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf { - !if $(TARGET) == DEBUG - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 - - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - !endif - } - - !endif - # - # EDK II Related Platform codes - # - MdeModulePkg/Core/Dxe/DxeMain.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 - -!if $(DXE_CRC32_SECTION_ENABLE) == TRUE - NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf -!endif -!if $(LZMA_ENABLE) == TRUE - NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf -!endif -!if $(TARGET) != RELEASE - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf -!endif - } - IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043 - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 - - !if $(TARGET) != RELEASE - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - !endif - - ICC:*_*_*_CC_FLAGS = /D MDEPKG_NDEBUG - GCC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG - } - MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { - - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - } - IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf - UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf - - MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf - MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf { - -!if $(TARGET) != RELEASE - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf -!endif - } - -!if $(DXE_ARCHITECTURE) == X64 -!if $(CAPSULE_ENABLE) == TRUE - MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf { - - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf - HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf - } -!endif -!endif - - MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf{ - - NULL|SecurityPkg/Library/DxeImageAuthenticationStatusLib/DxeImageAuthenticationStatusLib.inf -!if $(SECURE_BOOT_ENABLE) == TRUE - NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf -!endif -!if $(USER_IDENTIFICATION_ENABLE) - NULL|SecurityPkg/Library/DxeDeferImageLoadLib/DxeDeferImageLoadLib.inf -!endif -!if $(TPM_ENABLED) == TRUE - NULL|SecurityPkg/Library/DxeTpmMeasureBootLib/DxeTpmMeasureBootLib.inf -!endif -!if $(FTPM_ENABLE) == TRUE - NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib.inf -!endif - } - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MpCpu.inf - $(PLATFORM_PACKAGE)/Metronome/Metronome.inf - -!if $(HTTP_BOOT_SUPPORT) == TRUE - MdeModulePkg/Universal/BdsDxe/BdsDxe.inf{ - - OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf - IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf - PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf - !if $(FTPM_ENABLE) == TRUE - Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2DeviceLibSeC.inf - !else - TrEEPhysicalPresenceLib|$(PLATFORM_PACKAGE)/Library/DxeTrEEPhysicalPresenceLibNull/DxeTrEEPhysicalPresenceLibNull.inf - !endif - } - MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf - MdeModulePkg/Application/UiApp/UiApp.inf { - - NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf - NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf - NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf - } -!else - IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf{ - - OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf - IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf - PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf - !if $(FTPM_ENABLE) == TRUE - Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2DeviceLibSeC.inf - !else - TrEEPhysicalPresenceLib|$(PLATFORM_PACKAGE)/Library/DxeTrEEPhysicalPresenceLibNull/DxeTrEEPhysicalPresenceLibNull.inf - !endif - } - $(PLATFORM_PACKAGE)/UiApp/UiApp.inf -!endif - MdeModulePkg/Universal/LoadFileOnFv2/LoadFileOnFv2.inf - MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf - - - MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf - MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { - - NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf - } - $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf - MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf -!if $(SECURE_BOOT_ENABLE) == TRUE - SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf { - - PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf - - # - # Specify GUID gEfiIfrBootMaintenanceGuid, to install Secure Boot Configuration menu - # into Boot Maintenance Manager menu - # - *_*_*_VFR_FLAGS = -g b2dedc91-d59f-48d2-898a-12490c74a4e0 - } -!endif - MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf { - - FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf - } - - MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf - PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf - MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - - $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf { - !if $(TARGET) == DEBUG - - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf - !endif - } - - $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf - -!if $(DATAHUB_ENABLE) == TRUE - IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf { - - gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0 - } -!endif - IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandlerDxe/DatahubStatusCodeHandlerDxe.inf - MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchS3SupportDxe.inf - !if $(USE_HPET_TIMER) == TRUE - PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf - !else - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmartTimer.inf - !endif - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmControl.inf - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmbusDxe.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/IntelPchLegacyInterrupt.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchReset.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitDxe.inf{ - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043 - } - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitSmm.inf - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmiDispatcher.inf - -!if $(PCIESC_ENABLE) == TRUE - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPcieSmm.inf -!endif - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiRuntime.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPolicyInitDxe.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchBiosWriteProtect.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmAccess.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PciHostBridge.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/VlvInitDxe.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/GraphicDxeInitSmm.inf - - IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.inf - - PerformancePkg/Dp_App/Dp.inf { - - !if $(PERFORMANCE_ENABLE) == TRUE - PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf - TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf - !endif - } - - Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf{ - -!if $(TARGET) != RELEASE - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf -!endif - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Dptf.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PnpDxe.inf - -!if $(SEC_ENABLE) == TRUE - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/HeciDrv.inf { -!if $(SEC_DEBUG_INFO_ENABLE) == TRUE - - *_*_X64_CC_FLAGS = /DSEC_DEBUG_INFO=1 -!else - - *_*_X64_CC_FLAGS = /DSEC_DEBUG_INFO=0 -!endif - } - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SeCPolicyInitDxe.inf -!endif - -!if $(FTPM_ENABLE) == TRUE - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Tpm2DeviceSeCDxe.inf - SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf - SecurityPkg/Tcg/MemoryOverwriteRequestControlLock/TcgMorLockSmm.inf - SecurityPkg/Tcg/TrEEDxe/TrEEDxe.inf{ - - NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf - NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2DeviceLibSeC.inf - } - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/FtpmSmm.inf -!endif -!if $(TPM_ENABLED) == TRUE - SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf { - - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - } - - SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf { - - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - - # - # specify GUID gEfiIfrNotInTPVPageGuid, this page will not - # be showed in TPV page. - # - *_*_*_VFR_FLAGS = -g e58809f8-fbc1-48e2-883a-a30fdc4b441e - } - - SecurityPkg/Tcg/TcgDxe/TcgDxe.inf { - - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } - SecurityPkg/Tcg/TcgSmm/TcgSmm.inf -!endif - # - # EDK II Related Platform codes - # - $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf{ - - !if $(TARGET) != RELEASE - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - !endif - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } - $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf - $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf - $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf - $(PLATFORM_PACKAGE)/PlatformRtcRuntimeDxe/PlatformRtcRuntimeDxe.inf - - - $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf - $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PlatformCpuPolicy.inf - $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf - $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf -!if $(GOP_DRIVER_ENABLE) == TRUE - $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf - -!endif - - - # - # SMM - # - MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf - MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf - UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { - - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000 - } - UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf - MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf - UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf - UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf - $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PowerManagement2.inf - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/DigitalThermalSensor.inf - - # - # ACPI - # - MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043 - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 - - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } - MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf - MdeModulePkg/Universal/Acpi/SmmS3SaveState/SmmS3SaveState.inf - - $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf - IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDxe.inf - Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf - - $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf - - $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf - - # - # PCI - # - MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/ISPDxe.inf - - -# -# ISA -# - $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf - IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf - IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf - IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf - IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf - IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf -# -# eMMC/SD Card -# - MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf - MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf - MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf - -!if $(ACPI50_ENABLE) == TRUE - MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf { - - TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf - } - MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf { - - TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf - } - MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf -!endif - -# -# IDE/SCSI/AHCI -# - MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf - IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf - MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf -!if $(SATA_ENABLE) == TRUE - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SataController.inf -!endif - MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf -!if $(SCSI_ENABLE) == TRUE - MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf - MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf -!endif -# -# Console -# - MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf - IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf - MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - - # - # USB - # -!if $(USB_ENABLE) == TRUE - MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf - MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf - Vlv2TbltDevicePkg/Override/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf - MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf - MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf - MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - -!endif - - # - # ECP - # - EdkCompatibilityPkg/Compatibility/FrameworkHiiOnUefiHiiThunk/FrameworkHiiOnUefiHiiThunk.inf - EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf - EdkCompatibilityPkg/Compatibility/SmmBaseOnSmmBase2Thunk/SmmBaseOnSmmBase2Thunk.inf - EdkCompatibilityPkg/Compatibility/SmmBaseHelper/SmmBaseHelper.inf - EdkCompatibilityPkg/Compatibility/SmmAccess2OnSmmAccessThunk/SmmAccess2OnSmmAccessThunk.inf - EdkCompatibilityPkg/Compatibility/SmmControl2OnSmmControlThunk/SmmControl2OnSmmControlThunk.inf - EdkCompatibilityPkg/Compatibility/FrameworkSmmStatusCodeOnPiSmmStatusCodeThunk/FrameworkSmmStatusCodeOnPiSmmStatusCodeThunk.inf - EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf - # - # SMBIOS - # - MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmbiosMemory.inf - # - # CPU/FW Microde - # - Vlv2MiscBinariesPkg/Microcode/MicrocodeUpdates.inf { - - *_*_*_GENFW_FLAGS = -a 0x800 -p 0xFF - } - - - PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf - - -!if $(NETWORK_ENABLE) == TRUE - !if $(NETWORK_ISCSI_ENABLE) == TRUE - !if $(NETWORK_IP6_ENABLE) == TRUE - NetworkPkg/IScsiDxe/IScsiDxe.inf - !else - MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf - !endif - !endif - !if $(NETWORK_VLAN_ENABLE) == TRUE - MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf - !endif - !if $(CSM_ENABLE) == TRUE - IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Snp16Dxe.inf - !endif -!endif - -!if $(NETWORK_ENABLE) == TRUE - # - # UEFI network modules - # - MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf - MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf - - MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf - MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf - MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf -!if $(HTTP_BOOT_SUPPORT) == TRUE - NetworkPkg/HttpDxe/HttpDxe.inf - NetworkPkg/HttpBootDxe/HttpBootDxe.inf - NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf - NetworkPkg/DnsDxe/DnsDxe.inf - !if $(NETWORK_TLS_ENABLE) == TRUE - NetworkPkg/TlsDxe/TlsDxe.inf - NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf - !endif - MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf -!endif - MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf - MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf - MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000 - } - MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf - !if $(NETWORK_IP6_ENABLE) == TRUE - NetworkPkg/Ip6Dxe/Ip6Dxe.inf - NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf - NetworkPkg/IpSecDxe/IpSecDxe.inf - NetworkPkg/TcpDxe/TcpDxe.inf - NetworkPkg/Udp6Dxe/Udp6Dxe.inf - NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf - !endif - !if $(NETWORK_IP6_ENABLE) == TRUE - NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf - !else - MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf - !endif -!endif - -# -# capsule related drivers -# -IntelFrameworkModulePkg/Universal/FirmwareVolume/FwVolDxe/FwVolDxe.inf - -MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.inf - - Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.inf - Vlv2TbltDevicePkg/Application/SsdtUpdate/SsdtUpdate.inf - - !if $(CAPSULE_ENABLE) - MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf - MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf { - - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } - !endif - - !if $(CAPSULE_ENABLE) - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf { - - FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibRsa2048Sha256/FmpAuthenticationLibRsa2048Sha256.inf - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - } - -[Components.IA32] - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { - - FILE_GUID = 232393E2-185F-4212-A986-2B01F529EED9 - - FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibRsa2048Sha256/FmpAuthenticationLibRsa2048Sha256.inf - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } - -[Components.X64] - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { - - FILE_GUID = F1E68873-DA37-4AA0-A12F-F0F8EBA2B24E - - FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibRsa2048Sha256/FmpAuthenticationLibRsa2048Sha256.inf - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - } - -!endif - -[BuildOptions] -# -# Define Build Options both for EDK and EDKII drivers. -# - -# -# Define token for different Platform -# -!if $(MINNOW2_FSP_BUILD) == TRUE - DEFINE MINNOW2_FSP_OPTION = /DMINNOW2_FSP_BUILD -!else - DEFINE MINNOW2_FSP_OPTION = -!endif - -!if $(ENBDT_PF_BUILD) == TRUE - DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1 -!else - DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0 -!endif - - -!if $(CLKGEN_CONFIG_EXTRA_ENABLE) == TRUE - DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION = /DCLKGEN_CONFIG_EXTRA=1 -!else - DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION = -!endif - - - -!if $(PCIESC_ENABLE) == TRUE - DEFINE PCIESC_SUPPORT_BUILD_OPTION = /DPCIESC_SUPPORT=1 -!else - DEFINE PCIESC_SUPPORT_BUILD_OPTION = -!endif -!if $(SATA_ENABLE) == TRUE - DEFINE SATA_SUPPORT_BUILD_OPTION = /DSATA_SUPPORT=1 -!else - DEFINE SATA_SUPPORT_BUILD_OPTION = -!endif -!if $(ENBDT_S3_SUPPORT) == TRUE - DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT -!else - DEFINE ENBDT_S3_SUPPORT_OPTIONS = -!endif - -!if $(X64_CONFIG) == TRUE - DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1 -!else - DEFINE X64_BUILD_ENABLE = -!endif - -!if $(FTPM_ENABLE) == TRUE - DEFINE DSC_FTPM_BUILD_OPTIONS = /DFTPM_ENABLE -!else - DEFINE DSC_FTPM_BUILD_OPTIONS = -!endif -!if $(TPM_ENABLED) == TRUE - DEFINE DSC_TPM_BUILD_OPTIONS = /DTPM_ENABLED -!else - DEFINE DSC_TPM_BUILD_OPTIONS = -!endif - - - DEFINE EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS = $(MINNOW2_FSP_OPTION) $(MINNOW2_BUILD_OPTION) $(ENBDT_PF_ENABLE) $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) $(CLKGEN_CONFIG_EXTRA_BUILD_OPTION) $(SYSCTL_X0_CONVERT_BOARD_OPTION) $(ENBDT_S3_SUPPORT_OPTIONS) $(SATA_SUPPORT_BUILD_OPTION) $(PCIESC_SUPPORT_BUILD_OPTION) $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS) $(DSC_TPM_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) -!if $(PERFORMANCE_ENABLE) == TRUE - DEFINE PDB_BUILD_OPTION = /Zi -!endif - -!if $(SOURCE_DEBUG_ENABLE) == TRUE - MSFT:*_*_X64_GENFW_FLAGS = --keepexceptiontable - GCC:*_*_X64_GENFW_FLAGS = --keepexceptiontable - INTEL:*_*_X64_GENFW_FLAGS = --keepexceptiontable -!if $(TARGET) == DEBUG - DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS = /Od /Oy- -!endif -!else - DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS = - -!endif - -[BuildOptions.Common.EDK] - -# -# Define token for different Platform -# -!if $(ENBDT_PF_BUILD) == TRUE - DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1 -!else - DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0 -!endif - -!if $(PERFORMANCE_ENABLE) == TRUE - RELEASE_*_*_DLINK_FLAGS = /DEBUG -!endif - -!if $(S3_ENABLE) == TRUE - DEFINE DSC_S3_BUILD_OPTIONS = /DEFI_S3_RESUME -!else - DEFINE DSC_S3_BUILD_OPTIONS = -!endif - -!if $(ENBDT_S3_SUPPORT) == TRUE - DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT -!else - DEFINE ENBDT_S3_SUPPORT_OPTIONS = -!endif - -!if $(X64_CONFIG) == TRUE - DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1 -!else - DEFINE X64_BUILD_ENABLE = -!endif - - - DEFINE EDK_GLUE_LIB_DEBUG = - DEFINE DEBUG_BUILD_OPTIONS = /D EFI_DEBUG /D DEBUG_MODE=1 /GL- $(EDK_GLUE_LIB_DEBUG) /DEDKII_GLUE_DebugPrintErrorLevel=(EFI_D_ERROR) - DEFINE EDK_DSC_FEATURE_BUILD_OPTIONS = $(DSC_S3_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(DSC_SEC_BUILD_OPTIONS) $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS) $(DSC_TPM_BUILD_OPTIONS) $(SOFTSDV_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(QT_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /D$(PROJECT_SC_CHIPSET) - - DEFINE EDK_DSC_OTHER_BUILD_OPTIONS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SV_BUILD_OPTIONS) $(INTEL_FASTBOOT_BUILD_OPTION) - DEFINE EDK_DSC_GLOBAL_BUILD_OPTIONS = $(ENBDT_PF_ENABLE) $(EDK_DSC_FEATURE_BUILD_OPTIONS) $(EDK_DSC_OTHER_BUILD_OPTIONS) /D EFI_SPECIFICATION_VERSION=0x00020000 /D PI_SPECIFICATION_VERSION=0x00000009 /D TIANO_RELEASE_VERSION=0x00080006 /D SUPPORT_DEPRECATED_PCI_CFG_PPI /D CSM_SMMENTRY_PORT8DATA8 /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) /D MAX_VARIABLE_SIZE=0x2000 /D EFI_FIRMWARE_VENDOR="L/"INTEL/"" /D EFI_BUILD_VERSION="L/"EDKII/"" /DEFI_PEI_REPORT_STATUS_CODE_ON $(ENBDT_S3_SUPPORT_OPTIONS) - - *_*_IA32_ASM_FLAGS = /DEFI32 /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT - DEBUG_*_IA32_CC_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) - RELEASE_*_IA32_CC_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) - DEBUG_*_IA32_VFRPP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) - RELEASE_*_IA32_VFRPP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) - DEBUG_*_IA32_APP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) - RELEASE_*_IA32_APP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) - DEBUG_*_IA32_PP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) - RELEASE_*_IA32_PP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) - *_*_IA32_ASLPP_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) - *_*_IA32_ASLCC_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) - *_*_IA32_ASM16_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h - - *_*_X64_ASM_FLAGS = /DEFIX64 /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT - DEBUG_*_X64_CC_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) - RELEASE_*_X64_CC_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) - DEBUG_*_X64_VFRPP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) - RELEASE_*_X64_VFRPP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) - DEBUG_*_X64_APP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) - RELEASE_*_X64_APP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) - DEBUG_*_X64_PP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) - RELEASE_*_X64_PP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) - *_*_X64_ASLPP_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) - *_*_X64_ASLCC_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) - *_*_X64_ASM16_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h - # *_*_*_BUILD_FLAGS = -s - *_*_*_VFR_FLAGS = -c - *_*_*_BUILD_FLAGS = -c - -[BuildOptions.Common.EDKII] - *_*_IA32_ASM_FLAGS = $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT - - *_*_IA32_CC_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_IA32_VFRPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_IA32_APP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_IA32_PP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_IA32_ASLPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) - - *_*_X64_CC_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SOURCE_LEVEL_DEBUG_BUILD_OPTIONS) - *_*_X64_VFRPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_X64_APP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_X64_PP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_X64_ASLPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) - - -[Components.X64] - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SysFwUpdateCapsuleDxe.inf - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cBus.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043 - } - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cHost.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043 - } - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cPortA0Pio.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043 - } - - $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cMmioDeviceDxe.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043 - } +#/** @file +# Platform description. +# +# Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Vlv2TbltDevicePkg + PLATFORM_GUID = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + + # + # Set platform specific package/folder name, same as passed from PREBUILD script. + # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package build folder + # DEFINE only takes effect at R9 DSC and FDF. + # + DEFINE PLATFORM_PACKAGE = Vlv2TbltDevicePkg + DEFINE PLATFORM_RC_PACKAGE = Vlv2DeviceRefCodePkg + DEFINE PLATFORM_BINARY_PACKAGE = Vlv2BinaryPkg + OUTPUT_DIRECTORY = Build/$(PLATFORM_PACKAGE) + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + + DEFINE CPU_ARCH =ValleyView2 + DEFINE PROJECT_SC_FAMILY =IntelPch + DEFINE PROJECT_SC_ROOT =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/SouthCluster + DEFINE PROJECT_VLV_ROOT =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/NorthCluster + + DEFINE RC_BINARY_RELEASE = TRUE + # + # Platform On/Off features are defined here + # + # + # Platform Support:: Set only one token except Crestview Hills + # + # 3.BayleyBay + # ENBDT_PF_ENABLE = TRUE + # + !include $(PLATFORM_PACKAGE)/AutoPlatformCFG.txt + !include $(PLATFORM_PACKAGE)/PlatformPkgConfig.dsc + +!if $(X64_CONFIG) == TRUE + DEFINE DXE_ARCHITECTURE = X64 + DEFINE EDK_DXE_ARCHITECTURE = X64 + DEFINE UNDI_DXE_ARCHITECTURE = 64 +!else + DEFINE DXE_ARCHITECTURE = IA32 + DEFINE EDK_DXE_ARCHITECTURE = Ia32 + DEFINE UNDI_DXE_ARCHITECTURE = 32 +!endif + + FLASH_DEFINITION = $(PLATFORM_PACKAGE)/PlatformPkg.fdf +!if $(LFMA_ENABLE) == TRUE + FIX_LOAD_TOP_MEMORY_ADDRESS = 0xFFFFFFFFFFFFFFFF + DEFINE TOP_MEMORY_ADDRESS = 0xFFFFFFFFFFFFFFFF +!else + FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0 + DEFINE TOP_MEMORY_ADDRESS = 0x0 +!endif + + DEFINE PLATFORM_PCIEXPRESS_BASE = 0E0000000 + + DEFINE SEC_ENABLE = FALSE + DEFINE SEC_DEBUG_INFO_ENABLE = FALSE + DEFINE FTPM_ENABLE = FALSE + +################################################################################ +# +# SKU Identification section - list of all SKU IDs supported by this +# Platform. +# +################################################################################ +[SkuIds] + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required. + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ +[LibraryClasses.common] + # + # Entry point + # + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + DxeSmmDriverEntryPoint|IntelFrameworkPkg/Library/DxeSmmDriverEntryPoint/DxeSmmDriverEntryPoint.inf +!if $(HTTP_BOOT_SUPPORT) == TRUE + TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf + Tcg2PhysicalPresenceLib|SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.inf + TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull.inf + Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibNull.inf + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.inf + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf +!endif + + # + # Basic + # + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf +!if $(SSE2_ENABLE) == TRUE + BaseMemoryLib|MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2.inf +!else + BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +!endif + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf +!if $(RC_BINARY_RELEASE) == TRUE + PchPlatformLib|Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf +!endif + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + # + # UEFI & PI + # + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + GenericBdsLib|$(PLATFORM_PACKAGE)/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf + PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + FlashDeviceLib|$(PLATFORM_PACKAGE)/Library/FlashDeviceLib/FlashDeviceLib.inf + # + # Framework + # +!if $(S3_ENABLE) == TRUE + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +!else + S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf +!endif + S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf + SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf + + # + # Generic Modules + # +!if $(USB_ENABLE) == TRUE + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf +!endif +!if $(SCSI_ENABLE) == TRUE + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf +!endif +!if $(NETWORK_ENABLE) == TRUE + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf +!if $(HTTP_BOOT_SUPPORT) == TRUE + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf + PlatformBootManagerLib | $(PLATFORM_PACKAGE)/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + BootLogoLib | MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf +!endif +!endif +!if $(S3_ENABLE) == TRUE + S3Lib|IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf +!endif + + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + +!if $(CAPSULE_ENABLE) == TRUE + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf +!else + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf +!endif + + EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf + FmpAuthenticationLib|MdeModulePkg/Library/FmpAuthenticationLibNull/FmpAuthenticationLibNull.inf + IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf + PlatformFlashAccessLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.inf + + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + + LanguageLib|EdkCompatibilityPkg/Compatibility/Library/UefiLanguageLib/UefiLanguageLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + # + # CPU + # + MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf + LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf + CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf + + # + # ICH + # + SmbusLib|$(PLATFORM_PACKAGE)/Library/SmbusLib/SmbusLib.inf + SmmLib|$(PLATFORM_PACKAGE)/Library/PchSmmLib/PchSmmLib.inf + + # + # Platform + # + TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf + ResetSystemLib|$(PLATFORM_PACKAGE)/Library/ResetSystemLib/ResetSystemLib.inf + + PlatformCmosLib|$(PLATFORM_PACKAGE)/Library/PlatformCmosLib/PlatformCmosLib.inf + + # + # Misc + # + MonoStatusCodeLib|$(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf +!endif + + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +!if $(TPM_ENABLED) == TRUE + TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf + Tpm12CommandLib|SecurityPkg/Library/Tpm12CommandLib/Tpm12CommandLib.inf + Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm.inf + +!endif + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf +!endif + + # + # CryptLib + # +!if $(TPM_ENABLED) == TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf +!endif + + BiosIdLib|$(PLATFORM_PACKAGE)/Library/BiosIdLib/BiosIdLib.inf + CpuIA32Lib|$(PLATFORM_PACKAGE)/Library/CpuIA32Lib/CpuIA32Lib.inf + + StallSmmLib|$(PLATFORM_PACKAGE)/Library/StallSmmLib/StallSmmLib.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf +!if $(RC_BINARY_RELEASE) == TRUE + I2cLib|Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf +!endif + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf +!if $(FTPM_ENABLE) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf +!endif + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf + TrEEPhysicalPresenceLib|Vlv2TbltDevicePkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.inf +!if $(FTPM_ENABLE) == TRUE + TrEEPpVendorLib|SecurityPkg/Library/TrEEPpVendorLibNull/TrEEPpVendorLibNull.inf +!endif + + + Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf +!if $(MINNOW2_FSP_BUILD) == TRUE + FspApiLib|IntelFspWrapperPkg/Library/BaseFspApiLib/BaseFspApiLib.inf + FspPlatformInfoLib|IntelFspWrapperPkg/Library/BaseFspPlatformInfoLibSample/BaseFspPlatformInfoLibSample.inf + FspPlatformSecLib|Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf + FspHobProcessLib|Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf +!endif + +[LibraryClasses.IA32.SEC] +!if $(PERFORMANCE_ENABLE) == TRUE + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +!endif + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +[LibraryClasses.IA32.PEIM, LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.SEC] + # + # PEI phase common + # + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + MultiPlatformLib|$(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPlatformLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf + + +!if $(PERFORMANCE_ENABLE) == TRUE + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +!endif + +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf +!else + DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf + SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf +!endif + + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf + HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterPei.inf +!if $(SOURCE_DEBUG_ENABLE) == TRUE + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf +!endif + + !if $(MINNOW2_FSP_BUILD) == TRUE + PlatformFspLib|Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf + !endif +!if $(FTPM_ENABLE) == TRUE + Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2DeviceLibSeC.inf +!endif + +[LibraryClasses.IA32] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + !if $(TPM_ENABLED) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + !endif + + !if $(SECURE_BOOT_ENABLE) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + !endif + +[LibraryClasses.X64] + # + # DXE phase common + # + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + + TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf +!if $(TPM_ENABLED) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf +!endif + + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf + EfiRegTableLib|$(PLATFORM_PACKAGE)/Library/EfiRegTableLib/EfiRegTableLib.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf +!endif + + HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterDxe.inf + +[LibraryClasses.X64.DXE_DRIVER] + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf +!if $(PERFORMANCE_ENABLE) == TRUE + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +!endif + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + +[LibraryClasses.X64.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +!if $(PERFORMANCE_ENABLE) == TRUE + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf + TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +!endif + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + +[LibraryClasses.X64.DXE_SMM_DRIVER] + SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf + MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf + SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf + + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf + !if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !endif + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf + TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +!endif + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf + +[LibraryClasses.X64.SMM_CORE] + MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf + SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf + SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf + +!if $(TPM_ENABLED) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf +!endif + + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + +!if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf + TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +!endif + +[LibraryClasses.X64.DXE_RUNTIME_DRIVER] + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf +!if $(SECURE_BOOT_ENABLE) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif +!if $(TPM_ENABLED) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + +!if $(CAPSULE_ENABLE) == TRUE + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf +!endif + +[LibraryClasses.common.UEFI_DRIVER] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + +[LibraryClasses.X64.UEFI_APPLICATION] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + + +################################################################################ +# +# Library Section - list of all EDK/Framework libraries +# +################################################################################ +[Libraries.common] + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/BaseLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseMemoryLib/BaseMemoryLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePrintLib/BasePrintLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseDebugLibNull/BaseDebugLibNull.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciCf8Lib/BasePciCf8Lib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciExpressLib/BasePciExpressLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibCf8/BasePciLibCf8.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffLib/BasePeCoffLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/SmmRuntimeDxeReportStatusCodeLib/SmmRuntimeDxeReportStatusCodeLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiHobLib/PeiHobLib.inf + EdkCompatibilityPkg/Foundation/Ppi/EdkPpiLib.inf + EdkCompatibilityPkg/Foundation/Library/Pei/PeiLib/PeiLib.inf + EdkCompatibilityPkg/Compatibility/Library/UefiLanguageLib/UefiLanguageLib.inf + EdkCompatibilityPkg/Foundation/Guid/EdkGuidLib.inf + EdkCompatibilityPkg/Foundation/Efi/Protocol/EfiProtocolLib.inf + EdkCompatibilityPkg/Foundation/Library/Dxe/EfiDriverLib/EfiDriverLib.inf + EdkCompatibilityPkg/Foundation/Protocol/EdkProtocolLib.inf + EdkCompatibilityPkg/Foundation/Framework/Protocol/EdkFrameworkProtocolLib.inf +[Libraries.IA32] + EdkCompatibilityPkg/Foundation/Efi/Guid/EfiGuidLib.inf + EdkCompatibilityPkg/Foundation/Framework/Guid/EdkFrameworkGuidLib.inf + EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/EfiCommonLib.inf + EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/CpuIA32Lib.inf + EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib.inf + EdkCompatibilityPkg/Foundation/Framework/Ppi/EdkFrameworkPpiLib.inf + EdkCompatibilityPkg/Foundation/Library/Pei/Hob/PeiHobLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesTablePointerLibMm7/PeiServicesTablePointerLibMm7.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesLib/PeiServicesLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + EdkCompatibilityPkg/Foundation/Core/Dxe/ArchProtocol/ArchProtocolLib.inf + + $(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPlatformLib.inf +[Libraries.X64] + + EdkCompatibilityPkg/Foundation/Efi/Guid/EfiGuidLib.inf + EdkCompatibilityPkg/Foundation/Framework/Guid/EdkFrameworkGuidLib.inf + EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/EfiCommonLib.inf + EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/CpuIA32Lib.inf + EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib.inf + EdkCompatibilityPkg/Foundation/Framework/Ppi/EdkFrameworkPpiLib.inf + EdkCompatibilityPkg/Foundation/Core/Dxe/ArchProtocol/ArchProtocolLib.inf + EdkCompatibilityPkg/Foundation/Library/Dxe/Hob/HobLib.inf + EdkCompatibilityPkg/Foundation/Library/RuntimeDxe/EfiRuntimeLib/EfiRuntimeLib.inf + EdkCompatibilityPkg/Foundation/Library/Dxe/EfiIfrSupportLib/EfiIfrSupportLib.inf + EdkCompatibilityPkg/Foundation/Library/Dxe/Print/PrintLib.inf + EdkCompatibilityPkg/Foundation/Library/Dxe/EfiScriptLib/EfiScriptLib.inf + EdkCompatibilityPkg/Foundation/Library/Dxe/PrintLite/PrintLib.inf + EdkCompatibilityPkg/Foundation/Library/Dxe/GraphicsLite/Graphics.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeMemoryAllocationLib/DxeMemoryAllocationLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiLib/UefiLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeHobLib/DxeHobLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/HiiLib/HiiLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiDevicePathLib/UefiDevicePathLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiDriverModelLib/UefiDriverModelLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeServicesTableLib/DxeServicesTableLib.inf + EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/EdkDxeRuntimeDriverLib/EdkDxeRuntimeDriverLib.inf + + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ +[PcdsFeatureFlag.common] +!if $(MINI_BIOS_ENABLE) == FALSE + gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|TRUE +!else + gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|FALSE +!endif +# +# If PcdDxeIplSwitchToLongMode is TRUE, DxeIpl will load a 64-bit DxeCore and switch to long mode to hand over to DxeCore. +# + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserGrayOutTextStatement|TRUE + +!if $(CAPSULE_RESET_ENABLE) == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE + gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE +!if $(DATAHUB_STATUS_CODE_ENABLE) == TRUE + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|TRUE +!else + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|FALSE +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE +!if $(TARGET) == RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE +!if $(ISA_SERIAL_STATUS_CODE_ENABLE) == TRUE + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|TRUE +!else + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|FALSE +!endif +!if $(USB_SERIAL_STATUS_CODE_ENABLE) == TRUE + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|TRUE +!else + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|FALSE +!endif +!if $(RAM_SERIAL_STATUS_CODE_ENABLE) == TRUE + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|TRUE +!else + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|FALSE +!endif + + + ## This PCD specifies whether PS2 keyboard does a extended verification during start. + gEfiMdeModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|FALSE + + ## This PCD specifies whether PS2 mouse does a extended verification during start. + gEfiMdeModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|FALSE + +!if $(VARIABLE_INFO_ENABLE) == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|TRUE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|FALSE +!endif + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE + +[PcdsFixedAtBuild.common] +!if $(HTTP_BOOT_SUPPORT) == TRUE + gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE +!endif +!if $(BUILD_NEW_SHELL) == TRUE + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } +!endif + +!if $(MINNOW2_FSP_BUILD) == TRUE +# $(FLASH_REGION_VLVMICROCODE_BASE) + gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000 +# $(FLASH_REGION_VLVMICROCODE_SIZE) + gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000 + gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60 +# $(FLASH_AREA_BASE_ADDRESS) + gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000 +# $(FLASH_AREA_SIZE) + gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00800000 +# $(FLASH_REGION_FSPBIN_BASE) + gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFCC0000 +!endif + +!if $(PERFORMANCE_ENABLE) == TRUE +!if $(MINNOW2_FSP_BUILD) == TRUE + # in FSP, when this got used, the memory already is up + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000 +!else + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 +!endif + gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000 + +!else + !if $(MINNOW2_FSP_BUILD) == TRUE + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000 + !else + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 + !endif + gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000 + gEfiCpuTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x3C00 +!endif + + +!if $(SECURE_BOOT_ENABLE) == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x22000 +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 + gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000 + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x10000 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|50 + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPpiSupported|128 + gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000 +!if $(S4_ENABLE) == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE +!endif +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!endif +!if $(PERFORMANCE_ENABLE) == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|60 +!endif + + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x10000 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS) + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 + gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|FALSE + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE +!endif + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000 + +[PcdsFixedAtBuild.X64] +gEfiMdeModulePkgTokenSpaceGuid.PcdSystemRebootAfterCapsuleProcessFlag|0x0001 + +[PcdsFixedAtBuild.IA32.PEIM, PcdsFixedAtBuild.IA32.PEI_CORE, PcdsFixedAtBuild.IA32.SEC] +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!endif + +[PcdsPatchableInModule.common] + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x$(PLATFORM_PCIEXPRESS_BASE) + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|FALSE + + ## This PCD specifies whether to use the optimized timing for best PS2 detection performance. + # Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility. + gEfiMdeModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE + + ####################################################################################################### + # + # Begin of MRC parameters + # + + ## Memory Parameter Patchable. + # FALSE - MRC Parameters are fixed for MinnowBoard Max
+ # TRUE - MRC Parameters are patchable by following PCDs
+ # @Prompt Memory Parameter Patchable. + # @ValidList 0x80000001 | 0, 1 + gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|FALSE + + ## Memory Down or DIMM slot. + # 0 - DIMM
+ # 1 - Memory Down
+ # @Prompt Enable Memory Down + # @ValidList 0x80000001 | 0, 1 + gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|1 + + ## The speed of DRAM. + # 0 - 800 MHz
+ # 1 - 1066 MHz
+ # 2 - 1333 MHz
+ # 3 - 1600 MHz
+ # @Prompt DRAM Speed + # @ValidList 0x80000001 | 0, 1, 2, 3 + gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|1 + + ## DRAM Type. + # 0 - DDR3
+ # 1 - DDR3L
+ # 2 - DDR3U
+ # 3 - DDR3All
+ # 4 - LPDDR2
+ # 5 - LPDDR3
+ # 6 - DDR4
+ # @Prompt DRAM Type + # @ValidList 0x80000001 | 0, 1, 2, 3, 4, 5, 6 + gVlvRefCodePkgTokenSpaceGuid.PcdDramType|1 + + ## Please populate DIMM slot 0 if only one DIMM is supported. + # 0 - Disable
+ # 1 - Enable
+ # @Prompt DIMM 0 Enable + # @ValidList 0x80000001 | 0, 1 + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|1 + + ## DIMM 1 has to be identical to DIMM 0. + # 0 - Disable
+ # 1 - Enable
+ # @Prompt DIMM 1 Enable Type + # @ValidList 0x80000001 | 0, 1 + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0 + + ## DRAM device data width. + # 0 - x8
+ # 1 - x16
+ # 2 - x32
+ # @Prompt DIMM_DWIDTH + # @ValidList 0x80000001 | 0, 1, 2 + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|1 + + ## DRAM device data density. + # 0 - 1 Gbit
+ # 1 - 2 Gbit
+ # 2 - 4 Gbit
+ # 3 - 8 Gbit
+ # @Prompt DIMM_Density + # @ValidList 0x80000001 | 0, 1, 2, 3 + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|2 + + ## DRAM device data bus width. + # 0 - 8 bits
+ # 1 - 16 bits
+ # 2 - 32 bits
+ # 3 - 64 bits
+ # @Prompt DIMM_BusWidth + # @ValidList 0x80000001 | 0, 1, 2, 3 + gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|3 + + ## Ranks Per DIMM or Sides Per DIMM. + # 0 - 1 Rank
+ # 1 - 2 Ranks
+ # @Prompt DIMM_Sides + # @ValidList 0x80000001 | 0, 1 + gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0 + + ## tCL.

+ # @Prompt tCL + gVlvRefCodePkgTokenSpaceGuid.PcdTcl|11 + + ## tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. + # @Prompt tRP_tRCD + gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|11 + + ## tWR in DRAM clk. + # @Prompt tWR + gVlvRefCodePkgTokenSpaceGuid.PcdTwr|12 + + ## tWTR in DRAM clk. + # @Prompt tWTR + gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|6 + + ## tRRD in DRAM clk. + # @Prompt tRRD + gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|6 + + ## tRTP in DRAM clk. + # @Prompt tRTP + gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|6 + + ## tFAW in DRAM clk. + # @Prompt tFAW + gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|32 + + # + # End of MRC parameters. + # + ############################################################################################### + +[PcdsDynamicHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout" + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gEfiBootStateGuid|0x0|TRUE + + +[PcdsDynamicDefault.common.DEFAULT] + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 + !if $(TPM_ENABLED) == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd, 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13} + !endif + !if $(FTPM_ENABLE) == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd, 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13} + !endif + + ## This PCD defines the video horizontal resolution. + # This PCD could be set to 0 then video resolution could be at highest resolution. + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + ## This PCD defines the video vertical resolution. + # This PCD could be set to 0 then video resolution could be at highest resolution. + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + + ## This PCD defines the Console output column and the default value is 25 according to UEFI spec. + # This PCD could be set to 0 then console output could be at max column and max row. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 + ## This PCD defines the Console output row and the default value is 80 according to UEFI spec. + # This PCD could be set to 0 then console output could be at max column and max row. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100 + + ## The PCD is used to specify the video horizontal resolution of text setup. + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800 + ## The PCD is used to specify the video vertical resolution of text setup. + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600 + ## The PCD is used to specify the console output column of text setup. + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100 + ## The PCD is used to specify the console output column of text setup. + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|31 + +!if $(TPM_ENABLED) == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1 +!endif + + gPlatformModuleTokenSpaceGuid.PcdRtcPowerFailure|FALSE + +[PcdsDynamicExDefault.common.DEFAULT] + gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040 + gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId|0 + gEfiVLVTokenSpaceGuid.PcdProductSerialNumber|0 + gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable|TRUE + gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur|FALSE + gEfiVLVTokenSpaceGuid.PcdFTPMErrorSkip|FALSE + gEfiVLVTokenSpaceGuid.PcdFTPMCommand|0 + gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0 + gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE + gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0 + gEfiCpuTokenSpaceGuid.PcdCpuS3DataAddress|0 + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugDataAddress|0 + gEfiCpuTokenSpaceGuid.PcdCpuCallbackSignal|0 + gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer|0 + gEfiVLVTokenSpaceGuid.PcdCpuLockBoxDataAddress|0 + gEfiVLVTokenSpaceGuid.PcdCpuSmramCpuDataAddress|0 + gEfiVLVTokenSpaceGuid.PcdCpuLockBoxSize|0 + gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE + +!if $(CAPSULE_ENABLE) + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100 + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x7b, 0x26, 0x96, 0x40, 0x0a, 0xda, 0xeb, 0x42, 0xb5, 0xeb, 0xfe, 0xf3, 0x1d, 0x20, 0x7c, 0xb4} + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0x59, 0x3A, 0xD8, 0x14, 0x10, 0xA8, 0x56, 0x45, 0x81, 0x92, 0x1C, 0x0A, 0x59, 0x3C, 0x06, 0x5C} +!endif + + +[Components.IA32] + +!if $(CAPSULE_ENABLE) + # FMP image decriptor + Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } +!endif + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SecCore.inf + + !if $(MINNOW2_FSP_BUILD) == TRUE + IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf { + !if $(TARGET) == DEBUG + + + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !endif + } + Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf + IntelFspWrapperPkg/FspInitPei/FspInitPei.inf { + !if $(TARGET) == DEBUG + + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !endif + } + !endif + + MdeModulePkg/Core/Pei/PeiMain.inf { +!if $(TARGET) == DEBUG + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E +!endif + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 + } + + $(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf { +!if $(TARGET) == DEBUG + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E +!endif + } + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MemoryInit.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 + + !if $(FTPM_ENABLE)==TRUE + *_*_IA32_CC_FLAGS = /D FTPM_ENABLE + !endif + } + +!if $(RC_BINARY_RELEASE) == TRUE + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SeCUma.inf +!endif + +!if $(FTPM_ENABLE) == TRUE +$(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fTPMInitPeim.inf +!endif + +!if $(RC_BINARY_RELEASE) == TRUE + $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf { + + *_*_IA32_CC_FLAGS = /DRC_BINARY_RELEASE + !if $(TARGET) == DEBUG + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E + !endif + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } +!endif + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf{ + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + } +!endif + +!if $(FTPM_ENABLE) == TRUE + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Tpm2DeviceSeCPei.inf +!endif + +!if $(TPM_ENABLED) == TRUE + SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf + SecurityPkg/Tcg/TcgPei/TcgPei.inf { + + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf +} +!endif + + $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6 + +!if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } + $(PLATFORM_PACKAGE)/FvInfoPei/FvInfoPei.inf + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/VlvInitPeim.inf +!if $(PCIESC_ENABLE) == TRUE + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchEarlyInitPeim.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 + } +!endif + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchInitPeim.inf + + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSmbusArpDisabled.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSpiPeim.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmAccess.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmControl.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/CpuPeim.inf + UefiCpuPkg/CpuIoPei/CpuIoPei.inf + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MpS3.inf + EdkCompatibilityPkg/Compatibility/AcpiVariableHobOnSmramReserveHobThunk/AcpiVariableHobOnSmramReserveHobThunk.inf + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf +!if $(CAPSULE_ENABLE) == TRUE + MdeModulePkg/Universal/CapsulePei/CapsulePei.inf +!endif + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + +!if $(LZMA_ENABLE) == TRUE + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf +!endif + } + + + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + +!if $(FTPM_ENABLE) == TRUE + SecurityPkg/Tcg/TrEEPei/TrEEPei.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 + + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } +!endif +!if $(TPM_ENABLED) == TRUE + SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } +!endif +!if $(ACPI50_ENABLE) == TRUE + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf{ + + TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf + } + +!endif +!if $(PERFORMANCE_ENABLE) == TRUE + MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf +!endif +[Components.X64] + !if $(MINNOW2_FSP_BUILD) == TRUE + IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf { + !if $(TARGET) == DEBUG + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 + + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !endif + } + + !endif + # + # EDK II Related Platform codes + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 + +!if $(DXE_CRC32_SECTION_ENABLE) == TRUE + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf +!endif +!if $(LZMA_ENABLE) == TRUE + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf +!endif +!if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + } + IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043 + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 + + !if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !endif + + ICC:*_*_*_CC_FLAGS = /D MDEPKG_NDEBUG + GCC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf { + +!if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + } + +!if $(DXE_ARCHITECTURE) == X64 +!if $(CAPSULE_ENABLE) == TRUE + MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + } +!endif +!endif + + MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf{ + + NULL|SecurityPkg/Library/DxeImageAuthenticationStatusLib/DxeImageAuthenticationStatusLib.inf +!if $(SECURE_BOOT_ENABLE) == TRUE + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf +!endif +!if $(USER_IDENTIFICATION_ENABLE) + NULL|SecurityPkg/Library/DxeDeferImageLoadLib/DxeDeferImageLoadLib.inf +!endif +!if $(TPM_ENABLED) == TRUE + NULL|SecurityPkg/Library/DxeTpmMeasureBootLib/DxeTpmMeasureBootLib.inf +!endif +!if $(FTPM_ENABLE) == TRUE + NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib.inf +!endif + } + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MpCpu.inf + $(PLATFORM_PACKAGE)/Metronome/Metronome.inf + +!if $(HTTP_BOOT_SUPPORT) == TRUE + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf{ + + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf + !if $(FTPM_ENABLE) == TRUE + Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2DeviceLibSeC.inf + !else + TrEEPhysicalPresenceLib|$(PLATFORM_PACKAGE)/Library/DxeTrEEPhysicalPresenceLibNull/DxeTrEEPhysicalPresenceLibNull.inf + !endif + } + MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + } +!else + IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf{ + + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf + !if $(FTPM_ENABLE) == TRUE + Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2DeviceLibSeC.inf + !else + TrEEPhysicalPresenceLib|$(PLATFORM_PACKAGE)/Library/DxeTrEEPhysicalPresenceLibNull/DxeTrEEPhysicalPresenceLibNull.inf + !endif + } + $(PLATFORM_PACKAGE)/UiApp/UiApp.inf +!endif + MdeModulePkg/Universal/LoadFileOnFv2/LoadFileOnFv2.inf + MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf + + + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf + } + $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf +!if $(SECURE_BOOT_ENABLE) == TRUE + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf { + + PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf + + # + # Specify GUID gEfiIfrBootMaintenanceGuid, to install Secure Boot Configuration menu + # into Boot Maintenance Manager menu + # + *_*_*_VFR_FLAGS = -g b2dedc91-d59f-48d2-898a-12490c74a4e0 + } +!endif + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf { + + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + } + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf { + !if $(TARGET) == DEBUG + + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf + !endif + } + + $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf + +!if $(DATAHUB_ENABLE) == TRUE + IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0 + } +!endif + IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandlerDxe/DatahubStatusCodeHandlerDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchS3SupportDxe.inf + !if $(USE_HPET_TIMER) == TRUE + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf + !else + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmartTimer.inf + !endif + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmControl.inf + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmbusDxe.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/IntelPchLegacyInterrupt.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchReset.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitDxe.inf{ + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043 + } + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitSmm.inf + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmiDispatcher.inf + +!if $(PCIESC_ENABLE) == TRUE + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPcieSmm.inf +!endif + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiRuntime.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPolicyInitDxe.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchBiosWriteProtect.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmAccess.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PciHostBridge.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/VlvInitDxe.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/GraphicDxeInitSmm.inf + + IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.inf + + PerformancePkg/Dp_App/Dp.inf { + + !if $(PERFORMANCE_ENABLE) == TRUE + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf + !endif + } + + Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf{ + +!if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Dptf.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PnpDxe.inf + +!if $(SEC_ENABLE) == TRUE + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/HeciDrv.inf { +!if $(SEC_DEBUG_INFO_ENABLE) == TRUE + + *_*_X64_CC_FLAGS = /DSEC_DEBUG_INFO=1 +!else + + *_*_X64_CC_FLAGS = /DSEC_DEBUG_INFO=0 +!endif + } + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SeCPolicyInitDxe.inf +!endif + +!if $(FTPM_ENABLE) == TRUE + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Tpm2DeviceSeCDxe.inf + SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf + SecurityPkg/Tcg/MemoryOverwriteRequestControlLock/TcgMorLockSmm.inf + SecurityPkg/Tcg/TrEEDxe/TrEEDxe.inf{ + + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2DeviceLibSeC.inf + } + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/FtpmSmm.inf +!endif +!if $(TPM_ENABLED) == TRUE + SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } + + SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + + # + # specify GUID gEfiIfrNotInTPVPageGuid, this page will not + # be showed in TPV page. + # + *_*_*_VFR_FLAGS = -g e58809f8-fbc1-48e2-883a-a30fdc4b441e + } + + SecurityPkg/Tcg/TcgDxe/TcgDxe.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + SecurityPkg/Tcg/TcgSmm/TcgSmm.inf +!endif + # + # EDK II Related Platform codes + # + $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf{ + + !if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !endif + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf + $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf + $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf + $(PLATFORM_PACKAGE)/PlatformRtcRuntimeDxe/PlatformRtcRuntimeDxe.inf + + + $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf + $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PlatformCpuPolicy.inf + $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf + $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf +!if $(GOP_DRIVER_ENABLE) == TRUE + $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf + +!endif + + + # + # SMM + # + MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000 + } + UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PowerManagement2.inf + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/DigitalThermalSensor.inf + + # + # ACPI + # + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043 + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + MdeModulePkg/Universal/Acpi/SmmS3SaveState/SmmS3SaveState.inf + + $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf + IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDxe.inf + Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf + + $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf + + $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf + + # + # PCI + # + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/ISPDxe.inf + + +# +# ISA +# + $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf + IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf + IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf + IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf + IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf + IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf +# +# eMMC/SD Card +# + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf + MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf + MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + +!if $(ACPI50_ENABLE) == TRUE + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf { + + TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf + } + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf { + + TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf + } + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf +!endif + +# +# IDE/SCSI/AHCI +# + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf +!if $(SATA_ENABLE) == TRUE + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SataController.inf +!endif + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf +!if $(SCSI_ENABLE) == TRUE + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf +!endif +# +# Console +# + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + + # + # USB + # +!if $(USB_ENABLE) == TRUE + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + Vlv2TbltDevicePkg/Override/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + +!endif + + # + # ECP + # + EdkCompatibilityPkg/Compatibility/FrameworkHiiOnUefiHiiThunk/FrameworkHiiOnUefiHiiThunk.inf + EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf + EdkCompatibilityPkg/Compatibility/SmmBaseOnSmmBase2Thunk/SmmBaseOnSmmBase2Thunk.inf + EdkCompatibilityPkg/Compatibility/SmmBaseHelper/SmmBaseHelper.inf + EdkCompatibilityPkg/Compatibility/SmmAccess2OnSmmAccessThunk/SmmAccess2OnSmmAccessThunk.inf + EdkCompatibilityPkg/Compatibility/SmmControl2OnSmmControlThunk/SmmControl2OnSmmControlThunk.inf + EdkCompatibilityPkg/Compatibility/FrameworkSmmStatusCodeOnPiSmmStatusCodeThunk/FrameworkSmmStatusCodeOnPiSmmStatusCodeThunk.inf + EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf + # + # SMBIOS + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmbiosMemory.inf + # + # CPU/FW Microde + # + Vlv2MiscBinariesPkg/Microcode/MicrocodeUpdates.inf { + + *_*_*_GENFW_FLAGS = -a 0x800 -p 0xFF + } + + + PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf + + +!if $(NETWORK_ENABLE) == TRUE + !if $(NETWORK_ISCSI_ENABLE) == TRUE + !if $(NETWORK_IP6_ENABLE) == TRUE + NetworkPkg/IScsiDxe/IScsiDxe.inf + !else + MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf + !endif + !endif + !if $(NETWORK_VLAN_ENABLE) == TRUE + MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + !endif + !if $(CSM_ENABLE) == TRUE + IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Snp16Dxe.inf + !endif +!endif + +!if $(NETWORK_ENABLE) == TRUE + # + # UEFI network modules + # + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf + + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf +!if $(HTTP_BOOT_SUPPORT) == TRUE + NetworkPkg/HttpDxe/HttpDxe.inf + NetworkPkg/HttpBootDxe/HttpBootDxe.inf + NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + NetworkPkg/DnsDxe/DnsDxe.inf + !if $(NETWORK_TLS_ENABLE) == TRUE + NetworkPkg/TlsDxe/TlsDxe.inf + NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf + !endif + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf +!endif + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000 + } + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + !if $(NETWORK_IP6_ENABLE) == TRUE + NetworkPkg/Ip6Dxe/Ip6Dxe.inf + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + NetworkPkg/IpSecDxe/IpSecDxe.inf + NetworkPkg/TcpDxe/TcpDxe.inf + NetworkPkg/Udp6Dxe/Udp6Dxe.inf + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + !endif + !if $(NETWORK_IP6_ENABLE) == TRUE + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + !else + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + !endif +!endif + +# +# capsule related drivers +# +IntelFrameworkModulePkg/Universal/FirmwareVolume/FwVolDxe/FwVolDxe.inf + +MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.inf + + Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.inf + Vlv2TbltDevicePkg/Application/SsdtUpdate/SsdtUpdate.inf + + !if $(CAPSULE_ENABLE) + MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + !endif + + !if $(CAPSULE_ENABLE) + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibRsa2048Sha256/FmpAuthenticationLibRsa2048Sha256.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + +[Components.IA32] + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { + + FILE_GUID = 232393E2-185F-4212-A986-2B01F529EED9 + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibRsa2048Sha256/FmpAuthenticationLibRsa2048Sha256.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + +[Components.X64] + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { + + FILE_GUID = F1E68873-DA37-4AA0-A12F-F0F8EBA2B24E + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibRsa2048Sha256/FmpAuthenticationLibRsa2048Sha256.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + +!endif + +[BuildOptions] +# +# Define Build Options both for EDK and EDKII drivers. +# + +# +# Define token for different Platform +# +!if $(MINNOW2_FSP_BUILD) == TRUE + DEFINE MINNOW2_FSP_OPTION = /DMINNOW2_FSP_BUILD +!else + DEFINE MINNOW2_FSP_OPTION = +!endif + +!if $(ENBDT_PF_BUILD) == TRUE + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1 +!else + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0 +!endif + + +!if $(CLKGEN_CONFIG_EXTRA_ENABLE) == TRUE + DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION = /DCLKGEN_CONFIG_EXTRA=1 +!else + DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION = +!endif + + + +!if $(PCIESC_ENABLE) == TRUE + DEFINE PCIESC_SUPPORT_BUILD_OPTION = /DPCIESC_SUPPORT=1 +!else + DEFINE PCIESC_SUPPORT_BUILD_OPTION = +!endif +!if $(SATA_ENABLE) == TRUE + DEFINE SATA_SUPPORT_BUILD_OPTION = /DSATA_SUPPORT=1 +!else + DEFINE SATA_SUPPORT_BUILD_OPTION = +!endif +!if $(ENBDT_S3_SUPPORT) == TRUE + DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT +!else + DEFINE ENBDT_S3_SUPPORT_OPTIONS = +!endif + +!if $(X64_CONFIG) == TRUE + DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1 +!else + DEFINE X64_BUILD_ENABLE = +!endif + +!if $(FTPM_ENABLE) == TRUE + DEFINE DSC_FTPM_BUILD_OPTIONS = /DFTPM_ENABLE +!else + DEFINE DSC_FTPM_BUILD_OPTIONS = +!endif +!if $(TPM_ENABLED) == TRUE + DEFINE DSC_TPM_BUILD_OPTIONS = /DTPM_ENABLED +!else + DEFINE DSC_TPM_BUILD_OPTIONS = +!endif + + + DEFINE EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS = $(MINNOW2_FSP_OPTION) $(MINNOW2_BUILD_OPTION) $(ENBDT_PF_ENABLE) $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) $(CLKGEN_CONFIG_EXTRA_BUILD_OPTION) $(SYSCTL_X0_CONVERT_BOARD_OPTION) $(ENBDT_S3_SUPPORT_OPTIONS) $(SATA_SUPPORT_BUILD_OPTION) $(PCIESC_SUPPORT_BUILD_OPTION) $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS) $(DSC_TPM_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +!if $(PERFORMANCE_ENABLE) == TRUE + DEFINE PDB_BUILD_OPTION = /Zi +!endif + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + MSFT:*_*_X64_GENFW_FLAGS = --keepexceptiontable + GCC:*_*_X64_GENFW_FLAGS = --keepexceptiontable + INTEL:*_*_X64_GENFW_FLAGS = --keepexceptiontable +!if $(TARGET) == DEBUG + DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS = /Od /Oy- +!endif +!else + DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS = + +!endif + +[BuildOptions.Common.EDK] + +# +# Define token for different Platform +# +!if $(ENBDT_PF_BUILD) == TRUE + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1 +!else + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0 +!endif + +!if $(PERFORMANCE_ENABLE) == TRUE + RELEASE_*_*_DLINK_FLAGS = /DEBUG +!endif + +!if $(S3_ENABLE) == TRUE + DEFINE DSC_S3_BUILD_OPTIONS = /DEFI_S3_RESUME +!else + DEFINE DSC_S3_BUILD_OPTIONS = +!endif + +!if $(ENBDT_S3_SUPPORT) == TRUE + DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT +!else + DEFINE ENBDT_S3_SUPPORT_OPTIONS = +!endif + +!if $(X64_CONFIG) == TRUE + DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1 +!else + DEFINE X64_BUILD_ENABLE = +!endif + + + DEFINE EDK_GLUE_LIB_DEBUG = + DEFINE DEBUG_BUILD_OPTIONS = /D EFI_DEBUG /D DEBUG_MODE=1 /GL- $(EDK_GLUE_LIB_DEBUG) /DEDKII_GLUE_DebugPrintErrorLevel=(EFI_D_ERROR) + DEFINE EDK_DSC_FEATURE_BUILD_OPTIONS = $(DSC_S3_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(DSC_SEC_BUILD_OPTIONS) $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS) $(DSC_TPM_BUILD_OPTIONS) $(SOFTSDV_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(QT_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /D$(PROJECT_SC_CHIPSET) + + DEFINE EDK_DSC_OTHER_BUILD_OPTIONS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SV_BUILD_OPTIONS) $(INTEL_FASTBOOT_BUILD_OPTION) + DEFINE EDK_DSC_GLOBAL_BUILD_OPTIONS = $(ENBDT_PF_ENABLE) $(EDK_DSC_FEATURE_BUILD_OPTIONS) $(EDK_DSC_OTHER_BUILD_OPTIONS) /D EFI_SPECIFICATION_VERSION=0x00020000 /D PI_SPECIFICATION_VERSION=0x00000009 /D TIANO_RELEASE_VERSION=0x00080006 /D SUPPORT_DEPRECATED_PCI_CFG_PPI /D CSM_SMMENTRY_PORT8DATA8 /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) /D MAX_VARIABLE_SIZE=0x2000 /D EFI_FIRMWARE_VENDOR="L/"INTEL/"" /D EFI_BUILD_VERSION="L/"EDKII/"" /DEFI_PEI_REPORT_STATUS_CODE_ON $(ENBDT_S3_SUPPORT_OPTIONS) + + *_*_IA32_ASM_FLAGS = /DEFI32 /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT + DEBUG_*_IA32_CC_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) + RELEASE_*_IA32_CC_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) + DEBUG_*_IA32_VFRPP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) + RELEASE_*_IA32_VFRPP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) + DEBUG_*_IA32_APP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) + RELEASE_*_IA32_APP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) + DEBUG_*_IA32_PP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) + RELEASE_*_IA32_PP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) + *_*_IA32_ASLPP_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) + *_*_IA32_ASLCC_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) + *_*_IA32_ASM16_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h + + *_*_X64_ASM_FLAGS = /DEFIX64 /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT + DEBUG_*_X64_CC_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) + RELEASE_*_X64_CC_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) + DEBUG_*_X64_VFRPP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) + RELEASE_*_X64_VFRPP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) + DEBUG_*_X64_APP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) + RELEASE_*_X64_APP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) + DEBUG_*_X64_PP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS) + RELEASE_*_X64_PP_FLAGS = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) + *_*_X64_ASLPP_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) + *_*_X64_ASLCC_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) + *_*_X64_ASM16_FLAGS = /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h + # *_*_*_BUILD_FLAGS = -s + *_*_*_VFR_FLAGS = -c + *_*_*_BUILD_FLAGS = -c + +[BuildOptions.Common.EDKII] + *_*_IA32_ASM_FLAGS = $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT + + *_*_IA32_CC_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_VFRPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_APP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_PP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) + + *_*_X64_CC_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SOURCE_LEVEL_DEBUG_BUILD_OPTIONS) + *_*_X64_VFRPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_APP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_PP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) + + +[Components.X64] + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SysFwUpdateCapsuleDxe.inf + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cBus.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043 + } + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cHost.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043 + } + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cPortA0Pio.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043 + } + + $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cMmioDeviceDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043 + } + diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgo.fdf b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgo.fdf new file mode 100644 index 00000000..f8f056b8 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformPkgo.fdf @@ -0,0 +1,1120 @@ +#/** @file +# FDF file of Platform. +# +# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] +DEFINE FLASH_BASE = 0xFFC00000 #The base address of the 4Mb FLASH Device. +DEFINE FLASH_SIZE = 0x00400000 #The flash size in bytes of the 4Mb FLASH Device. +DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 4Mb FLASH Device. +DEFINE FLASH_NUM_BLOCKS = 0x400 #The number of blocks in 4Mb FLASH Device. +DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000 +DEFINE FLASH_AREA_SIZE = 0x00800000 + +DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000 +DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00040000 +DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFC00000 + +DEFINE FLASH_REGION_VPD_OFFSET = 0x00040000 +DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000 + +DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0007E000 +DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000 + + +DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00080000 +DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000 + +!if $(MINNOW2_FSP_BUILD) == TRUE +DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x000C0000 +DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000 +DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFCC0000 + +DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x00108000 +DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000 +DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFD08000 + +!endif + +DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00110000 +DEFINE FLASH_REGION_FVMAIN_SIZE = 0x00210000 + +DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x00320000 +DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x00070000 + +DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x00390000 +DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x00070000 + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.Vlv] +BaseAddress = $(FLASH_BASE)|gPlatformModuleTokenSpaceGuid.PcdBiosImageBase #The base address of the 3Mb FLASH Device. +Size = $(FLASH_SIZE)|gPlatformModuleTokenSpaceGuid.PcdBiosImageSize #The flash size in bytes of the 3Mb FLASH Device. +ErasePolarity = 1 +BlockSize = $(FLASH_BLOCK_SIZE) #The block size in bytes of the 3Mb FLASH Device. +NumBlocks = $(FLASH_NUM_BLOCKS) #The number of blocks in 3Mb FLASH Device. + +# +#Flash location override based on actual flash map +# +SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress = $(FLASH_AREA_BASE_ADDRESS) +SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize = $(FLASH_AREA_SIZE) + +!if $(MINNOW2_FSP_BUILD) == TRUE +# put below PCD value setting into dsc file +#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(FLASH_REGION_VLVMICROCODE_BASE) +#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(FLASH_REGION_VLVMICROCODE_SIZE) +#SET gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset = 0x60 +#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = $(FLASH_AREA_BASE_ADDRESS) +#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize = $(FLASH_AREA_SIZE) +#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase = $(FLASH_REGION_FSPBIN_BASE) +#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize = $(FLASH_REGION_FSPBIN_SIZE) + +!endif +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# Fv Size can be adjusted; FVMAIN_COMPACT can be reduced to 0x120000, and FV_RECOVERY can be enlarged to 0x80000 +# +################################################################################ + # + # CPU Microcodes + # + +$(FLASH_REGION_VLVMICROCODE_OFFSET)|$(FLASH_REGION_VLVMICROCODE_SIZE) +gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize +FV = MICROCODE_FV +$(FLASH_REGION_VPD_OFFSET)|$(FLASH_REGION_VPD_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x80000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 7 Blocks * 0x10000 Bytes / Block + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if $(SECURE_BOOT_ENABLE) == TRUE + #Signature: gEfiAuthenticatedVariableGuid = + # { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + #Signature: gEfiVariableGuid = + # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + #Size: 0x3E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x03DFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xDF, 0x03, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + + +$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49, + 0xA0, 0xCE, 0x65, 0x0, 0xFD, 0x9F, 0x1B, 0x95, + + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x3, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +!if $(MINNOW2_FSP_BUILD) == TRUE + + $(FLASH_REGION_FSPBIN_OFFSET)|$(FLASH_REGION_FSPBIN_SIZE) + gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize + FILE = Vlv2MiscBinariesPkg/FspBinary/FvFsp.bin + + + $(FLASH_REGION_AZALIABIN_OFFSET)|$(FLASH_REGION_AZALIABIN_SIZE) + FILE = Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin + +!endif + + # + # Main Block + # +$(FLASH_REGION_FVMAIN_OFFSET)|$(FLASH_REGION_FVMAIN_SIZE) +gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize +FV = FVMAIN_COMPACT + + # + # FV Recovery#2 + # +$(FLASH_REGION_FV_RECOVERY2_OFFSET)|$(FLASH_REGION_FV_RECOVERY2_SIZE) +gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size +FV = FVRECOVERY2 + + # + # FV Recovery + # +$(FLASH_REGION_FV_RECOVERY_OFFSET)|$(FLASH_REGION_FV_RECOVERY_SIZE) +gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize +FV = FVRECOVERY + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.MICROCODE_FV] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = FALSE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 { + $(OUTPUT_DIRECTORY)\$(TARGET)_$(TOOL_CHAIN_TAG)\$(DXE_ARCHITECTURE)\MicrocodeUpdates.bin +} + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.FVRECOVERY2] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092 + + + +INF $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf + +!if $(MINNOW2_FSP_BUILD) == FALSE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSmbusArpDisabled.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/VlvInitPeim.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchInitPeim.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSpiPeim.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmAccess.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmControl.inf +INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MpS3.inf +INF EdkCompatibilityPkg/Compatibility/AcpiVariableHobOnSmramReserveHobThunk/AcpiVariableHobOnSmramReserveHobThunk.inf +!endif + +INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf +!if $(TPM_ENABLED) == TRUE +INF SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf +INF SecurityPkg/Tcg/TcgPei/TcgPei.inf +INF SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf +!endif +!if $(FTPM_ENABLE) == TRUE +INF SecurityPkg/Tcg/TrEEPei/TrEEPei.inf #use PCD config +!endif +INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + +!if $(ACPI50_ENABLE) == TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf +!endif +!if $(PERFORMANCE_ENABLE) == TRUE +INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf +!endif + +[FV.FVRECOVERY] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270091 + + +!if $(MINNOW2_FSP_BUILD) == TRUE +INF IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf +!else +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SecCore.inf +!endif + +INF MdeModulePkg/Core/Pei/PeiMain.inf +!if $(MINNOW2_FSP_BUILD) == TRUE +INF Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf +INF IntelFspWrapperPkg/FspInitPei/FspInitPei.inf +!endif +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/CpuPeim.inf +INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf +INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + +INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf +INF $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf + +!if $(MINNOW2_FSP_BUILD) == FALSE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SeCUma.inf +!endif + +!if $(FTPM_ENABLE) == TRUE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fTPMInitPeim.inf +!endif + +!if $(SOURCE_DEBUG_ENABLE) == TRUE + INF SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf +!endif + +INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf + +!if $(CAPSULE_ENABLE) == TRUE +!if $(DXE_ARCHITECTURE) == X64 +INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf +INF MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf +!else +INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf +!endif +!endif + +!if $(MINNOW2_FSP_BUILD) == FALSE +!if $(PCIESC_ENABLE) == TRUE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchEarlyInitPeim.inf +!endif +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MemoryInit.inf +!endif + +!if $(CAPSULE_ENABLE) + # FMP image decriptor +INF RuleOverride = FMP_IMAGE_DESC Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +!endif + +[FV.FVMAIN] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5 + +APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + } + +FILE FREEFORM = C3E36D09-8294-4b97-A857-D5288FE33E28 { + SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITECTURE)/BiosId.bin + } + +FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) { + SECTION RAW = MdeModulePkg/Logo/Logo.bmp + } + + # + # EDK II Related Platform codes + # + + !if $(MINNOW2_FSP_BUILD) == TRUE + INF IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf + !endif + +INF MdeModulePkg/Core/Dxe/DxeMain.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf +!if $(ACPI50_ENABLE) == TRUE +INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf +INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf +INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf +!endif + + +INF IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf +INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MpCpu.inf +INF $(PLATFORM_PACKAGE)/Metronome/Metronome.inf +!if $(HTTP_BOOT_SUPPORT) == TRUE +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf +INF MdeModulePkg/Application/UiApp/UiApp.inf +!else +INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf +!endif +INF MdeModulePkg/Universal/LoadFileOnFv2/LoadFileOnFv2.inf +INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf +INF IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf + +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf +INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf +!if $(SECURE_BOOT_ENABLE) +INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf +!endif + +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf +INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf + + +INF $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf + +!if $(DATAHUB_ENABLE) == TRUE +INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf +!endif +INF IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandlerDxe/DatahubStatusCodeHandlerDxe.inf +INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Dptf.inf + + # + # EDK II Related Silicon codes + # +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchS3SupportDxe.inf + +!if $(USE_HPET_TIMER) == TRUE +INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf +!else +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmartTimer.inf +!endif +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmControl.inf + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmbusDxe.inf + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/IntelPchLegacyInterrupt.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchReset.inf + +!if $(MINNOW2_FSP_BUILD) == FALSE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitDxe.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitSmm.inf +!endif +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmiDispatcher.inf +!if $(PCIESC_ENABLE) == TRUE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPcieSmm.inf +!endif + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiRuntime.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPolicyInitDxe.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchBiosWriteProtect.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmAccess.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PciHostBridge.inf +!if $(MINNOW2_FSP_BUILD) == FALSE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/VlvInitDxe.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/GraphicDxeInitSmm.inf +!else +INF IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.inf +INF Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf +!endif +!if $(MINNOW2_FSP_BUILD) == FALSE + !if $(SEC_ENABLE) == TRUE + INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/HeciDrv.inf + INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SeCPolicyInitDxe.inf + !endif +!endif +!if $(TPM_ENABLED) == TRUE +INF SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf +INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf +INF RuleOverride = DRIVER_ACPITABLE SecurityPkg/Tcg/TcgSmm/TcgSmm.inf +!endif +!if $(FTPM_ENABLE) == TRUE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Tpm2DeviceSeCPei.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Tpm2DeviceSeCDxe.inf +INF SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf +INF SecurityPkg/Tcg/MemoryOverwriteRequestControlLock/TcgMorLockSmm.inf +INF SecurityPkg/Tcg/TrEEDxe/TrEEDxe.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/FtpmSmm.inf +!endif + +# +# EDK II Related Platform codes +# +INF $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf +INF $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf +INF $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf +INF $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf +INF $(PLATFORM_PACKAGE)/PlatformRtcRuntimeDxe/PlatformRtcRuntimeDxe.inf +INF $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf +INF $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PlatformCpuPolicy.inf +INF $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf +INF $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf +!if $(GOP_DRIVER_ENABLE) == TRUE + INF $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf + FILE DRIVER = FF0C8745-3270-4439-B74F-3E45F8C77064 { + SECTION DXE_DEPEX_EXP = {gPlatformGOPPolicyGuid} + SECTION PE32 = Vlv2MiscBinariesPkg/GOP/7.2.1011/RELEASE_VS2008x86/$(DXE_ARCHITECTURE)/IntelGopDriver.efi + SECTION UI = "IntelGopDriver" +} +!endif + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PnpDxe.inf + # + # SMM + # +INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf +INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf +INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf +INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf +INF $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PowerManagement2.inf +# INF Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/Smm/DigitalThermalSensor.inf +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/DigitalThermalSensor.inf + # + # ACPI + # +INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf +INF $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf +INF IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDxe.inf +INF RuleOverride = ACPITABLE2 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf + +INF RuleOverride = ACPITABLE $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf + +INF $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf + +INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf +INF MdeModulePkg/Universal/Acpi/SmmS3SaveState/SmmS3SaveState.inf + + # + # PCI + # +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/ISPDxe.inf + + +# +# ISA +# +INF $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf +INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf +INF IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf +!if $(SOURCE_DEBUG_ENABLE) != TRUE +INF IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf +!endif +#INF IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf +#INF IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf + +# +# eMMC/SD Card +# +INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf +INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf +INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + +# +# IDE/SCSI/AHCI +# +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf +!if $(SATA_ENABLE) == TRUE +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SataController.inf +# + +# +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf +!if $(SCSI_ENABLE) == TRUE +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf +!endif +# +!endif +# Console +# +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf +INF IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + # + # USB + # +!if $(USB_ENABLE) == TRUE +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF Vlv2TbltDevicePkg/Override/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf +!endif + + # + # ECP + # +INF EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf +INF EdkCompatibilityPkg/Compatibility/SmmBaseOnSmmBase2Thunk/SmmBaseOnSmmBase2Thunk.inf +INF EdkCompatibilityPkg/Compatibility/SmmBaseHelper/SmmBaseHelper.inf +INF EdkCompatibilityPkg/Compatibility/SmmAccess2OnSmmAccessThunk/SmmAccess2OnSmmAccessThunk.inf +INF EdkCompatibilityPkg/Compatibility/SmmControl2OnSmmControlThunk/SmmControl2OnSmmControlThunk.inf +INF EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf + # + # SMBIOS + # +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf +INF $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf + +INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmbiosMemory.inf + + # + # Legacy Modules + # +INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf + +# +# FAT file system +# +FILE DRIVER = 961578FE-B6B7-44c3-AF35-6BC705CD2B1F { + SECTION PE32 = FatBinPkg/EnhancedFatDxe/$(EDK_DXE_ARCHITECTURE)/Fat.efi + } +# +# UEFI Shell And /or HTTP Boot +# +!if $(HTTP_BOOT_SUPPORT) == TRUE +FILE APPLICATION = 7C04A583-9E3E-4f1c-AD65-E05268D0B4D1 { +# SECTION PE32 = EdkShellBinPkg/FullShell/$(EDK_DXE_ARCHITECTURE)/Shell_Full.efi + SECTION PE32 = ShellBinPkg/UefiShell/$(EDK_DXE_ARCHITECTURE)/Shell.efi + } +!else +!if $(BUILD_NEW_SHELL) == TRUE +# FILE APPLICATION = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile) { +# SECTION PE32 = $(OUTPUT_DIRECTORY)/DEBUG_VS2010x86/X64/shell.efi +# } + INF ShellPkg/Application/Shell/Shell.inf + +!else +FILE APPLICATION = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile) { +# SECTION PE32 = EdkShellBinPkg/FullShell/$(EDK_DXE_ARCHITECTURE)/Shell_Full.efi + SECTION PE32 = ShellBinPkg/UefiShell/$(EDK_DXE_ARCHITECTURE)/Shell.efi + } + +!endif +!endif + + +!if $(GOP_DRIVER_ENABLE) == TRUE +FILE FREEFORM = 878AC2CC-5343-46F2-B563-51F89DAF56BA { + SECTION RAW = Vlv2MiscBinariesPkg/GOP/7.2.1011/VBT/MNW2/Vbt.bin + SECTION UI = "IntelGopVbt" +} +!endif + +# +# Network Modules +# +!if $(NETWORK_ENABLE) == TRUE + FILE DRIVER = 22DE1691-D65D-456a-993E-A253DD1F308C { + SECTION PE32 = Vlv2MiscBinariesPkg/UNDI/RtkUndiDxe/$(DXE_ARCHITECTURE)/RtkUndiDxe.efi + SECTION UI = "UNDI" + } + # 32-bit E7006X3.EFI UNDI driver is not available. + !if $(DXE_ARCHITECTURE) == X64 + FILE DRIVER = 0270D660-E7E2-4C6B-94B1-16B7FCD49351 { + SECTION PE32 = Vlv2MiscBinariesPkg/UNDI/I211PcieUndiDxe/$(DXE_ARCHITECTURE)/E7006X3.EFI + SECTION UI = "UNDI" + } + !endif + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + !if $(HTTP_BOOT_SUPPORT) == TRUE + INF NetworkPkg/HttpDxe/HttpDxe.inf + INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf + INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + INF NetworkPkg/DnsDxe/DnsDxe.inf + !if $(NETWORK_TLS_ENABLE) == TRUE + INF NetworkPkg/TlsDxe/TlsDxe.inf + INF NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf + !endif + INF RuleOverride = DRIVER_ACPITABLE MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + !endif + !if $(NETWORK_IP6_ENABLE) == TRUE + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + INF NetworkPkg/IpSecDxe/IpSecDxe.inf + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + !endif + !if $(NETWORK_IP6_ENABLE) == TRUE + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF NetworkPkg/TcpDxe/TcpDxe.inf + !else + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + !endif + !if $(NETWORK_VLAN_ENABLE) == TRUE + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + !endif + !if $(NETWORK_ISCSI_ENABLE) == TRUE + !if $(NETWORK_IP6_ENABLE) == TRUE + INF NetworkPkg/IScsiDxe/IScsiDxe.inf + !else + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf + !endif + !endif +!endif + +!if $(CAPSULE_ENABLE) +INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf +!endif +!if $(CAPSULE_ENABLE) +INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf +!endif + +!if $(CAPSULE_ENABLE) +FILE FREEFORM = PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiRsa2048Sha256TestPublicKeyFileGuid) { + SECTION RAW = BaseTools/Source/Python/Rsa2048Sha256Sign/TestSigningPublicKey.bin + SECTION UI = "Rsa2048Sha256TestSigningPublicKey" + } +!endif + +[FV.FVMAIN_COMPACT] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { +!if $(LZMA_ENABLE) == TRUE +# LZMA Compress + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } +!else +!if $(DXE_COMPRESS_ENABLE) == TRUE +# Tiano Compress + SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } +!else +# No Compress + SECTION COMPRESS PI_NONE { + SECTION FV_IMAGE = FVMAIN + } +!endif +!endif + } + +[FV.SETUP_DATA] +BlockSize = $(FLASH_BLOCK_SIZE) +#NumBlocks = 0x10 +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + +!if $(CAPSULE_ENABLE) +[FV.CapsuleDispatchFv] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +INF FILE_GUID=232393E2-185F-4212-A986-2B01F529EED9 USE=IA32 SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf +INF FILE_GUID=F1E68873-DA37-4AA0-A12F-F0F8EBA2B24E USE=X64 SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf + + +!endif + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + PE32 PE32 Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi + RAW BIN Align = 16 |.com + } + +[Rule.Common.SEC.BINARY] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + PE32 PE32 Align = 8 |.efi + RAW BIN Align = 16 |.com + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.PEIM.BINARY] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional |.depex + PE32 PE32 Align = Auto |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.PEIM.BIOSID] + FILE PEIM = $(NAMED_GUID) { + RAW BIN BiosId.bin + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED.APINIT] + FILE RAW = $(NAMED_GUID) Fixed Align=4K { + RAW SEC_BIN |.com + } +#cjia 2011-07-21 +[Rule.Common.USER_DEFINED.LEGACY16] + FILE FREEFORM = $(NAMED_GUID) { + UI STRING="$(MODULE_NAME)" Optional + RAW BIN |.bin + } +#cjia + +[Rule.Common.USER_DEFINED.ASM16] + FILE FREEFORM = $(NAMED_GUID) { + UI STRING="$(MODULE_NAME)" Optional + RAW BIN |.com + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.NATIVE_BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER.DRIVER_ACPITABLE] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_SMM_DRIVER] + FILE SMM = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_SMM_DRIVER.BINARY] + FILE SMM = $(NAMED_GUID) { + SMM_DEPEX SMM_DEPEX |.depex + PE32 PE32 |.efi + RAW BIN Optional |.aml + RAW ASL Optional |.aml + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_SMM_DRIVER.DRIVER_ACPITABLE] + FILE SMM = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.SMM_CORE] + FILE SMM_CORE = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.SMM_CORE.BINARY] + FILE SMM_CORE = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.UI] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="Enter Setup" + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED] + FILE FREEFORM = $(NAMED_GUID) { + UI STRING="$(MODULE_NAME)" Optional + RAW BIN |.bin + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.USER_DEFINED.ACPITABLE2] + FILE FREEFORM = $(NAMED_GUID) { + RAW ASL Optional |.aml + } + +[Rule.Common.USER_DEFINED.LOGO] + FILE FREEFORM = $(NAMED_GUID) { + RAW BIN |.bmp + } + +[Rule.Common.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.PEIM.FMP_IMAGE_DESC] + FILE PEIM = $(NAMED_GUID) { + RAW BIN |.acpi + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformSetupDxe/SystemComponent.vfi b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformSetupDxe/SystemComponent.vfi index e21f8803..097d3248 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformSetupDxe/SystemComponent.vfi +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformSetupDxe/SystemComponent.vfi @@ -1,6 +1,6 @@ // // -// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+// Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
// // This program and the accompanying materials are licensed and made available under // the terms and conditions of the BSD License that accompanies this distribution. @@ -81,6 +81,11 @@ form formid = SYSTEM_COMPONENT_FORM_ID, option text = STRING_TOKEN(STR_ON), value = 1, flags = RESET_REQUIRED; endoneof; - + string varid = Setup.SystemUuid, + prompt = STRING_TOKEN (STR_SYSTEM_UUID_TITLE), + help = STRING_TOKEN (STR_SYSTEM_UUID_HELP), + minsize = 0, + maxsize = 36, + endstring; endform; diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni index ad4cf644..20fcde03 100644 Binary files a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni and b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni differ diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction - Copy.c b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction - Copy.c index 1d47e4ac..40a84a8f 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction - Copy.c +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction - Copy.c @@ -1,6 +1,6 @@ /*++ -Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. @@ -31,147 +31,211 @@ Abstract: #include "Library/DebugLib.h" #include #include +#include +#include +#include extern EFI_PLATFORM_INFO_HOB *mPlatformInfo; -static EFI_SMBIOS_HANDLE mSmbiosHandleType1; +EFI_GUID mSystemConfigurationGuid = SYSTEM_CONFIGURATION_GUID; + + +/** + Return the description for network boot device. + + @param Handle Controller handle. + + @return The description string. +**/ +CHAR16 * +GetNetworkDescription ( + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + MAC_ADDR_DEVICE_PATH *Mac; + CHAR16 *Description; + UINTN DescriptionSize; + + Status = gBS->OpenProtocol ( + Handle, + &gEfiLoadFileProtocolGuid, + NULL, + gImageHandle, + Handle, + EFI_OPEN_PROTOCOL_TEST_PROTOCOL + ); + if (EFI_ERROR (Status)) { + return NULL; + } + + Status = gBS->OpenProtocol ( + Handle, + &gEfiDevicePathProtocolGuid, + (VOID **) &DevicePath, + gImageHandle, + Handle, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status) || (DevicePath == NULL)) { + return NULL; + } + + // + // The PXE device path is like: + // ....../Mac(...)[/Vlan(...)][/Wi-Fi(...)] + // ....../Mac(...)[/Vlan(...)][/Wi-Fi(...)]/IPv4(...) + // ....../Mac(...)[/Vlan(...)][/Wi-Fi(...)]/IPv6(...) + // + // The HTTP device path is like: + // ....../Mac(...)[/Vlan(...)][/Wi-Fi(...)]/IPv4(...)/Uri(...) + // ....../Mac(...)[/Vlan(...)][/Wi-Fi(...)]/IPv6(...)/Uri(...) + // + while (!IsDevicePathEnd (DevicePath) && + ((DevicePathType (DevicePath) != MESSAGING_DEVICE_PATH) || + (DevicePathSubType (DevicePath) != MSG_MAC_ADDR_DP)) + ) { + DevicePath = NextDevicePathNode (DevicePath); + } + + if (IsDevicePathEnd (DevicePath)) { + return NULL; + } + + Mac = (MAC_ADDR_DEVICE_PATH *) DevicePath; + DevicePath = NextDevicePathNode (DevicePath); + + // + // Skip the optional Wi-Fi node + // + if ((DevicePathType (DevicePath) == MESSAGING_DEVICE_PATH) && + (DevicePathSubType (DevicePath) == MSG_WIFI_DP) + ) { + DevicePath = NextDevicePathNode (DevicePath); + } + + // + // Build description like below: + // "PXEv6 (MAC:112233445566 VLAN1)" + // "HTTPv4 (MAC:112233445566)" + // + DescriptionSize = sizeof (L"112233445566"); + Description = AllocatePool (DescriptionSize); + ASSERT (Description != NULL); + UnicodeSPrint ( + Description, DescriptionSize, + L"%02x%02x%02x%02x%02x%02x", + Mac->MacAddress.Addr[0], Mac->MacAddress.Addr[1], Mac->MacAddress.Addr[2], + Mac->MacAddress.Addr[3], Mac->MacAddress.Addr[4], Mac->MacAddress.Addr[5] + ); + + return Description; +} + + + +CHAR16 * +GetMacAddressString( + ) +{ + EFI_HANDLE *Handles; + UINTN HandleCount; + UINT8 Index; + CHAR16 *MacAddressString = NULL; + + // + // Parse load file protocol + // + gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiLoadFileProtocolGuid, + NULL, + &HandleCount, + &Handles + ); + for (Index = 0; Index < HandleCount; Index++) { + + MacAddressString = GetNetworkDescription (Handles[Index]); + + if (MacAddressString != NULL) { + break; + } + } + + if (HandleCount != 0) { + FreePool (Handles); + } + + return MacAddressString; +} EFI_STATUS EFIAPI -UpdateSmbiosManuCallback ( +AddSmbiosManuCallback ( IN EFI_EVENT Event, IN VOID *Context ) { - EFI_STATUS Status; - EFI_HANDLE *Handles; - UINTN BufferSize; - CHAR16 *MacStr; - EFI_SMBIOS_PROTOCOL *Smbios; - UINTN SerialNumberOffset; - CHAR8 AsciiData[SMBIOS_STRING_MAX_LENGTH]; - - gBS->CloseEvent (Event); // Unload this event. - - DEBUG ((EFI_D_INFO, "Executing UpdateSmbiosManuCallback.\n")); - - // - //Get handle infomation - // - BufferSize = 0; - Handles = NULL; - Status = gBS->LocateHandle ( - ByProtocol, - &gEfiSimpleNetworkProtocolGuid, - NULL, - &BufferSize, - Handles - ); - - if (Status == EFI_BUFFER_TOO_SMALL) { - Handles = AllocateZeroPool(BufferSize); - if (Handles == NULL) { - return (EFI_OUT_OF_RESOURCES); - } - Status = gBS->LocateHandle( - ByProtocol, - &gEfiSimpleNetworkProtocolGuid, - NULL, - &BufferSize, - Handles - ); - } - - // - //Get the MAC string - // - Status = NetLibGetMacString ( - *Handles, - NULL, - &MacStr - ); - if (EFI_ERROR (Status)) { - return Status; - } - - ZeroMem (AsciiData, SMBIOS_STRING_MAX_LENGTH); - UnicodeStrToAsciiStr (MacStr, AsciiData); - - Status = gBS->LocateProtocol ( - &gEfiSmbiosProtocolGuid, - NULL, - (VOID *) &Smbios - ); - ASSERT_EFI_ERROR (Status); - - SerialNumberOffset = 4; - Status = Smbios->UpdateString ( - Smbios, - &mSmbiosHandleType1, - &SerialNumberOffset, - AsciiData - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - return EFI_SUCCESS; -} - - -/** - - Publish the smbios type 1. - - @param Event Event whose notification function is being invoked (gEfiDxeSmmReadyToLockProtocolGuid). - @param Context Pointer to the notification functions context, which is implementation dependent. - - @retval None - -**/ -MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) -{ - CHAR8 *OptionalStrStart; UINTN ManuStrLen; UINTN VerStrLen; UINTN PdNameStrLen; UINTN SerialNumStrLen; UINTN SkuNumberStrLen; - UINTN FamilyNameStrLen; + UINTN FamilyNameStrLen; EFI_STATUS Status; EFI_STRING Manufacturer; EFI_STRING ProductName; EFI_STRING Version; EFI_STRING SerialNumber; EFI_STRING SkuNumber; - EFI_STRING FamilyName; + EFI_STRING FamilyName; STRING_REF TokenToGet; EFI_SMBIOS_HANDLE SmbiosHandle; SMBIOS_TABLE_TYPE1 *SmbiosRecord; EFI_MISC_SYSTEM_MANUFACTURER *ForType1InputData; CHAR16 Buffer[40]; - CHAR16 *MacStr; CHAR16 PlatformNameBuffer[40]; - VOID *UpdateSmbiosManuCallbackNotifyReg; - EFI_EVENT UpdateSmbiosManuCallbackEvent; - static BOOLEAN CallbackIsInstalledT1 = FALSE; + CHAR16 *MacAddressString = NULL; + CHAR16 SerialNumberBuffer[sizeof (L"112233445566")]; + EFI_SMBIOS_PROTOCOL *Smbios; + SYSTEM_CONFIGURATION SetupVarBuffer; + UINTN VariableSize; + CHAR16 *Uuid; + UINT64 TempData; + UINTN Index; + static BOOLEAN RemoveTable = TRUE; + EFI_SMBIOS_TABLE_HEADER *Record; - ForType1InputData = (EFI_MISC_SYSTEM_MANUFACTURER *)RecordData; + + +if (Event != NULL) { + gBS->CloseEvent (Event); // Unload this event. +} + + DEBUG ((EFI_D_INFO, "Executing AddSmbiosManuCallback.\n")); + + + ForType1InputData = (EFI_MISC_SYSTEM_MANUFACTURER *)Context; // // First check for invalid parameters. // - if (RecordData == NULL || mPlatformInfo == NULL) { + if (Context == NULL || mPlatformInfo == NULL) { DEBUG ((EFI_D_INFO, "MISC_SMBIOS_TABLE_FUNCTION error.\n")); return EFI_INVALID_PARAMETER; } + Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID **) &Smbios); + ASSERT_EFI_ERROR (Status); + + if (BOARD_ID_MINNOW2_TURBOT == mPlatformInfo->BoardId) { - // - // Detect the board is Turbot board platform - // - UnicodeSPrint (PlatformNameBuffer, sizeof (PlatformNameBuffer),L"%s",L"Minnowboard Turbot "); + // + // Detect the board is Turbot board platform + // + UnicodeSPrint (PlatformNameBuffer, sizeof (PlatformNameBuffer),L"%s",L"Minnowboard Turbot "); } else { UnicodeSPrint (PlatformNameBuffer, sizeof (PlatformNameBuffer),L"%s",L"Minnowboard Max "); } @@ -237,9 +301,9 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) DEBUG ((EFI_D_ERROR, "D0 Stepping Detected\n")); break; default: - DEBUG ((EFI_D_ERROR, "Unknow Stepping Detected\n")); + DEBUG ((EFI_D_ERROR, "Unknow Stepping Detected\n")); break; - } + } if (BOARD_ID_MINNOW2_TURBOT == mPlatformInfo->BoardId) { UnicodeSPrint (Buffer, sizeof (Buffer),L"ADI"); @@ -266,8 +330,15 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) return EFI_UNSUPPORTED; } - MacStr = L"00000000"; - SerialNumber = MacStr; + + MacAddressString = GetMacAddressString(); + + if ( MacAddressString != NULL) { + UnicodeSPrint (SerialNumberBuffer, sizeof (L"112233445566"), L"%s", GetMacAddressString()); + HiiSetString (mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER), SerialNumberBuffer, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER); + SerialNumber = SmbiosMiscGetString (TokenToGet); SerialNumStrLen = StrLen(SerialNumber); if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) { return EFI_UNSUPPORTED; @@ -327,9 +398,49 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) // ForType1InputData->SystemUuid.Data1 = PcdGet32 (PcdProductSerialNumber); ForType1InputData->SystemUuid.Data4[0] = PcdGet8 (PcdEmmcManufacturerId); + VariableSize = sizeof (SYSTEM_CONFIGURATION); + Status = gRT->GetVariable ( + L"Setup", + &mSystemConfigurationGuid, + NULL, + &VariableSize, + &SetupVarBuffer + ); + ASSERT_EFI_ERROR (Status); + + Uuid = AllocatePool(sizeof(SetupVarBuffer.SystemUuid)); + ASSERT (Uuid != NULL); + CopyMem (Uuid, SetupVarBuffer.SystemUuid, sizeof(SetupVarBuffer.SystemUuid)); + + if(StrLen(Uuid) != 0) { + DEBUG ((EFI_D_INFO, "CustomerUuid %s\n",SetupVarBuffer.SystemUuid)); + ForType1InputData->SystemUuid.Data1 = (UINT32) StrHexToUint64 (Uuid); + ForType1InputData->SystemUuid.Data2 = (UINT16) StrHexToUint64 (Uuid + 9); + ForType1InputData->SystemUuid.Data3 = (UINT16) StrHexToUint64 (Uuid + 14); + ForType1InputData->SystemUuid.Data4[0] = (UINT8) (StrHexToUint64 (Uuid + 19) >> 8); + ForType1InputData->SystemUuid.Data4[1] = (UINT8) StrHexToUint64 (Uuid + 21); + TempData = StrHexToUint64 (Uuid + 24); + for(Index = sizeof(ForType1InputData->SystemUuid.Data4)/sizeof(UINT8); Index > 2; Index--) { + ForType1InputData->SystemUuid.Data4[Index-1] = (UINT8) TempData; + TempData = TempData >> 8; + } + } else if (MacAddressString != NULL) { + ForType1InputData->SystemUuid.Data1 = (UINT32)MacAddressString [0] + (((UINT32)MacAddressString [1]) << 16); + ForType1InputData->SystemUuid.Data2 = (UINT16)MacAddressString [2]; + ForType1InputData->SystemUuid.Data3 = (UINT16)MacAddressString [3]; + ForType1InputData->SystemUuid.Data4[0] = (UINT8)MacAddressString [4]; + ForType1InputData->SystemUuid.Data4[1] = (UINT8)(MacAddressString [5]); + ForType1InputData->SystemUuid.Data4[2] = (UINT8)MacAddressString [6]; + ForType1InputData->SystemUuid.Data4[3] = (UINT8)(MacAddressString [7]); + ForType1InputData->SystemUuid.Data4[4] = (UINT8)(MacAddressString [8]); + ForType1InputData->SystemUuid.Data4[5] = (UINT8)(MacAddressString [9]); + ForType1InputData->SystemUuid.Data4[6] = (UINT8)(MacAddressString [10]); + ForType1InputData->SystemUuid.Data4[7] = (UINT8)(MacAddressString [11]); + } CopyMem ((UINT8 *) (&SmbiosRecord->Uuid),&ForType1InputData->SystemUuid,16); + SmbiosRecord->WakeUpType = (UINT8)ForType1InputData->SystemWakeupType; OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); @@ -338,13 +449,28 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1); UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1); - UnicodeStrToAsciiStr(SkuNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1); + UnicodeStrToAsciiStr(SkuNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1); UnicodeStrToAsciiStr(FamilyName, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SkuNumberStrLen +1); // // Now we have got the full smbios record, call smbios protocol to add this record. // SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + if (RemoveTable == TRUE) { + Status = EFI_SUCCESS; + while (!EFI_ERROR(Status)) { + Status = Smbios->GetNext (Smbios, &SmbiosHandle, NULL, &Record, NULL); + if (Record->Type == SMBIOS_TYPE_SYSTEM_INFORMATION) { + Status = Smbios-> Remove( + Smbios, + SmbiosHandle + ); + RemoveTable = FALSE; + break; + } + } + } + Status = Smbios-> Add( Smbios, NULL, @@ -353,36 +479,43 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) ); FreePool(SmbiosRecord); - // - // gEfiSimpleNetworkProtocolGuid is ready - // - if (CallbackIsInstalledT1 == FALSE) { - CallbackIsInstalledT1 = TRUE; // Prevent more than 1 callback. - DEBUG ((EFI_D_INFO, "Create Smbios Type1 callback.\n")); - - mSmbiosHandleType1 = SmbiosHandle; - Status = gBS->CreateEvent ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - (EFI_EVENT_NOTIFY)UpdateSmbiosManuCallback, - RecordData, - &UpdateSmbiosManuCallbackEvent - ); - - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR (Status)) { - return Status; - - } - - Status = gBS->RegisterProtocolNotify ( - &gEfiSimpleNetworkProtocolGuid, - UpdateSmbiosManuCallbackEvent, - &UpdateSmbiosManuCallbackNotifyReg - ); - return Status; - } - - return EFI_SUCCESS; + return Status; +} + + +/** + + Publish the smbios type 1. + + @param Event Event whose notification function is being invoked (gEfiDxeSmmReadyToLockProtocolGuid). + @param Context Pointer to the notification functions context, which is implementation dependent. + + @retval None + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) +{ + EFI_STATUS Status = EFI_SUCCESS; + static BOOLEAN CallbackIsInstalledManu = FALSE; + EFI_EVENT AddSmbiosManuCallbackEvent; + + + Status = AddSmbiosManuCallback (NULL, RecordData); + + if (CallbackIsInstalledManu == FALSE) { + CallbackIsInstalledManu = TRUE; // Prevent more than 1 callback. + DEBUG ((EFI_D_INFO, "Create Smbios Manu callback.\n")); + + + Status = EfiCreateEventReadyToBootEx ( + TPL_CALLBACK, + (EFI_EVENT_NOTIFY)AddSmbiosManuCallback, + RecordData, + &AddSmbiosManuCallbackEvent + ); + } + + return Status; + } diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction.c b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction.c index 1d47e4ac..40a84a8f 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction.c +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction.c @@ -1,6 +1,6 @@ /*++ -Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. @@ -31,147 +31,211 @@ Abstract: #include "Library/DebugLib.h" #include #include +#include +#include +#include extern EFI_PLATFORM_INFO_HOB *mPlatformInfo; -static EFI_SMBIOS_HANDLE mSmbiosHandleType1; +EFI_GUID mSystemConfigurationGuid = SYSTEM_CONFIGURATION_GUID; + + +/** + Return the description for network boot device. + + @param Handle Controller handle. + + @return The description string. +**/ +CHAR16 * +GetNetworkDescription ( + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + MAC_ADDR_DEVICE_PATH *Mac; + CHAR16 *Description; + UINTN DescriptionSize; + + Status = gBS->OpenProtocol ( + Handle, + &gEfiLoadFileProtocolGuid, + NULL, + gImageHandle, + Handle, + EFI_OPEN_PROTOCOL_TEST_PROTOCOL + ); + if (EFI_ERROR (Status)) { + return NULL; + } + + Status = gBS->OpenProtocol ( + Handle, + &gEfiDevicePathProtocolGuid, + (VOID **) &DevicePath, + gImageHandle, + Handle, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status) || (DevicePath == NULL)) { + return NULL; + } + + // + // The PXE device path is like: + // ....../Mac(...)[/Vlan(...)][/Wi-Fi(...)] + // ....../Mac(...)[/Vlan(...)][/Wi-Fi(...)]/IPv4(...) + // ....../Mac(...)[/Vlan(...)][/Wi-Fi(...)]/IPv6(...) + // + // The HTTP device path is like: + // ....../Mac(...)[/Vlan(...)][/Wi-Fi(...)]/IPv4(...)/Uri(...) + // ....../Mac(...)[/Vlan(...)][/Wi-Fi(...)]/IPv6(...)/Uri(...) + // + while (!IsDevicePathEnd (DevicePath) && + ((DevicePathType (DevicePath) != MESSAGING_DEVICE_PATH) || + (DevicePathSubType (DevicePath) != MSG_MAC_ADDR_DP)) + ) { + DevicePath = NextDevicePathNode (DevicePath); + } + + if (IsDevicePathEnd (DevicePath)) { + return NULL; + } + + Mac = (MAC_ADDR_DEVICE_PATH *) DevicePath; + DevicePath = NextDevicePathNode (DevicePath); + + // + // Skip the optional Wi-Fi node + // + if ((DevicePathType (DevicePath) == MESSAGING_DEVICE_PATH) && + (DevicePathSubType (DevicePath) == MSG_WIFI_DP) + ) { + DevicePath = NextDevicePathNode (DevicePath); + } + + // + // Build description like below: + // "PXEv6 (MAC:112233445566 VLAN1)" + // "HTTPv4 (MAC:112233445566)" + // + DescriptionSize = sizeof (L"112233445566"); + Description = AllocatePool (DescriptionSize); + ASSERT (Description != NULL); + UnicodeSPrint ( + Description, DescriptionSize, + L"%02x%02x%02x%02x%02x%02x", + Mac->MacAddress.Addr[0], Mac->MacAddress.Addr[1], Mac->MacAddress.Addr[2], + Mac->MacAddress.Addr[3], Mac->MacAddress.Addr[4], Mac->MacAddress.Addr[5] + ); + + return Description; +} + + + +CHAR16 * +GetMacAddressString( + ) +{ + EFI_HANDLE *Handles; + UINTN HandleCount; + UINT8 Index; + CHAR16 *MacAddressString = NULL; + + // + // Parse load file protocol + // + gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiLoadFileProtocolGuid, + NULL, + &HandleCount, + &Handles + ); + for (Index = 0; Index < HandleCount; Index++) { + + MacAddressString = GetNetworkDescription (Handles[Index]); + + if (MacAddressString != NULL) { + break; + } + } + + if (HandleCount != 0) { + FreePool (Handles); + } + + return MacAddressString; +} EFI_STATUS EFIAPI -UpdateSmbiosManuCallback ( +AddSmbiosManuCallback ( IN EFI_EVENT Event, IN VOID *Context ) { - EFI_STATUS Status; - EFI_HANDLE *Handles; - UINTN BufferSize; - CHAR16 *MacStr; - EFI_SMBIOS_PROTOCOL *Smbios; - UINTN SerialNumberOffset; - CHAR8 AsciiData[SMBIOS_STRING_MAX_LENGTH]; - - gBS->CloseEvent (Event); // Unload this event. - - DEBUG ((EFI_D_INFO, "Executing UpdateSmbiosManuCallback.\n")); - - // - //Get handle infomation - // - BufferSize = 0; - Handles = NULL; - Status = gBS->LocateHandle ( - ByProtocol, - &gEfiSimpleNetworkProtocolGuid, - NULL, - &BufferSize, - Handles - ); - - if (Status == EFI_BUFFER_TOO_SMALL) { - Handles = AllocateZeroPool(BufferSize); - if (Handles == NULL) { - return (EFI_OUT_OF_RESOURCES); - } - Status = gBS->LocateHandle( - ByProtocol, - &gEfiSimpleNetworkProtocolGuid, - NULL, - &BufferSize, - Handles - ); - } - - // - //Get the MAC string - // - Status = NetLibGetMacString ( - *Handles, - NULL, - &MacStr - ); - if (EFI_ERROR (Status)) { - return Status; - } - - ZeroMem (AsciiData, SMBIOS_STRING_MAX_LENGTH); - UnicodeStrToAsciiStr (MacStr, AsciiData); - - Status = gBS->LocateProtocol ( - &gEfiSmbiosProtocolGuid, - NULL, - (VOID *) &Smbios - ); - ASSERT_EFI_ERROR (Status); - - SerialNumberOffset = 4; - Status = Smbios->UpdateString ( - Smbios, - &mSmbiosHandleType1, - &SerialNumberOffset, - AsciiData - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - return EFI_SUCCESS; -} - - -/** - - Publish the smbios type 1. - - @param Event Event whose notification function is being invoked (gEfiDxeSmmReadyToLockProtocolGuid). - @param Context Pointer to the notification functions context, which is implementation dependent. - - @retval None - -**/ -MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) -{ - CHAR8 *OptionalStrStart; UINTN ManuStrLen; UINTN VerStrLen; UINTN PdNameStrLen; UINTN SerialNumStrLen; UINTN SkuNumberStrLen; - UINTN FamilyNameStrLen; + UINTN FamilyNameStrLen; EFI_STATUS Status; EFI_STRING Manufacturer; EFI_STRING ProductName; EFI_STRING Version; EFI_STRING SerialNumber; EFI_STRING SkuNumber; - EFI_STRING FamilyName; + EFI_STRING FamilyName; STRING_REF TokenToGet; EFI_SMBIOS_HANDLE SmbiosHandle; SMBIOS_TABLE_TYPE1 *SmbiosRecord; EFI_MISC_SYSTEM_MANUFACTURER *ForType1InputData; CHAR16 Buffer[40]; - CHAR16 *MacStr; CHAR16 PlatformNameBuffer[40]; - VOID *UpdateSmbiosManuCallbackNotifyReg; - EFI_EVENT UpdateSmbiosManuCallbackEvent; - static BOOLEAN CallbackIsInstalledT1 = FALSE; + CHAR16 *MacAddressString = NULL; + CHAR16 SerialNumberBuffer[sizeof (L"112233445566")]; + EFI_SMBIOS_PROTOCOL *Smbios; + SYSTEM_CONFIGURATION SetupVarBuffer; + UINTN VariableSize; + CHAR16 *Uuid; + UINT64 TempData; + UINTN Index; + static BOOLEAN RemoveTable = TRUE; + EFI_SMBIOS_TABLE_HEADER *Record; - ForType1InputData = (EFI_MISC_SYSTEM_MANUFACTURER *)RecordData; + + +if (Event != NULL) { + gBS->CloseEvent (Event); // Unload this event. +} + + DEBUG ((EFI_D_INFO, "Executing AddSmbiosManuCallback.\n")); + + + ForType1InputData = (EFI_MISC_SYSTEM_MANUFACTURER *)Context; // // First check for invalid parameters. // - if (RecordData == NULL || mPlatformInfo == NULL) { + if (Context == NULL || mPlatformInfo == NULL) { DEBUG ((EFI_D_INFO, "MISC_SMBIOS_TABLE_FUNCTION error.\n")); return EFI_INVALID_PARAMETER; } + Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID **) &Smbios); + ASSERT_EFI_ERROR (Status); + + if (BOARD_ID_MINNOW2_TURBOT == mPlatformInfo->BoardId) { - // - // Detect the board is Turbot board platform - // - UnicodeSPrint (PlatformNameBuffer, sizeof (PlatformNameBuffer),L"%s",L"Minnowboard Turbot "); + // + // Detect the board is Turbot board platform + // + UnicodeSPrint (PlatformNameBuffer, sizeof (PlatformNameBuffer),L"%s",L"Minnowboard Turbot "); } else { UnicodeSPrint (PlatformNameBuffer, sizeof (PlatformNameBuffer),L"%s",L"Minnowboard Max "); } @@ -237,9 +301,9 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) DEBUG ((EFI_D_ERROR, "D0 Stepping Detected\n")); break; default: - DEBUG ((EFI_D_ERROR, "Unknow Stepping Detected\n")); + DEBUG ((EFI_D_ERROR, "Unknow Stepping Detected\n")); break; - } + } if (BOARD_ID_MINNOW2_TURBOT == mPlatformInfo->BoardId) { UnicodeSPrint (Buffer, sizeof (Buffer),L"ADI"); @@ -266,8 +330,15 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) return EFI_UNSUPPORTED; } - MacStr = L"00000000"; - SerialNumber = MacStr; + + MacAddressString = GetMacAddressString(); + + if ( MacAddressString != NULL) { + UnicodeSPrint (SerialNumberBuffer, sizeof (L"112233445566"), L"%s", GetMacAddressString()); + HiiSetString (mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER), SerialNumberBuffer, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER); + SerialNumber = SmbiosMiscGetString (TokenToGet); SerialNumStrLen = StrLen(SerialNumber); if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) { return EFI_UNSUPPORTED; @@ -327,9 +398,49 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) // ForType1InputData->SystemUuid.Data1 = PcdGet32 (PcdProductSerialNumber); ForType1InputData->SystemUuid.Data4[0] = PcdGet8 (PcdEmmcManufacturerId); + VariableSize = sizeof (SYSTEM_CONFIGURATION); + Status = gRT->GetVariable ( + L"Setup", + &mSystemConfigurationGuid, + NULL, + &VariableSize, + &SetupVarBuffer + ); + ASSERT_EFI_ERROR (Status); + + Uuid = AllocatePool(sizeof(SetupVarBuffer.SystemUuid)); + ASSERT (Uuid != NULL); + CopyMem (Uuid, SetupVarBuffer.SystemUuid, sizeof(SetupVarBuffer.SystemUuid)); + + if(StrLen(Uuid) != 0) { + DEBUG ((EFI_D_INFO, "CustomerUuid %s\n",SetupVarBuffer.SystemUuid)); + ForType1InputData->SystemUuid.Data1 = (UINT32) StrHexToUint64 (Uuid); + ForType1InputData->SystemUuid.Data2 = (UINT16) StrHexToUint64 (Uuid + 9); + ForType1InputData->SystemUuid.Data3 = (UINT16) StrHexToUint64 (Uuid + 14); + ForType1InputData->SystemUuid.Data4[0] = (UINT8) (StrHexToUint64 (Uuid + 19) >> 8); + ForType1InputData->SystemUuid.Data4[1] = (UINT8) StrHexToUint64 (Uuid + 21); + TempData = StrHexToUint64 (Uuid + 24); + for(Index = sizeof(ForType1InputData->SystemUuid.Data4)/sizeof(UINT8); Index > 2; Index--) { + ForType1InputData->SystemUuid.Data4[Index-1] = (UINT8) TempData; + TempData = TempData >> 8; + } + } else if (MacAddressString != NULL) { + ForType1InputData->SystemUuid.Data1 = (UINT32)MacAddressString [0] + (((UINT32)MacAddressString [1]) << 16); + ForType1InputData->SystemUuid.Data2 = (UINT16)MacAddressString [2]; + ForType1InputData->SystemUuid.Data3 = (UINT16)MacAddressString [3]; + ForType1InputData->SystemUuid.Data4[0] = (UINT8)MacAddressString [4]; + ForType1InputData->SystemUuid.Data4[1] = (UINT8)(MacAddressString [5]); + ForType1InputData->SystemUuid.Data4[2] = (UINT8)MacAddressString [6]; + ForType1InputData->SystemUuid.Data4[3] = (UINT8)(MacAddressString [7]); + ForType1InputData->SystemUuid.Data4[4] = (UINT8)(MacAddressString [8]); + ForType1InputData->SystemUuid.Data4[5] = (UINT8)(MacAddressString [9]); + ForType1InputData->SystemUuid.Data4[6] = (UINT8)(MacAddressString [10]); + ForType1InputData->SystemUuid.Data4[7] = (UINT8)(MacAddressString [11]); + } CopyMem ((UINT8 *) (&SmbiosRecord->Uuid),&ForType1InputData->SystemUuid,16); + SmbiosRecord->WakeUpType = (UINT8)ForType1InputData->SystemWakeupType; OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); @@ -338,13 +449,28 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1); UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1); - UnicodeStrToAsciiStr(SkuNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1); + UnicodeStrToAsciiStr(SkuNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1); UnicodeStrToAsciiStr(FamilyName, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SkuNumberStrLen +1); // // Now we have got the full smbios record, call smbios protocol to add this record. // SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + if (RemoveTable == TRUE) { + Status = EFI_SUCCESS; + while (!EFI_ERROR(Status)) { + Status = Smbios->GetNext (Smbios, &SmbiosHandle, NULL, &Record, NULL); + if (Record->Type == SMBIOS_TYPE_SYSTEM_INFORMATION) { + Status = Smbios-> Remove( + Smbios, + SmbiosHandle + ); + RemoveTable = FALSE; + break; + } + } + } + Status = Smbios-> Add( Smbios, NULL, @@ -353,36 +479,43 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) ); FreePool(SmbiosRecord); - // - // gEfiSimpleNetworkProtocolGuid is ready - // - if (CallbackIsInstalledT1 == FALSE) { - CallbackIsInstalledT1 = TRUE; // Prevent more than 1 callback. - DEBUG ((EFI_D_INFO, "Create Smbios Type1 callback.\n")); - - mSmbiosHandleType1 = SmbiosHandle; - Status = gBS->CreateEvent ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - (EFI_EVENT_NOTIFY)UpdateSmbiosManuCallback, - RecordData, - &UpdateSmbiosManuCallbackEvent - ); - - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR (Status)) { - return Status; - - } - - Status = gBS->RegisterProtocolNotify ( - &gEfiSimpleNetworkProtocolGuid, - UpdateSmbiosManuCallbackEvent, - &UpdateSmbiosManuCallbackNotifyReg - ); - return Status; - } - - return EFI_SUCCESS; + return Status; +} + + +/** + + Publish the smbios type 1. + + @param Event Event whose notification function is being invoked (gEfiDxeSmmReadyToLockProtocolGuid). + @param Context Pointer to the notification functions context, which is implementation dependent. + + @retval None + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) +{ + EFI_STATUS Status = EFI_SUCCESS; + static BOOLEAN CallbackIsInstalledManu = FALSE; + EFI_EVENT AddSmbiosManuCallbackEvent; + + + Status = AddSmbiosManuCallback (NULL, RecordData); + + if (CallbackIsInstalledManu == FALSE) { + CallbackIsInstalledManu = TRUE; // Prevent more than 1 callback. + DEBUG ((EFI_D_INFO, "Create Smbios Manu callback.\n")); + + + Status = EfiCreateEventReadyToBootEx ( + TPL_CALLBACK, + (EFI_EVENT_NOTIFY)AddSmbiosManuCallback, + RecordData, + &AddSmbiosManuCallbackEvent + ); + } + + return Status; + } diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf index b17e5b72..50bcb8be 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf @@ -2,7 +2,7 @@ # Component name for module MiscSubclass # # FIX ME! -# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
# # This program and the accompanying materials are licensed and made available under # the terms and conditions of the BSD License that accompanies this distribution. @@ -125,6 +125,7 @@ gEfiNormalSetupGuid gEfiPlatformInfoGuid gEfiVlv2VariableGuid + gEfiSetupVariableGuid [Protocols] gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED @@ -136,6 +137,8 @@ gDxePchPlatformPolicyProtocolGuid gEfiSpiProtocolGuid gEfiSimpleNetworkProtocolGuid + gEfiLoadFileProtocolGuid + gEfiDevicePathProtocolGuid [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageVariable.bin b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageVariable.bin index 2273b251..5fca3dba 100644 Binary files a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageVariable.bin and b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageVariable.bin differ diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/bld_vlv - Copy.bat b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/bld_vlv - Copy.bat index 76d9fd3f..501a1ea2 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/bld_vlv - Copy.bat +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/bld_vlv - Copy.bat @@ -39,7 +39,7 @@ cd ./edk2 if exist %CORE_PATH%\edk2.log del %CORE_PATH%\edk2.log if exist %CORE_PATH%\unitool.log del %CORE_PATH%\unitool.log if exist %CORE_PATH%\Conf\target.txt del %CORE_PATH%\Conf\target.txt -@REM if exist %CORE_PATH%\Conf\tools_def.txt del %CORE_PATH%\Conf\tools_def.txt +if exist %CORE_PATH%\Conf\tools_def.txt del %CORE_PATH%\Conf\tools_def.txt if exist %CORE_PATH%\Conf\build_rule.txt del %CORE_PATH%\Conf\build_rule.txt if exist %CORE_PATH%\Conf\FrameworkDatabase.db del %CORE_PATH%\Conf\FrameworkDatabase.db if exist conf\.cache rmdir /q/s conf\.cache diff --git a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/bld_vlv.bat b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/bld_vlv.bat index 527d0b7a..065ca994 100644 --- a/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/bld_vlv.bat +++ b/FW/PlatformBuildLab/Max/edk2-platforms/Vlv2TbltDevicePkg/bld_vlv.bat @@ -219,6 +219,7 @@ if "%TOOL_CHAIN_TAG%" == "" ( echo. goto :BldFail ) + echo Ensuring correct build directory is present for GenBiosId... set BUILD_PATH=Build\%PLATFORM_NAME%\%TARGET%_%TOOL_CHAIN_TAG% diff --git a/FW/PlatformBuildLab/Max/edk2/.gitignore b/FW/PlatformBuildLab/Max/edk2/.gitignore deleted file mode 100644 index 97f22c34..00000000 --- a/FW/PlatformBuildLab/Max/edk2/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -Build/ -tags/ -.DS_Store diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/ArmPkg.dec b/FW/PlatformBuildLab/Max/edk2/ArmPkg/ArmPkg.dec new file mode 100644 index 00000000..c4b4da2f --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/ArmPkg.dec @@ -0,0 +1,324 @@ +#/** @file +# ARM processor package. +# +# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
+# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = ArmPkg + PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[LibraryClasses.common] + ArmLib|Include/Library/ArmLib.h + ArmMmuLib|Include/Library/ArmMmuLib.h + SemihostLib|Include/Library/Semihosting.h + UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h + DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h + ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h + ArmGicArchLib|Include/Library/ArmGicArchLib.h + +[Guids.common] + gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } } + + ## ARM MPCore table + # Include/Guid/ArmMpCoreInfo.h + gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} } + +[Ppis] + ## Include/Ppi/ArmMpCoreInfo.h + gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} } + +[PcdsFeatureFlag.common] + gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001 + + # On ARM Architecture with the Security Extension, the address for the + # Vector Table can be mapped anywhere in the memory map. It means we can + # point the Exception Vector Table to its location in CpuDxe. + # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress) + gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022 + # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before + # it has been configured by the CPU DXE + gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032 + + # Define if the spin-table mechanism is used by the secondary cores when booting + # Linux (instead of PSCI) + gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033 + + # Define if the GICv3 controller should use the GICv2 legacy + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042 + +[PcdsFeatureFlag.ARM] + # Whether to map normal memory as non-shareable. FALSE is the safe choice, but + # TRUE may be appropriate to fix performance problems if you don't care about + # hardware coherency (i.e., no virtualization or cache coherent DMA) + gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043 + +[PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006 + + # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file. + # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor. + gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024 + + # This PCD will free the unallocated buffers if their size reach this threshold. + # We set the default value to 512MB. + gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003 + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004 + gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005 + + # + # ARM Secure Firmware PCDs + # + gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015 + gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016 + gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F + gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030 + + # + # ARM Hypervisor Firmware PCDs + # + gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A + gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B + gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C + gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D + + # Use ClusterId + CoreId to identify the PrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031 + # The Primary Core is ClusterId[0] & CoreId[0] + gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037 + + # + # ARM L2x0 PCDs + # + gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B + + # + # BdsLib + # + # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory + gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F + # Maximum file size for TFTP servers that do not support 'tsize' extension + gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000 + + # + # ARM Normal (or Non Secure) Firmware PCDs + # + gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C + gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E + + # + # Value to add to a host address to obtain a device address, using + # unsigned 64-bit integer arithmetic on both ARM and AArch64. This + # means we can rely on truncation on overflow to specify negative + # offsets. + # + gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044 + +[PcdsFixedAtBuild.common, PcdsPatchableInModule.common] + gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B + gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D + +[PcdsFixedAtBuild.ARM] + # + # ARM Security Extension + # + + # Secure Configuration Register + # - BIT0 : NS - Non Secure bit + # - BIT1 : IRQ Handler + # - BIT2 : FIQ Handler + # - BIT3 : EA - External Abort + # - BIT4 : FW - F bit writable + # - BIT5 : AW - A bit writable + # - BIT6 : nET - Not Early Termination + # - BIT7 : SCD - Secure Monitor Call Disable + # - BIT8 : HCE - Hyp Call enable + # - BIT9 : SIF - Secure Instruction Fetch + # 0x31 = NS | EA | FW + gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038 + + # By default we do not do a transition to non-secure mode + gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E + + # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory + gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020 + + # If the fixed FDT address is not available, then it should be loaded below the kernel. + # The recommendation from the Linux kernel is to have the FDT below 16KB. + # (see the kernel doc: Documentation/arm/Booting) + gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023 + # The FDT blob must be loaded at a 64bit aligned address. + gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026 + + # Non Secure Access Control Register + # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality + # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 + # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable + # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable + # 0xC00 = cp10 | cp11 + gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039 + +[PcdsFixedAtBuild.AARCH64] + # + # AArch64 Security Extension + # + + # Secure Configuration Register + # - BIT0 : NS - Non Secure bit + # - BIT1 : IRQ Handler + # - BIT2 : FIQ Handler + # - BIT3 : EA - External Abort + # - BIT4 : FW - F bit writable + # - BIT5 : AW - A bit writable + # - BIT6 : nET - Not Early Termination + # - BIT7 : SCD - Secure Monitor Call Disable + # - BIT8 : HCE - Hyp Call enable + # - BIT9 : SIF - Secure Instruction Fetch + # - BIT10: RW - Register width control for lower exception levels + # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer + # - BIT12: TWI - Trap WFI + # - BIT13: TWE - Trap WFE + # 0x501 = NS | HCE | RW + gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038 + + # By default we do transition to EL2 non-secure mode with Stack for EL2. + # Mode Description Bits + # NS EL2 SP2 all interrupts disabled = 0x3c9 + # NS EL1 SP1 all interrupts disabled = 0x3c5 + # Other modes include using SP0 or switching to Aarch32, but these are + # not currently supported. + gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E + # If the fixed FDT address is not available, then it should be loaded above the kernel. + # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB. + # (see the kernel doc: Documentation/arm64/booting.txt) + gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023 + # The FDT blob must be loaded at a 2MB aligned address. + gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026 + + +# +# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be +# redefined when using UEFI in a context of virtual machine. +# +[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common] + + # System Memory (DRAM): These PCDs define the region of in-built system memory + # Some platforms can get DRAM extensions, these additional regions will be declared + # to UEFI by ArmPlatformLib + gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029 + gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A + +[PcdsFixedAtBuild.common, PcdsDynamic.common] + # + # ARM Architectural Timer + # + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034 + + # ARM Architectural Timer Interrupt(GIC PPI) numbers + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035 + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036 + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040 + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041 + + # + # ARM Generic Watchdog + # + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007 + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008 + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009 + + # + # ARM Generic Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C + # Base address for the GIC Redistributor region that contains the boot CPU + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D + gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025 + + # + # Bases, sizes and translation offsets of IO and MMIO spaces, respectively. + # Note that "IO" is just another MMIO range that simulates IO space; there + # are no special instructions to access it. + # + # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are + # specific to their containing address spaces. In order to get the physical + # address for the CPU, for a given access, the respective translation value + # has to be added. + # + # The translations always have to be initialized like this, using UINT64: + # + # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space + # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space + # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space + # + # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase; + # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base; + # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base; + # + # because (a) the target address space (ie. the cpu-physical space) is + # 64-bit, and (b) the translation values are meant as offsets for *modular* + # arithmetic. + # + # Accordingly, the translation itself needs to be implemented as: + # + # UINT64 UntranslatedIoAddress; // input parameter + # UINT32 UntranslatedMmio32Address; // input parameter + # UINT64 UntranslatedMmio64Address; // input parameter + # + # UINT64 TranslatedIoAddress; // output parameter + # UINT64 TranslatedMmio32Address; // output parameter + # UINT64 TranslatedMmio64Address; // output parameter + # + # TranslatedIoAddress = UntranslatedIoAddress + + # PcdPciIoTranslation; + # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address + + # PcdPciMmio32Translation; + # TranslatedMmio64Address = UntranslatedMmio64Address + + # PcdPciMmio64Translation; + # + # The modular arithmetic performed in UINT64 ensures that the translation + # works correctly regardless of the relation between IoCpuBase and + # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and + # PcdPciMmio64Base. + # + gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050 + gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051 + gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052 + gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053 + gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054 + gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055 + gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056 + gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057 + gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058 + + # + # Inclusive range of allowed PCI buses. + # + gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059 + gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/ArmPkg.dsc b/FW/PlatformBuildLab/Max/edk2/ArmPkg/ArmPkg.dsc new file mode 100644 index 00000000..9144334c --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/ArmPkg.dsc @@ -0,0 +1,155 @@ +#/** @file +# ARM processor package. +# +# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
+# Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ArmPkg + PLATFORM_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/Arm + SUPPORTED_ARCHITECTURES = ARM|AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + +[BuildOptions] + XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 + GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -mfpu=neon + # We use A15 to get the Secure and Virtualization extensions + RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 + + RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG + *_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES + +[LibraryClasses.common] + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf + + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + +[LibraryClasses.common.PEIM] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + +[LibraryClasses.ARM, LibraryClasses.AARCH64] + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + +[Components.common] + ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf + ArmPkg/Library/BdsLib/BdsLib.inf + ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf + ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf + ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf + ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf + ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf + ArmPkg/Library/SemihostLib/SemihostLib.inf + ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf + ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf + ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf + + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf + + ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.inf + ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf + + ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf + ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf + ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + +[Components.AARCH64] + ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Contributions.txt b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Contributions.txt new file mode 100644 index 00000000..f87cbd73 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Contributions.txt @@ -0,0 +1,218 @@ + +====================== += Code Contributions = +====================== + +To make a contribution to a TianoCore project, follow these steps. +1. Create a change description in the format specified below to + use in the source control commit log. +2. Your commit message must include your "Signed-off-by" signature, + and "Contributed-under" message. +3. Your "Contributed-under" message explicitly states that the + contribution is made under the terms of the specified + contribution agreement. Your "Contributed-under" message + must include the name of contribution agreement and version. + For example: Contributed-under: TianoCore Contribution Agreement 1.0 + The "TianoCore Contribution Agreement" is included below in + this document. +4. Submit your code to the TianoCore project using the process + that the project documents on its web page. If the process is + not documented, then submit the code on development email list + for the project. +5. It is preferred that contributions are submitted using the same + copyright license as the base project. When that is not possible, + then contributions using the following licenses can be accepted: + * BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause + * BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause + * MIT: http://opensource.org/licenses/MIT + * Python-2.0: http://opensource.org/licenses/Python-2.0 + * Zlib: http://opensource.org/licenses/Zlib + + Contributions of code put into the public domain can also be + accepted. + + Contributions using other licenses might be accepted, but further + review will be required. + +===================================================== += Change Description / Commit Message / Patch Email = +===================================================== + +Your change description should use the standard format for a +commit message, and must include your "Signed-off-by" signature +and the "Contributed-under" message. + +== Sample Change Description / Commit Message = + +=== Start of sample patch email message === + +From: Contributor Name +Subject: [PATCH] CodeModule: Brief-single-line-summary + +Full-commit-message + +Contributed-under: TianoCore Contribution Agreement 1.0 +Signed-off-by: Contributor Name +--- + +An extra message for the patch email which will not be considered part +of the commit message can be added here. + +Patch content inline or attached + +=== End of sample patch email message === + +=== Notes for sample patch email === + +* The first line of commit message is taken from the email's subject + line following [PATCH]. The remaining portion of the commit message + is the email's content until the '---' line. +* git format-patch is one way to create this format + +=== Definitions for sample patch email === + +* "CodeModule" is a short idenfier for the affected code. For + example MdePkg, or MdeModulePkg UsbBusDxe. +* "Brief-single-line-summary" is a short summary of the change. +* The entire first line should be less than ~70 characters. +* "Full-commit-message" a verbose multiple line comment describing + the change. Each line should be less than ~70 characters. +* "Contributed-under" explicitely states that the contribution is + made under the terms of the contribtion agreement. This + agreement is included below in this document. +* "Signed-off-by" is the contributor's signature identifying them + by their real/legal name and their email address. + +======================================== += TianoCore Contribution Agreement 1.0 = +======================================== + +INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION, +INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE +PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE +TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE +TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR +REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE +CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS +OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED +BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS +AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE +AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT +USE THE CONTENT. + +Unless otherwise indicated, all Content made available on the TianoCore +site is provided to you under the terms and conditions of the BSD +License ("BSD"). A copy of the BSD License is available at +http://opensource.org/licenses/bsd-license.php +or when applicable, in the associated License.txt file. + +Certain other content may be made available under other licenses as +indicated in or with such Content. (For example, in a License.txt file.) + +You accept and agree to the following terms and conditions for Your +present and future Contributions submitted to TianoCore site. Except +for the license granted to Intel hereunder, You reserve all right, +title, and interest in and to Your Contributions. + +== SECTION 1: Definitions == +* "You" or "Contributor" shall mean the copyright owner or legal + entity authorized by the copyright owner that is making a + Contribution hereunder. All other entities that control, are + controlled by, or are under common control with that entity are + considered to be a single Contributor. For the purposes of this + definition, "control" means (i) the power, direct or indirect, to + cause the direction or management of such entity, whether by + contract or otherwise, or (ii) ownership of fifty percent (50%) + or more of the outstanding shares, or (iii) beneficial ownership + of such entity. +* "Contribution" shall mean any original work of authorship, + including any modifications or additions to an existing work, + that is intentionally submitted by You to the TinaoCore site for + inclusion in, or documentation of, any of the Content. For the + purposes of this definition, "submitted" means any form of + electronic, verbal, or written communication sent to the + TianoCore site or its representatives, including but not limited + to communication on electronic mailing lists, source code + control systems, and issue tracking systems that are managed by, + or on behalf of, the TianoCore site for the purpose of + discussing and improving the Content, but excluding + communication that is conspicuously marked or otherwise + designated in writing by You as "Not a Contribution." + +== SECTION 2: License for Contributions == +* Contributor hereby agrees that redistribution and use of the + Contribution in source and binary forms, with or without + modification, are permitted provided that the following + conditions are met: +** Redistributions of source code must retain the Contributor's + copyright notice, this list of conditions and the following + disclaimer. +** Redistributions in binary form must reproduce the Contributor's + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. +* Disclaimer. None of the names of Contributor, Intel, or the names + of their respective contributors may be used to endorse or + promote products derived from this software without specific + prior written permission. +* Contributor grants a license (with the right to sublicense) under + claims of Contributor's patents that Contributor can license that + are infringed by the Contribution (as delivered by Contributor) to + make, use, distribute, sell, offer for sale, and import the + Contribution and derivative works thereof solely to the minimum + extent necessary for licensee to exercise the granted copyright + license; this patent license applies solely to those portions of + the Contribution that are unmodified. No hardware per se is + licensed. +* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE + CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE + CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + DAMAGE. + +== SECTION 3: Representations == +* You represent that You are legally entitled to grant the above + license. If your employer(s) has rights to intellectual property + that You create that includes Your Contributions, You represent + that You have received permission to make Contributions on behalf + of that employer, that Your employer has waived such rights for + Your Contributions. +* You represent that each of Your Contributions is Your original + creation (see Section 4 for submissions on behalf of others). + You represent that Your Contribution submissions include complete + details of any third-party license or other restriction + (including, but not limited to, related patents and trademarks) + of which You are personally aware and which are associated with + any part of Your Contributions. + +== SECTION 4: Third Party Contributions == +* Should You wish to submit work that is not Your original creation, + You may submit it to TianoCore site separately from any + Contribution, identifying the complete details of its source + and of any license or other restriction (including, but not + limited to, related patents, trademarks, and license agreements) + of which You are personally aware, and conspicuously marking the + work as "Submitted on behalf of a third-party: [named here]". + +== SECTION 5: Miscellaneous == +* Applicable Laws. Any claims arising under or relating to this + Agreement shall be governed by the internal substantive laws of + the State of Delaware or federal courts located in Delaware, + without regard to principles of conflict of laws. +* Language. This Agreement is in the English language only, which + language shall be controlling in all respects, and all versions + of this Agreement in any other language shall be for accommodation + only and shall not be binding. All communications and notices made + or given pursuant to this Agreement, and all documentation and + support to be provided, unless otherwise noted, shall be in the + English language. + diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c new file mode 100644 index 00000000..be77b836 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c @@ -0,0 +1,141 @@ +/*++ + +Copyright (c) 2013-2014, ARM Ltd. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +--*/ + +#include "ArmGicDxe.h" + +VOID +EFIAPI +IrqInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext + ); + +VOID +EFIAPI +ExitBootServicesEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +// +// Making this global saves a few bytes in image size +// +EFI_HANDLE gHardwareInterruptHandle = NULL; + +// +// Notifications +// +EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL; + +// Maximum Number of Interrupts +UINTN mGicNumInterrupts = 0; + +HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL; + +/** + Register Handler for the specified interrupt source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + @param Handler Callback for interrupt. NULL to unregister + + @retval EFI_SUCCESS Source was updated to support Handler. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +EFI_STATUS +EFIAPI +RegisterInterruptSource ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN HARDWARE_INTERRUPT_HANDLER Handler + ) +{ + if (Source >= mGicNumInterrupts) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + + if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) { + return EFI_ALREADY_STARTED; + } + + gRegisteredInterruptHandlers[Source] = Handler; + + // If the interrupt handler is unregistered then disable the interrupt + if (NULL == Handler){ + return This->DisableInterruptSource (This, Source); + } else { + return This->EnableInterruptSource (This, Source); + } +} + +EFI_STATUS +InstallAndRegisterInterruptService ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, + IN EFI_EVENT_NOTIFY ExitBootServicesEvent + ) +{ + EFI_STATUS Status; + EFI_CPU_ARCH_PROTOCOL *Cpu; + + // Initialize the array for the Interrupt Handlers + gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts); + if (gRegisteredInterruptHandlers == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status = gBS->InstallMultipleProtocolInterfaces ( + &gHardwareInterruptHandle, + &gHardwareInterruptProtocolGuid, InterruptProtocol, + NULL + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Get the CPU protocol that this driver requires. + // + Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Unregister the default exception handler. + // + Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Register to receive interrupts + // + Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, InterruptHandler); + if (EFI_ERROR (Status)) { + return Status; + } + + // Register for an ExitBootServicesEvent + Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent); + + return Status; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.c new file mode 100644 index 00000000..2bb064f8 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.c @@ -0,0 +1,59 @@ +/*++ + +Copyright (c) 2013-2014, ARM Ltd. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +Module Name: + + ArmGicDxe.c + +Abstract: + + Driver implementing the GIC interrupt controller protocol + +--*/ + +#include + +#include "ArmGicDxe.h" + +/** + Initialize the state information for the CPU Architectural Protocol + + @param ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Protocol registered + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Hardware problems + @retval EFI_UNSUPPORTED GIC version not supported + +**/ +EFI_STATUS +InterruptDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + ARM_GIC_ARCH_REVISION Revision; + + Revision = ArmGicGetSupportedArchRevision (); + + if (Revision == ARM_GIC_ARCH_REVISION_2) { + Status = GicV2DxeInitialize (ImageHandle, SystemTable); + } else if (Revision == ARM_GIC_ARCH_REVISION_3) { + Status = GicV3DxeInitialize (ImageHandle, SystemTable); + } else { + Status = EFI_UNSUPPORTED; + } + + return Status; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.h new file mode 100644 index 00000000..af33aa90 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.h @@ -0,0 +1,67 @@ +/*++ + +Copyright (c) 2013-2014, ARM Ltd. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +--*/ + +#ifndef __ARM_GIC_DXE_H__ +#define __ARM_GIC_DXE_H__ + +#include +#include +#include +#include +#include +#include + +#include +#include + +extern UINTN mGicNumInterrupts; +extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers; + +// +// Common API +// +EFI_STATUS +InstallAndRegisterInterruptService ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, + IN EFI_EVENT_NOTIFY ExitBootServicesEvent + ); + +EFI_STATUS +EFIAPI +RegisterInterruptSource ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN HARDWARE_INTERRUPT_HANDLER Handler + ); + +// +// GicV2 API +// +EFI_STATUS +GicV2DxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +// +// GicV3 API +// +EFI_STATUS +GicV3DxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf new file mode 100644 index 00000000..e554301c --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf @@ -0,0 +1,60 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+# Copyright (c) 2012 - 2015, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmGicDxe + FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InterruptDxeInitialize + +[Sources.common] + ArmGicDxe.c + ArmGicCommonDxe.c + + GicV2/ArmGicV2Dxe.c + GicV3/ArmGicV3Dxe.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + ArmGicLib + BaseLib + UefiLib + UefiBootServicesTableLib + DebugLib + PrintLib + MemoryAllocationLib + UefiDriverEntryPoint + IoLib + PcdLib + +[Protocols] + gHardwareInterruptProtocolGuid + gEfiCpuArchProtocolGuid + +[Pcd.common] + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy + +[Depex] + gEfiCpuArchProtocolGuid diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.c new file mode 100644 index 00000000..e658e9bf --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -0,0 +1,330 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include + +/** + * + * Return whether the Source interrupt index refers to a shared interrupt (SPI) + */ +STATIC +BOOLEAN +SourceIsSpi ( + IN UINTN Source + ) +{ + return Source >= 32 && Source < 1020; +} + +/** + * Return the base address of the GIC redistributor for the current CPU + * + * @param Revision GIC Revision. The GIC redistributor might have a different + * granularity following the GIC revision. + * + * @retval Base address of the associated GIC Redistributor + */ +STATIC +UINTN +GicGetCpuRedistributorBase ( + IN UINTN GicRedistributorBase, + IN ARM_GIC_ARCH_REVISION Revision + ) +{ + UINTN Index; + UINTN MpId; + UINTN CpuAffinity; + UINTN Affinity; + UINTN GicRedistributorGranularity; + UINTN GicCpuRedistributorBase; + + MpId = ArmReadMpidr (); + // Define CPU affinity as Affinity0[0:8], Affinity1[9:15], Affinity2[16:23], Affinity3[24:32] + // whereas Affinity3 is defined at [32:39] in MPIDR + CpuAffinity = (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) | ((MpId & ARM_CORE_AFF3) >> 8); + + if (Revision == ARM_GIC_ARCH_REVISION_3) { + // 2 x 64KB frame: Redistributor control frame + SGI Control & Generation frame + GicRedistributorGranularity = ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_SGI_PPI_FRAME_SIZE; + } else { + ASSERT_EFI_ERROR (EFI_UNSUPPORTED); + return 0; + } + + GicCpuRedistributorBase = GicRedistributorBase; + + for (Index = 0; Index < PcdGet32 (PcdCoreCount); Index++) { + Affinity = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER) >> 32; + if (Affinity == CpuAffinity) { + return GicCpuRedistributorBase; + } + + // Move to the next GIC Redistributor frame + GicCpuRedistributorBase += GicRedistributorGranularity; + } + + // The Redistributor has not been found for the current CPU + ASSERT_EFI_ERROR (EFI_NOT_FOUND); + return 0; +} + +UINTN +EFIAPI +ArmGicGetInterfaceIdentification ( + IN INTN GicInterruptInterfaceBase + ) +{ + // Read the GIC Identification Register + return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR); +} + +UINTN +EFIAPI +ArmGicGetMaxNumInterrupts ( + IN INTN GicDistributorBase + ) +{ + return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1); +} + +VOID +EFIAPI +ArmGicSendSgiTo ( + IN INTN GicDistributorBase, + IN INTN TargetListFilter, + IN INTN CPUTargetList, + IN INTN SgiId + ) +{ + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId); +} + +/* + * Acknowledge and return the value of the Interrupt Acknowledge Register + * + * InterruptId is returned separately from the register value because in + * the GICv2 the register value contains the CpuId and InterruptId while + * in the GICv3 the register value is only the InterruptId. + * + * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface + * @param InterruptId InterruptId read from the Interrupt Acknowledge Register + * + * @retval value returned by the Interrupt Acknowledge Register + * + */ +UINTN +EFIAPI +ArmGicAcknowledgeInterrupt ( + IN UINTN GicInterruptInterfaceBase, + OUT UINTN *InterruptId + ) +{ + UINTN Value; + ARM_GIC_ARCH_REVISION Revision; + + Revision = ArmGicGetSupportedArchRevision (); + if (Revision == ARM_GIC_ARCH_REVISION_2) { + Value = ArmGicV2AcknowledgeInterrupt (GicInterruptInterfaceBase); + // InterruptId is required for the caller to know if a valid or spurious + // interrupt has been read + ASSERT (InterruptId != NULL); + if (InterruptId != NULL) { + *InterruptId = Value & ARM_GIC_ICCIAR_ACKINTID; + } + } else if (Revision == ARM_GIC_ARCH_REVISION_3) { + Value = ArmGicV3AcknowledgeInterrupt (); + } else { + ASSERT_EFI_ERROR (EFI_UNSUPPORTED); + // Report Spurious interrupt which is what the above controllers would + // return if no interrupt was available + Value = 1023; + } + + return Value; +} + +VOID +EFIAPI +ArmGicEndOfInterrupt ( + IN UINTN GicInterruptInterfaceBase, + IN UINTN Source + ) +{ + ARM_GIC_ARCH_REVISION Revision; + + Revision = ArmGicGetSupportedArchRevision (); + if (Revision == ARM_GIC_ARCH_REVISION_2) { + ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source); + } else if (Revision == ARM_GIC_ARCH_REVISION_3) { + ArmGicV3EndOfInterrupt (Source); + } else { + ASSERT_EFI_ERROR (EFI_UNSUPPORTED); + } +} + +VOID +EFIAPI +ArmGicEnableInterrupt ( + IN UINTN GicDistributorBase, + IN UINTN GicRedistributorBase, + IN UINTN Source + ) +{ + UINT32 RegOffset; + UINTN RegShift; + ARM_GIC_ARCH_REVISION Revision; + UINTN GicCpuRedistributorBase; + + // Calculate enable register offset and bit position + RegOffset = Source / 32; + RegShift = Source % 32; + + Revision = ArmGicGetSupportedArchRevision (); + if ((Revision == ARM_GIC_ARCH_REVISION_2) || + FeaturePcdGet (PcdArmGicV3WithV2Legacy) || + SourceIsSpi (Source)) { + // Write set-enable register + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift); + } else { + GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision); + if (GicCpuRedistributorBase == 0) { + ASSERT_EFI_ERROR (EFI_NOT_FOUND); + return; + } + + // Write set-enable register + MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * RegOffset), 1 << RegShift); + } +} + +VOID +EFIAPI +ArmGicDisableInterrupt ( + IN UINTN GicDistributorBase, + IN UINTN GicRedistributorBase, + IN UINTN Source + ) +{ + UINT32 RegOffset; + UINTN RegShift; + ARM_GIC_ARCH_REVISION Revision; + UINTN GicCpuRedistributorBase; + + // Calculate enable register offset and bit position + RegOffset = Source / 32; + RegShift = Source % 32; + + Revision = ArmGicGetSupportedArchRevision (); + if ((Revision == ARM_GIC_ARCH_REVISION_2) || + FeaturePcdGet (PcdArmGicV3WithV2Legacy) || + SourceIsSpi (Source)) { + // Write clear-enable register + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift); + } else { + GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision); + if (GicCpuRedistributorBase == 0) { + return; + } + + // Write clear-enable register + MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * RegOffset), 1 << RegShift); + } +} + +BOOLEAN +EFIAPI +ArmGicIsInterruptEnabled ( + IN UINTN GicDistributorBase, + IN UINTN GicRedistributorBase, + IN UINTN Source + ) +{ + UINT32 RegOffset; + UINTN RegShift; + ARM_GIC_ARCH_REVISION Revision; + UINTN GicCpuRedistributorBase; + UINT32 Interrupts; + + // Calculate enable register offset and bit position + RegOffset = Source / 32; + RegShift = Source % 32; + + Revision = ArmGicGetSupportedArchRevision (); + if ((Revision == ARM_GIC_ARCH_REVISION_2) || + FeaturePcdGet (PcdArmGicV3WithV2Legacy) || + SourceIsSpi (Source)) { + Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0); + } else { + GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision); + if (GicCpuRedistributorBase == 0) { + return 0; + } + + // Read set-enable register + Interrupts = MmioRead32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * RegOffset)); + } + + return ((Interrupts & (1 << RegShift)) != 0); +} + +VOID +EFIAPI +ArmGicDisableDistributor ( + IN INTN GicDistributorBase + ) +{ + // Disable Gic Distributor + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0); +} + +VOID +EFIAPI +ArmGicEnableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + ARM_GIC_ARCH_REVISION Revision; + + Revision = ArmGicGetSupportedArchRevision (); + if (Revision == ARM_GIC_ARCH_REVISION_2) { + ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase); + } else if (Revision == ARM_GIC_ARCH_REVISION_3) { + ArmGicV3EnableInterruptInterface (); + } else { + ASSERT_EFI_ERROR (EFI_UNSUPPORTED); + } +} + +VOID +EFIAPI +ArmGicDisableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + ARM_GIC_ARCH_REVISION Revision; + + Revision = ArmGicGetSupportedArchRevision (); + if (Revision == ARM_GIC_ARCH_REVISION_2) { + ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase); + } else if (Revision == ARM_GIC_ARCH_REVISION_3) { + ArmGicV3DisableInterruptInterface (); + } else { + ASSERT_EFI_ERROR (EFI_UNSUPPORTED); + } +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.inf new file mode 100644 index 00000000..047adac8 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.inf @@ -0,0 +1,51 @@ +#/* @file +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmGicLib + FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmGicLib + +[Sources] + ArmGicLib.c + ArmGicNonSecLib.c + + GicV2/ArmGicV2Lib.c + GicV2/ArmGicV2NonSecLib.c + +[Sources.ARM] + GicV3/Arm/ArmGicV3.S | GCC + GicV3/Arm/ArmGicV3.asm | RVCT + +[Sources.AARCH64] + GicV3/AArch64/ArmGicV3.S + +[LibraryClasses] + ArmLib + DebugLib + IoLib + ArmGicArchLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + +[Pcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + +[FeaturePcd] + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c new file mode 100644 index 00000000..f90391b7 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c @@ -0,0 +1,41 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include + +VOID +EFIAPI +ArmGicEnableDistributor ( + IN INTN GicDistributorBase + ) +{ + ARM_GIC_ARCH_REVISION Revision; + + /* + * Enable GIC distributor in Non-Secure world. + * Note: The ICDDCR register is banked when Security extensions are implemented + */ + Revision = ArmGicGetSupportedArchRevision (); + if (Revision == ARM_GIC_ARCH_REVISION_2) { + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1); + } else { + if (MmioRead32 (GicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_ARE) { + MmioOr32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x2); + } else { + MmioOr32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1); + } + } +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c new file mode 100644 index 00000000..d64806d2 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c @@ -0,0 +1,64 @@ +/** @file +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include + +/* + * This function configures the interrupts set by the mask to be secure. + * + */ +VOID +EFIAPI +ArmGicSetSecureInterrupts ( + IN UINTN GicDistributorBase, + IN UINTN* GicSecureInterruptMask, + IN UINTN GicSecureInterruptMaskSize + ) +{ + UINTN Index; + UINT32 InterruptStatus; + + // We must not have more interrupts defined by the mask than the number of available interrupts + ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32)); + + // Set all the interrupts defined by the mask as Secure + for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) { + InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4)); + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index])); + } +} + +VOID +EFIAPI +ArmGicEnableDistributor ( + IN INTN GicDistributorBase + ) +{ + // Turn on the GIC distributor + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1); +} + +VOID +EFIAPI +ArmGicSetupNonSecure ( + IN UINTN MpId, + IN INTN GicDistributorBase, + IN INTN GicInterruptInterfaceBase + ) +{ + ArmGicV2SetupNonSecure (MpId, GicDistributorBase, GicInterruptInterfaceBase); +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf new file mode 100644 index 00000000..fc2e1bc0 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf @@ -0,0 +1,52 @@ +#/* @file +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmGicSecLib + FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmGicLib + +[Sources] + ArmGicLib.c + ArmGicSecLib.c + + GicV2/ArmGicV2Lib.c + GicV2/ArmGicV2SecLib.c + +[Sources.ARM] + GicV3/Arm/ArmGicV3.S | GCC + GicV3/Arm/ArmGicV3.asm | RVCT + +[Sources.AARCH64] + GicV3/AArch64/ArmGicV3.S + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + ArmLib + DebugLib + IoLib + ArmGicArchLib + +[Pcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + +[FeaturePcd] + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c new file mode 100644 index 00000000..b9ecd554 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c @@ -0,0 +1,317 @@ +/*++ + +Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
+Portions copyright (c) 2010, Apple Inc. All rights reserved.
+Portions copyright (c) 2011-2016, ARM Ltd. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +Module Name: + + GicV2/ArmGicV2Dxe.c + +Abstract: + + Driver implementing the GicV2 interrupt controller protocol + +--*/ + +#include + +#include "ArmGicDxe.h" + +#define ARM_GIC_DEFAULT_PRIORITY 0x80 + +extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol; + +STATIC UINT32 mGicInterruptInterfaceBase; +STATIC UINT32 mGicDistributorBase; + +/** + Enable interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt enabled. + @retval EFI_UNSUPPORTED Source interrupt is not supported + +**/ +EFI_STATUS +EFIAPI +GicV2EnableInterruptSource ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ) +{ + if (Source >= mGicNumInterrupts) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + + ArmGicEnableInterrupt (mGicDistributorBase, 0, Source); + + return EFI_SUCCESS; +} + +/** + Disable interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt disabled. + @retval EFI_UNSUPPORTED Source interrupt is not supported + +**/ +EFI_STATUS +EFIAPI +GicV2DisableInterruptSource ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ) +{ + if (Source >= mGicNumInterrupts) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + + ArmGicDisableInterrupt (mGicDistributorBase, 0, Source); + + return EFI_SUCCESS; +} + +/** + Return current state of interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + @param InterruptState TRUE: source enabled, FALSE: source disabled. + + @retval EFI_SUCCESS InterruptState is valid + @retval EFI_UNSUPPORTED Source interrupt is not supported + +**/ +EFI_STATUS +EFIAPI +GicV2GetInterruptSourceState ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN BOOLEAN *InterruptState + ) +{ + if (Source >= mGicNumInterrupts) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + + *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, 0, Source); + + return EFI_SUCCESS; +} + +/** + Signal to the hardware that the End Of Interrupt state + has been reached. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt EOI'ed. + @retval EFI_UNSUPPORTED Source interrupt is not supported + +**/ +EFI_STATUS +EFIAPI +GicV2EndOfInterrupt ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ) +{ + if (Source >= mGicNumInterrupts) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + + ArmGicV2EndOfInterrupt (mGicInterruptInterfaceBase, Source); + return EFI_SUCCESS; +} + +/** + EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. + + @param InterruptType Defines the type of interrupt or exception that + occurred on the processor.This parameter is processor architecture specific. + @param SystemContext A pointer to the processor context when + the interrupt occurred on the processor. + + @return None + +**/ +VOID +EFIAPI +GicV2IrqInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + UINT32 GicInterrupt; + HARDWARE_INTERRUPT_HANDLER InterruptHandler; + + GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase); + + // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt). + if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) { + // The special interrupt do not need to be acknowledge + return; + } + + InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt]; + if (InterruptHandler != NULL) { + // Call the registered interrupt handler. + InterruptHandler (GicInterrupt, SystemContext); + } else { + DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt)); + GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt); + } +} + +// +// The protocol instance produced by this driver +// +EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = { + RegisterInterruptSource, + GicV2EnableInterruptSource, + GicV2DisableInterruptSource, + GicV2GetInterruptSourceState, + GicV2EndOfInterrupt +}; + +/** + Shutdown our hardware + + DXE Core will disable interrupts and turn off the timer and disable interrupts + after all the event handlers have run. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +GicV2ExitBootServicesEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINTN Index; + UINT32 GicInterrupt; + + // Disable all the interrupts + for (Index = 0; Index < mGicNumInterrupts; Index++) { + GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index); + } + + // Acknowledge all pending interrupts + do { + GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase); + + if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) < mGicNumInterrupts) { + GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt); + } + } while (!ARM_GIC_IS_SPECIAL_INTERRUPTS (GicInterrupt)); + + // Disable Gic Interface + ArmGicV2DisableInterruptInterface (mGicInterruptInterfaceBase); + + // Disable Gic Distributor + ArmGicDisableDistributor (mGicDistributorBase); +} + +/** + Initialize the state information for the CPU Architectural Protocol + + @param ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Protocol registered + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Hardware problems + +**/ +EFI_STATUS +GicV2DxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINTN Index; + UINT32 RegOffset; + UINTN RegShift; + UINT32 CpuTarget; + + // Make sure the Interrupt Controller Protocol is not already installed in the system. + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid); + + mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase); + mGicDistributorBase = PcdGet64 (PcdGicDistributorBase); + mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase); + + for (Index = 0; Index < mGicNumInterrupts; Index++) { + GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index); + + // Set Priority + RegOffset = Index / 4; + RegShift = (Index % 4) * 8; + MmioAndThenOr32 ( + mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset), + ~(0xff << RegShift), + ARM_GIC_DEFAULT_PRIORITY << RegShift + ); + } + + // + // Targets the interrupts to the Primary Cpu + // + + // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading + // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each + // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31. + // More Info in the GIC Specification about "Interrupt Processor Targets Registers" + // + // Read the first Interrupt Processor Targets Register (that corresponds to the 4 + // first SGIs) + CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR); + + // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value + // is 0 when we run on a uniprocessor platform. + if (CpuTarget != 0) { + // The 8 first Interrupt Processor Targets Registers are read-only + for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) { + MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget); + } + } + + // Set binary point reg to 0x7 (no preemption) + MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCBPR, 0x7); + + // Set priority mask reg to 0xff to allow all priorities through + MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff); + + // Enable gic cpu interface + ArmGicEnableInterruptInterface (mGicInterruptInterfaceBase); + + // Enable gic distributor + ArmGicEnableDistributor (mGicDistributorBase); + + Status = InstallAndRegisterInterruptService ( + &gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent); + + return Status; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c new file mode 100644 index 00000000..5ac1d89a --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c @@ -0,0 +1,36 @@ +/** @file +* +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include + +UINTN +EFIAPI +ArmGicV2AcknowledgeInterrupt ( + IN UINTN GicInterruptInterfaceBase + ) +{ + // Read the Interrupt Acknowledge Register + return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); +} + +VOID +EFIAPI +ArmGicV2EndOfInterrupt ( + IN UINTN GicInterruptInterfaceBase, + IN UINTN Source + ) +{ + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source); +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c new file mode 100644 index 00000000..92b764f4 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c @@ -0,0 +1,42 @@ +/** @file +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include + + +VOID +EFIAPI +ArmGicV2EnableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + /* + * Enable the CPU interface in Non-Secure world + * Note: The ICCICR register is banked when Security extensions are implemented + */ + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1); +} + +VOID +EFIAPI +ArmGicV2DisableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + // Disable Gic Interface + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0); + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0); +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c new file mode 100644 index 00000000..ac1e0e49 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c @@ -0,0 +1,100 @@ +/** @file +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include + +/* + * This function configures the all interrupts to be Non-secure. + * + */ +VOID +EFIAPI +ArmGicV2SetupNonSecure ( + IN UINTN MpId, + IN INTN GicDistributorBase, + IN INTN GicInterruptInterfaceBase + ) +{ + UINTN InterruptId; + UINTN CachedPriorityMask; + UINTN Index; + UINTN MaxInterrupts; + + CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR); + + // Set priority Mask so that no interrupts get through to CPU + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0); + + InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); + MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase); + + // Only try to clear valid interrupts. Ignore spurious interrupts. + while ((InterruptId & 0x3FF) < MaxInterrupts) { + // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal + ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId); + + // Next + InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); + } + + // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt). + if (ArmPlatformIsPrimaryCore (MpId)) { + // Ensure all GIC interrupts are Non-Secure + for (Index = 0; Index < (MaxInterrupts / 32); Index++) { + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff); + } + } else { + // The secondary cores only set the Non Secure bit to their banked PPIs + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); + } + + // Ensure all interrupts can get through the priority mask + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask); +} + +VOID +EFIAPI +ArmGicV2EnableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + // Set Priority Mask to allow interrupts + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); + + // Enable CPU interface in Secure world + // Enable CPU interface in Non-secure World + // Signal Secure Interrupts to CPU using FIQ line * + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, + ARM_GIC_ICCICR_ENABLE_SECURE | + ARM_GIC_ICCICR_ENABLE_NS | + ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ); +} + +VOID +EFIAPI +ArmGicV2DisableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + UINT32 ControlValue; + + // Disable CPU interface in Secure world and Non-secure World + ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR); + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS)); +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S new file mode 100644 index 00000000..a4e0a417 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S @@ -0,0 +1,112 @@ +# +# Copyright (c) 2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +#include + +#if !defined(__clang__) + +// +// Clang versions before v3.6 do not support the GNU extension that allows +// system registers outside of the IMPLEMENTATION DEFINED range to be specified +// using the generic notation below. However, clang knows these registers by +// their architectural names, so it has no need for these aliases anyway. +// +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_EOIR1_EL1 S3_0_C12_C12_1 +#define ICC_IAR1_EL1 S3_0_C12_C12_0 +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_BPR1_EL1 S3_0_C12_C12_3 + +#endif + +//UINT32 +//EFIAPI +//ArmGicV3GetControlSystemRegisterEnable ( +// VOID +// ); +ASM_FUNC(ArmGicV3GetControlSystemRegisterEnable) + EL1_OR_EL2_OR_EL3(x1) +1: mrs x0, ICC_SRE_EL1 + b 4f +2: mrs x0, ICC_SRE_EL2 + b 4f +3: mrs x0, ICC_SRE_EL3 +4: ret + +//VOID +//EFIAPI +//ArmGicV3SetControlSystemRegisterEnable ( +// IN UINT32 ControlSystemRegisterEnable +// ); +ASM_FUNC(ArmGicV3SetControlSystemRegisterEnable) + EL1_OR_EL2_OR_EL3(x1) +1: msr ICC_SRE_EL1, x0 + b 4f +2: msr ICC_SRE_EL2, x0 + b 4f +3: msr ICC_SRE_EL3, x0 +4: isb + ret + +//VOID +//ArmGicV3EnableInterruptInterface ( +// VOID +// ); +ASM_FUNC(ArmGicV3EnableInterruptInterface) + mov x0, #1 + msr ICC_IGRPEN1_EL1, x0 + ret + +//VOID +//ArmGicV3DisableInterruptInterface ( +// VOID +// ); +ASM_FUNC(ArmGicV3DisableInterruptInterface) + mov x0, #0 + msr ICC_IGRPEN1_EL1, x0 + ret + +//VOID +//ArmGicV3EndOfInterrupt ( +// IN UINTN InterruptId +// ); +ASM_FUNC(ArmGicV3EndOfInterrupt) + msr ICC_EOIR1_EL1, x0 + ret + +//UINTN +//ArmGicV3AcknowledgeInterrupt ( +// VOID +// ); +ASM_FUNC(ArmGicV3AcknowledgeInterrupt) + mrs x0, ICC_IAR1_EL1 + ret + +//VOID +//ArmGicV3SetPriorityMask ( +// IN UINTN Priority +// ); +ASM_FUNC(ArmGicV3SetPriorityMask) + msr ICC_PMR_EL1, x0 + ret + +//VOID +//ArmGicV3SetBinaryPointer ( +// IN UINTN BinaryPoint +// ); +ASM_FUNC(ArmGicV3SetBinaryPointer) + msr ICC_BPR1_EL1, x0 + ret diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S new file mode 100644 index 00000000..a72f3c86 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S @@ -0,0 +1,86 @@ +# +# Copyright (c) 2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +#include +#include + +// For the moment we assume this will run in SVC mode on ARMv7 + +//UINT32 +//EFIAPI +//ArmGicGetControlSystemRegisterEnable ( +// VOID +// ); +ASM_FUNC(ArmGicV3GetControlSystemRegisterEnable) + mrc p15, 0, r0, c12, c12, 5 // ICC_SRE + bx lr + +//VOID +//EFIAPI +//ArmGicSetControlSystemRegisterEnable ( +// IN UINT32 ControlSystemRegisterEnable +// ); +ASM_FUNC(ArmGicV3SetControlSystemRegisterEnable) + mcr p15, 0, r0, c12, c12, 5 // ICC_SRE + isb + bx lr + +//VOID +//ArmGicV3EnableInterruptInterface ( +// VOID +// ); +ASM_FUNC(ArmGicV3EnableInterruptInterface) + mov r0, #1 + mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1 + bx lr + +//VOID +//ArmGicV3DisableInterruptInterface ( +// VOID +// ); +ASM_FUNC(ArmGicV3DisableInterruptInterface) + mov r0, #0 + mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1 + bx lr + +//VOID +//ArmGicV3EndOfInterrupt ( +// IN UINTN InterruptId +// ); +ASM_FUNC(ArmGicV3EndOfInterrupt) + mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1 + bx lr + +//UINTN +//ArmGicV3AcknowledgeInterrupt ( +// VOID +// ); +ASM_FUNC(ArmGicV3AcknowledgeInterrupt) + mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1 + bx lr + +//VOID +//ArmGicV3SetPriorityMask ( +// IN UINTN Priority +// ); +ASM_FUNC(ArmGicV3SetPriorityMask) + mcr p15, 0, r0, c4, c6, 0 //ICC_PMR + bx lr + +//VOID +//ArmGicV3SetBinaryPointer ( +// IN UINTN BinaryPoint +// ); +ASM_FUNC(ArmGicV3SetBinaryPointer) + mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1 + bx lr diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm new file mode 100644 index 00000000..4228fb59 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm @@ -0,0 +1,88 @@ +// +// Copyright (c) 2014, ARM Limited. All rights reserved. +// +// This program and the accompanying materials are licensed and made available +// under the terms and conditions of the BSD License which accompanies this +// distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +// For the moment we assume this will run in SVC mode on ARMv7 + + + INCLUDE AsmMacroExport.inc + +//UINT32 +//EFIAPI +//ArmGicGetControlSystemRegisterEnable ( +// VOID +// ); + RVCT_ASM_EXPORT ArmGicV3GetControlSystemRegisterEnable + mrc p15, 0, r0, c12, c12, 5 // ICC_SRE + bx lr + +//VOID +//EFIAPI +//ArmGicSetControlSystemRegisterEnable ( +// IN UINT32 ControlSystemRegisterEnable +// ); + RVCT_ASM_EXPORT ArmGicV3SetControlSystemRegisterEnable + mcr p15, 0, r0, c12, c12, 5 // ICC_SRE + isb + bx lr + +//VOID +//ArmGicV3EnableInterruptInterface ( +// VOID +// ); + RVCT_ASM_EXPORT ArmGicV3EnableInterruptInterface + mov r0, #1 + mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1 + bx lr + +//VOID +//ArmGicV3DisableInterruptInterface ( +// VOID +// ); + RVCT_ASM_EXPORT ArmGicV3DisableInterruptInterface + mov r0, #0 + mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1 + bx lr + +//VOID +//ArmGicV3EndOfInterrupt ( +// IN UINTN InterruptId +// ); + RVCT_ASM_EXPORT ArmGicV3EndOfInterrupt + mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1 + bx lr + +//UINTN +//ArmGicV3AcknowledgeInterrupt ( +// VOID +// ); + RVCT_ASM_EXPORT ArmGicV3AcknowledgeInterrupt + mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1 + bx lr + +//VOID +//ArmGicV3SetPriorityMask ( +// IN UINTN Priority +// ); + RVCT_ASM_EXPORT ArmGicV3SetPriorityMask + mcr p15, 0, r0, c4, c6, 0 //ICC_PMR + bx lr + +//VOID +//ArmGicV3SetBinaryPointer ( +// IN UINTN BinaryPoint +// ); + RVCT_ASM_EXPORT ArmGicV3SetBinaryPointer + mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1 + bx lr + + END diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c new file mode 100644 index 00000000..8af97a93 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -0,0 +1,337 @@ +/** @file +* +* Copyright (c) 2011-2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include "ArmGicDxe.h" + +#define ARM_GIC_DEFAULT_PRIORITY 0x80 + +extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol; + +STATIC UINTN mGicDistributorBase; +STATIC UINTN mGicRedistributorsBase; + +/** + Enable interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt enabled. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +EFI_STATUS +EFIAPI +GicV3EnableInterruptSource ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ) +{ + if (Source >= mGicNumInterrupts) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + + ArmGicEnableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source); + + return EFI_SUCCESS; +} + +/** + Disable interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt disabled. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +EFI_STATUS +EFIAPI +GicV3DisableInterruptSource ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ) +{ + if (Source >= mGicNumInterrupts) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + + ArmGicDisableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source); + + return EFI_SUCCESS; +} + +/** + Return current state of interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + @param InterruptState TRUE: source enabled, FALSE: source disabled. + + @retval EFI_SUCCESS InterruptState is valid + @retval EFI_DEVICE_ERROR InterruptState is not valid + +**/ +EFI_STATUS +EFIAPI +GicV3GetInterruptSourceState ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN BOOLEAN *InterruptState + ) +{ + if (Source >= mGicNumInterrupts) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + + *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, mGicRedistributorsBase, Source); + + return EFI_SUCCESS; +} + +/** + Signal to the hardware that the End Of Interrupt state + has been reached. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt EOI'ed. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +EFI_STATUS +EFIAPI +GicV3EndOfInterrupt ( + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ) +{ + if (Source >= mGicNumInterrupts) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + + ArmGicV3EndOfInterrupt (Source); + return EFI_SUCCESS; +} + +/** + EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. + + @param InterruptType Defines the type of interrupt or exception that + occurred on the processor.This parameter is processor architecture specific. + @param SystemContext A pointer to the processor context when + the interrupt occurred on the processor. + + @return None + +**/ +VOID +EFIAPI +GicV3IrqInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + UINT32 GicInterrupt; + HARDWARE_INTERRUPT_HANDLER InterruptHandler; + + GicInterrupt = ArmGicV3AcknowledgeInterrupt (); + + // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the + // number of interrupt (ie: Spurious interrupt). + if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) { + // The special interrupt do not need to be acknowledge + return; + } + + InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt]; + if (InterruptHandler != NULL) { + // Call the registered interrupt handler. + InterruptHandler (GicInterrupt, SystemContext); + } else { + DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt)); + GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, GicInterrupt); + } +} + +// +// The protocol instance produced by this driver +// +EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = { + RegisterInterruptSource, + GicV3EnableInterruptSource, + GicV3DisableInterruptSource, + GicV3GetInterruptSourceState, + GicV3EndOfInterrupt +}; + +/** + Shutdown our hardware + + DXE Core will disable interrupts and turn off the timer and disable interrupts + after all the event handlers have run. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +GicV3ExitBootServicesEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINTN Index; + + // Acknowledge all pending interrupts + for (Index = 0; Index < mGicNumInterrupts; Index++) { + GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index); + } + + for (Index = 0; Index < mGicNumInterrupts; Index++) { + GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, Index); + } + + // Disable Gic Interface + ArmGicV3DisableInterruptInterface (); + + // Disable Gic Distributor + ArmGicDisableDistributor (mGicDistributorBase); +} + +/** + Initialize the state information for the CPU Architectural Protocol + + @param ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Protocol registered + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Hardware problems + +**/ +EFI_STATUS +GicV3DxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINTN Index; + UINT32 RegOffset; + UINTN RegShift; + UINT64 CpuTarget; + UINT64 MpId; + + // Make sure the Interrupt Controller Protocol is not already installed in the system. + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid); + + mGicDistributorBase = PcdGet64 (PcdGicDistributorBase); + mGicRedistributorsBase = PcdGet64 (PcdGicRedistributorsBase); + mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase); + + // + // We will be driving this GIC in native v3 mode, i.e., with Affinity + // Routing enabled. So ensure that the ARE bit is set. + // + if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { + MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE); + } + + for (Index = 0; Index < mGicNumInterrupts; Index++) { + GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index); + + // Set Priority + RegOffset = Index / 4; + RegShift = (Index % 4) * 8; + MmioAndThenOr32 ( + mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset), + ~(0xff << RegShift), + ARM_GIC_DEFAULT_PRIORITY << RegShift + ); + } + + // + // Targets the interrupts to the Primary Cpu + // + + if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { + // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading + // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each + // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31. + // More Info in the GIC Specification about "Interrupt Processor Targets Registers" + // + // Read the first Interrupt Processor Targets Register (that corresponds to the 4 + // first SGIs) + CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR); + + // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value + // is 0 when we run on a uniprocessor platform. + if (CpuTarget != 0) { + // The 8 first Interrupt Processor Targets Registers are read-only + for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) { + MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget); + } + } + } else { + MpId = ArmReadMpidr (); + CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3); + + if ((MmioRead32 (mGicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_DS) != 0) { + // + // If the Disable Security (DS) control bit is set, we are dealing with a + // GIC that has only one security state. In this case, let's assume we are + // executing in non-secure state (which is appropriate for DXE modules) + // and that no other firmware has performed any configuration on the GIC. + // This means we need to reconfigure all interrupts to non-secure Group 1 + // first. + // + MmioWrite32 (mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR, 0xffffffff); + + for (Index = 32; Index < mGicNumInterrupts; Index += 32) { + MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDISR + Index / 8, 0xffffffff); + } + } + + // Route the SPIs to the primary CPU. SPIs start at the INTID 32 + for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { + MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget | ARM_GICD_IROUTER_IRM); + } + } + + // Set binary point reg to 0x7 (no preemption) + ArmGicV3SetBinaryPointer (0x7); + + // Set priority mask reg to 0xff to allow all priorities through + ArmGicV3SetPriorityMask (0xff); + + // Enable gic cpu interface + ArmGicV3EnableInterruptInterface (); + + // Enable gic distributor + ArmGicEnableDistributor (mGicDistributorBase); + + Status = InstallAndRegisterInterruptService ( + &gHardwareInterruptV3Protocol, GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent); + + return Status; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c new file mode 100644 index 00000000..fecf6a87 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c @@ -0,0 +1,559 @@ +/** @file + Produces the CPU I/O 2 Protocol. + +Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2016, Linaro Ltd. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include + +#include +#include +#include +#include +#include + +#define MAX_IO_PORT_ADDRESS 0xFFFF + +// +// Handle for the CPU I/O 2 Protocol +// +STATIC EFI_HANDLE mHandle = NULL; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mInStride[] = { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 0, // EfiCpuIoWidthFifoUint8 + 0, // EfiCpuIoWidthFifoUint16 + 0, // EfiCpuIoWidthFifoUint32 + 0, // EfiCpuIoWidthFifoUint64 + 1, // EfiCpuIoWidthFillUint8 + 2, // EfiCpuIoWidthFillUint16 + 4, // EfiCpuIoWidthFillUint32 + 8 // EfiCpuIoWidthFillUint64 +}; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mOutStride[] = { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 1, // EfiCpuIoWidthFifoUint8 + 2, // EfiCpuIoWidthFifoUint16 + 4, // EfiCpuIoWidthFifoUint32 + 8, // EfiCpuIoWidthFifoUint64 + 0, // EfiCpuIoWidthFillUint8 + 0, // EfiCpuIoWidthFillUint16 + 0, // EfiCpuIoWidthFillUint32 + 0 // EfiCpuIoWidthFillUint64 +}; + +/** + Check parameters to a CPU I/O 2 Protocol service request. + + The I/O operations are carried out exactly as requested. The caller is responsible + for satisfying any alignment and I/O width restrictions that a PI System on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will + be handled by the driver. + + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number of + bytes moved is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to store the results. + For write operations, the source buffer from which to write data. + + @retval EFI_SUCCESS The parameters for this request pass the checks. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. + @retval EFI_UNSUPPORTED The address range specified by Address, Width, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +CpuIoCheckParameter ( + IN BOOLEAN MmioOperation, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT64 MaxCount; + UINT64 Limit; + + // + // Check to see if Buffer is NULL + // + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Width is in the valid range + // + if ((UINT32)Width >= EfiCpuIoWidthMaximum) { + return EFI_INVALID_PARAMETER; + } + + // + // For FIFO type, the target address won't increase during the access, + // so treat Count as 1 + // + if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) { + Count = 1; + } + + // + // Check to see if Width is in the valid range for I/O Port operations + // + Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) { + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Address is aligned + // + if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) { + return EFI_UNSUPPORTED; + } + + // + // Check to see if any address associated with this transfer exceeds the maximum + // allowed address. The maximum address implied by the parameters passed in is + // Address + Size * Count. If the following condition is met, then the transfer + // is not supported. + // + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1 + // + // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count + // can also be the maximum integer value supported by the CPU, this range + // check must be adjusted to avoid all oveflow conditions. + // + // The following form of the range check is equivalent but assumes that + // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1). + // + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); + if (Count == 0) { + if (Address > Limit) { + return EFI_UNSUPPORTED; + } + } else { + MaxCount = RShiftU64 (Limit, Width); + if (MaxCount < (Count - 1)) { + return EFI_UNSUPPORTED; + } + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { + return EFI_UNSUPPORTED; + } + } + + // + // Check to see if Buffer is aligned + // + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) { + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** + Reads memory-mapped registers. + + The I/O operations are carried out exactly as requested. The caller is responsible + for satisfying any alignment and I/O width restrictions that a PI System on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read or + write operation is performed Count times from the first element of Buffer. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number of + bytes moved is Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. + For write operations, the source buffer from which to write data. + + @retval EFI_SUCCESS The data was read from or written to the PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. + @retval EFI_UNSUPPORTED The address range specified by Address, Width, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuMemoryServiceRead ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Select loop based on the width of the transfer + // + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { + if (OperationWidth == EfiCpuIoWidthUint8) { + *Uint8Buffer = MmioRead8 ((UINTN)Address); + } else if (OperationWidth == EfiCpuIoWidthUint16) { + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address); + } else if (OperationWidth == EfiCpuIoWidthUint32) { + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address); + } else if (OperationWidth == EfiCpuIoWidthUint64) { + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address); + } + } + return EFI_SUCCESS; +} + +/** + Writes memory-mapped registers. + + The I/O operations are carried out exactly as requested. The caller is responsible + for satisfying any alignment and I/O width restrictions that a PI System on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read or + write operation is performed Count times from the first element of Buffer. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number of + bytes moved is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to store the results. + For write operations, the source buffer from which to write data. + + @retval EFI_SUCCESS The data was read from or written to the PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. + @retval EFI_UNSUPPORTED The address range specified by Address, Width, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuMemoryServiceWrite ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Select loop based on the width of the transfer + // + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { + if (OperationWidth == EfiCpuIoWidthUint8) { + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + } else if (OperationWidth == EfiCpuIoWidthUint16) { + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + } else if (OperationWidth == EfiCpuIoWidthUint32) { + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + } else if (OperationWidth == EfiCpuIoWidthUint64) { + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); + } + } + return EFI_SUCCESS; +} + +/** + Reads I/O registers. + + The I/O operations are carried out exactly as requested. The caller is responsible + for satisfying any alignment and I/O width restrictions that a PI System on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read or + write operation is performed Count times from the first element of Buffer. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number of + bytes moved is Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. + For write operations, the source buffer from which to write data. + + @retval EFI_SUCCESS The data was read from or written to the PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. + @retval EFI_UNSUPPORTED The address range specified by Address, Width, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuIoServiceRead ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + Address += PcdGet64 (PcdPciIoTranslation); + + // + // Select loop based on the width of the transfer + // + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { + if (OperationWidth == EfiCpuIoWidthUint8) { + *Uint8Buffer = MmioRead8 ((UINTN)Address); + } else if (OperationWidth == EfiCpuIoWidthUint16) { + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address); + } else if (OperationWidth == EfiCpuIoWidthUint32) { + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address); + } + } + + return EFI_SUCCESS; +} + +/** + Write I/O registers. + + The I/O operations are carried out exactly as requested. The caller is responsible + for satisfying any alignment and I/O width restrictions that a PI System on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read or + write operation is performed Count times from the first element of Buffer. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number of + bytes moved is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to store the results. + For write operations, the source buffer from which to write data. + + @retval EFI_SUCCESS The data was read from or written to the PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. + @retval EFI_UNSUPPORTED The address range specified by Address, Width, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuIoServiceWrite ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + // + // Make sure the parameters are valid + // + Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + Address += PcdGet64 (PcdPciIoTranslation); + + // + // Select loop based on the width of the transfer + // + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + + for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { + if (OperationWidth == EfiCpuIoWidthUint8) { + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + } else if (OperationWidth == EfiCpuIoWidthUint16) { + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + } else if (OperationWidth == EfiCpuIoWidthUint32) { + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + } + } + + return EFI_SUCCESS; +} + +// +// CPU I/O 2 Protocol instance +// +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = { + { + CpuMemoryServiceRead, + CpuMemoryServiceWrite + }, + { + CpuIoServiceRead, + CpuIoServiceWrite + } +}; + + +/** + The user Entry Point for module CpuIo2Dxe. The user code starts with this function. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry point. + +**/ +EFI_STATUS +EFIAPI +ArmPciCpuIo2Initialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid); + Status = gBS->InstallMultipleProtocolInterfaces ( + &mHandle, + &gEfiCpuIo2ProtocolGuid, &mCpuIo2, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf new file mode 100644 index 00000000..f7eab9d0 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf @@ -0,0 +1,53 @@ +## @file +# Produces the CPU I/O 2 Protocol by using the services of the I/O Library. +# +# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmPciCpuIo2Dxe + FILE_GUID = 168D1A6E-F4A5-448A-9E95-795661BB3067 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = ArmPciCpuIo2Initialize + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = ARM AARCH64 +# + +[Sources] + ArmPciCpuIo2Dxe.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + BaseLib + DebugLib + IoLib + PcdLib + UefiBootServicesTableLib + +[Pcd] + gArmTokenSpaceGuid.PcdPciIoTranslation + +[Protocols] + gEfiCpuIo2ProtocolGuid ## PRODUCES + +[Depex] + TRUE diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c new file mode 100644 index 00000000..3e216c7c --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -0,0 +1,347 @@ +/*++ + +Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
+Portions copyright (c) 2010, Apple Inc. All rights reserved.
+Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + +#include +#include "CpuDxe.h" + +#define TT_ATTR_INDX_INVALID ((UINT32)~0) + +STATIC +UINT64 +GetFirstPageAttribute ( + IN UINT64 *FirstLevelTableAddress, + IN UINTN TableLevel + ) +{ + UINT64 FirstEntry; + + // Get the first entry of the table + FirstEntry = *FirstLevelTableAddress; + + if ((TableLevel != 3) && (FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) { + // Only valid for Levels 0, 1 and 2 + + // Get the attribute of the subsequent table + return GetFirstPageAttribute ((UINT64*)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1); + } else if (((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) || + ((TableLevel == 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3))) + { + return FirstEntry & TT_ATTR_INDX_MASK; + } else { + return TT_ATTR_INDX_INVALID; + } +} + +STATIC +UINT64 +GetNextEntryAttribute ( + IN UINT64 *TableAddress, + IN UINTN EntryCount, + IN UINTN TableLevel, + IN UINT64 BaseAddress, + IN OUT UINT32 *PrevEntryAttribute, + IN OUT UINT64 *StartGcdRegion + ) +{ + UINTN Index; + UINT64 Entry; + UINT32 EntryAttribute; + UINT32 EntryType; + EFI_STATUS Status; + UINTN NumberOfDescriptors; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; + + // Get the memory space map from GCD + MemorySpaceMap = NULL; + Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); + ASSERT_EFI_ERROR (Status); + + // We cannot get more than 3-level page table + ASSERT (TableLevel <= 3); + + // While the top level table might not contain TT_ENTRY_COUNT entries; + // the subsequent ones should be filled up + for (Index = 0; Index < EntryCount; Index++) { + Entry = TableAddress[Index]; + EntryType = Entry & TT_TYPE_MASK; + EntryAttribute = Entry & TT_ATTR_INDX_MASK; + + // If Entry is a Table Descriptor type entry then go through the sub-level table + if ((EntryType == TT_TYPE_BLOCK_ENTRY) || + ((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3))) { + if ((*PrevEntryAttribute == TT_ATTR_INDX_INVALID) || (EntryAttribute != *PrevEntryAttribute)) { + if (*PrevEntryAttribute != TT_ATTR_INDX_INVALID) { + // Update GCD with the last region + SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, + *StartGcdRegion, + (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion, + PageAttributeToGcdAttribute (*PrevEntryAttribute)); + } + + // Start of the new region + *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel)); + *PrevEntryAttribute = EntryAttribute; + } else { + continue; + } + } else if (EntryType == TT_TYPE_TABLE_ENTRY) { + // Table Entry type is only valid for Level 0, 1, 2 + ASSERT (TableLevel < 3); + + // Increase the level number and scan the sub-level table + GetNextEntryAttribute ((UINT64*)(Entry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), + TT_ENTRY_COUNT, TableLevel + 1, + (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))), + PrevEntryAttribute, StartGcdRegion); + } else { + if (*PrevEntryAttribute != TT_ATTR_INDX_INVALID) { + // Update GCD with the last region + SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, + *StartGcdRegion, + (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion, + PageAttributeToGcdAttribute (*PrevEntryAttribute)); + + // Start of the new region + *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel)); + *PrevEntryAttribute = TT_ATTR_INDX_INVALID; + } + } + } + + FreePool (MemorySpaceMap); + + return BaseAddress + (EntryCount * TT_ADDRESS_AT_LEVEL(TableLevel)); +} + +EFI_STATUS +SyncCacheConfig ( + IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol + ) +{ + EFI_STATUS Status; + UINT32 PageAttribute = 0; + UINT64 *FirstLevelTableAddress; + UINTN TableLevel; + UINTN TableCount; + UINTN NumberOfDescriptors; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; + UINTN Tcr; + UINTN T0SZ; + UINT64 BaseAddressGcdRegion; + UINT64 EndAddressGcdRegion; + + // This code assumes MMU is enabled and filed with section translations + ASSERT (ArmMmuEnabled ()); + + // + // Get the memory space map from GCD + // + MemorySpaceMap = NULL; + Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); + ASSERT_EFI_ERROR (Status); + + // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs + // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a + // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were + // a client) to update its copy of the attributes. This is bad architecture and should be replaced + // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead. + + // Obtain page table base + FirstLevelTableAddress = (UINT64*)(ArmGetTTBR0BaseAddress ()); + + // Get Translation Control Register value + Tcr = ArmGetTCR (); + // Get Address Region Size + T0SZ = Tcr & TCR_T0SZ_MASK; + + // Get the level of the first table for the indicated Address Region Size + GetRootTranslationTableInfo (T0SZ, &TableLevel, &TableCount); + + // First Attribute of the Page Tables + PageAttribute = GetFirstPageAttribute (FirstLevelTableAddress, TableLevel); + + // We scan from the start of the memory map (ie: at the address 0x0) + BaseAddressGcdRegion = 0x0; + EndAddressGcdRegion = GetNextEntryAttribute (FirstLevelTableAddress, + TableCount, TableLevel, + BaseAddressGcdRegion, + &PageAttribute, &BaseAddressGcdRegion); + + // Update GCD with the last region if valid + if (PageAttribute != TT_ATTR_INDX_INVALID) { + SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, + BaseAddressGcdRegion, + EndAddressGcdRegion - BaseAddressGcdRegion, + PageAttributeToGcdAttribute (PageAttribute)); + } + + FreePool (MemorySpaceMap); + + return EFI_SUCCESS; +} + +UINT64 +EfiAttributeToArmAttribute ( + IN UINT64 EfiAttributes + ) +{ + UINT64 ArmAttributes; + + switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) { + case EFI_MEMORY_UC: + if (ArmReadCurrentEL () == AARCH64_EL2) { + ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK; + } else { + ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK; + } + break; + case EFI_MEMORY_WC: + ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE; + break; + case EFI_MEMORY_WT: + ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; + break; + case EFI_MEMORY_WB: + ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; + break; + default: + ArmAttributes = TT_ATTR_INDX_MASK; + } + + // Set the access flag to match the block attributes + ArmAttributes |= TT_AF; + + // Determine protection attributes + if (EfiAttributes & EFI_MEMORY_RO) { + ArmAttributes |= TT_AP_RO_RO; + } + + // Process eXecute Never attribute + if (EfiAttributes & EFI_MEMORY_XP) { + ArmAttributes |= TT_PXN_MASK; + } + + return ArmAttributes; +} + +// This function will recursively go down the page table to find the first block address linked to 'BaseAddress'. +// And then the function will identify the size of the region that has the same page table attribute. +EFI_STATUS +GetMemoryRegionRec ( + IN UINT64 *TranslationTable, + IN UINTN TableLevel, + IN UINT64 *LastBlockEntry, + IN OUT UINTN *BaseAddress, + OUT UINTN *RegionLength, + OUT UINTN *RegionAttributes + ) +{ + EFI_STATUS Status; + UINT64 *NextTranslationTable; + UINT64 *BlockEntry; + UINT64 BlockEntryType; + UINT64 EntryType; + + if (TableLevel != 3) { + BlockEntryType = TT_TYPE_BLOCK_ENTRY; + } else { + BlockEntryType = TT_TYPE_BLOCK_ENTRY_LEVEL3; + } + + // Find the block entry linked to the Base Address + BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress); + EntryType = *BlockEntry & TT_TYPE_MASK; + + if ((TableLevel < 3) && (EntryType == TT_TYPE_TABLE_ENTRY)) { + NextTranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE); + + // The entry is a page table, so we go to the next level + Status = GetMemoryRegionRec ( + NextTranslationTable, // Address of the next level page table + TableLevel + 1, // Next Page Table level + (UINTN*)TT_LAST_BLOCK_ADDRESS(NextTranslationTable, TT_ENTRY_COUNT), + BaseAddress, RegionLength, RegionAttributes); + + // In case of 'Success', it means the end of the block region has been found into the upper + // level translation table + if (!EFI_ERROR(Status)) { + return EFI_SUCCESS; + } + + // Now we processed the table move to the next entry + BlockEntry++; + } else if (EntryType == BlockEntryType) { + // We have found the BlockEntry attached to the address. We save its start address (the start + // address might be before the 'BaseAdress') and attributes + *BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL(TableLevel) - 1); + *RegionLength = 0; + *RegionAttributes = *BlockEntry & TT_ATTRIBUTES_MASK; + } else { + // We have an 'Invalid' entry + return EFI_UNSUPPORTED; + } + + while (BlockEntry <= LastBlockEntry) { + if ((*BlockEntry & TT_ATTRIBUTES_MASK) == *RegionAttributes) { + *RegionLength = *RegionLength + TT_BLOCK_ENTRY_SIZE_AT_LEVEL(TableLevel); + } else { + // In case we have found the end of the region we return success + return EFI_SUCCESS; + } + BlockEntry++; + } + + // If we have reached the end of the TranslationTable and we have not found the end of the region then + // we return EFI_NOT_FOUND. + // The caller will continue to look for the memory region at its level + return EFI_NOT_FOUND; +} + +EFI_STATUS +GetMemoryRegion ( + IN OUT UINTN *BaseAddress, + OUT UINTN *RegionLength, + OUT UINTN *RegionAttributes + ) +{ + EFI_STATUS Status; + UINT64 *TranslationTable; + UINTN TableLevel; + UINTN EntryCount; + UINTN T0SZ; + + ASSERT ((BaseAddress != NULL) && (RegionLength != NULL) && (RegionAttributes != NULL)); + + TranslationTable = ArmGetTTBR0BaseAddress (); + + T0SZ = ArmGetTCR () & TCR_T0SZ_MASK; + // Get the Table info from T0SZ + GetRootTranslationTableInfo (T0SZ, &TableLevel, &EntryCount); + + Status = GetMemoryRegionRec (TranslationTable, TableLevel, + (UINTN*)TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount), + BaseAddress, RegionLength, RegionAttributes); + + // If the region continues up to the end of the root table then GetMemoryRegionRec() + // will return EFI_NOT_FOUND + if (Status == EFI_NOT_FOUND) { + return EFI_SUCCESS; + } else { + return Status; + } +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c new file mode 100644 index 00000000..12ca5b26 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -0,0 +1,514 @@ +/*++ + +Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
+Portions copyright (c) 2010, Apple Inc. All rights reserved.
+Portions copyright (c) 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + +#include +#include "CpuDxe.h" + +EFI_STATUS +SectionToGcdAttributes ( + IN UINT32 SectionAttributes, + OUT UINT64 *GcdAttributes + ) +{ + *GcdAttributes = 0; + + // determine cacheability attributes + switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) { + case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED: + *GcdAttributes |= EFI_MEMORY_UC; + break; + case TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE: + *GcdAttributes |= EFI_MEMORY_UC; + break; + case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC: + *GcdAttributes |= EFI_MEMORY_WT; + break; + case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC: + *GcdAttributes |= EFI_MEMORY_WB; + break; + case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE: + *GcdAttributes |= EFI_MEMORY_WC; + break; + case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC: + *GcdAttributes |= EFI_MEMORY_WB; + break; + case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE: + *GcdAttributes |= EFI_MEMORY_UC; + break; + default: + return EFI_UNSUPPORTED; + } + + // determine protection attributes + switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) { + case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write + //*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP; + break; + + case TT_DESCRIPTOR_SECTION_AP_RW_NO: + case TT_DESCRIPTOR_SECTION_AP_RW_RW: + // normal read/write access, do not add additional attributes + break; + + // read only cases map to write-protect + case TT_DESCRIPTOR_SECTION_AP_RO_NO: + case TT_DESCRIPTOR_SECTION_AP_RO_RO: + *GcdAttributes |= EFI_MEMORY_RO; + break; + + default: + return EFI_UNSUPPORTED; + } + + // now process eXectue Never attribute + if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) { + *GcdAttributes |= EFI_MEMORY_XP; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +PageToGcdAttributes ( + IN UINT32 PageAttributes, + OUT UINT64 *GcdAttributes + ) +{ + *GcdAttributes = 0; + + // determine cacheability attributes + switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) { + case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED: + *GcdAttributes |= EFI_MEMORY_UC; + break; + case TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE: + *GcdAttributes |= EFI_MEMORY_UC; + break; + case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC: + *GcdAttributes |= EFI_MEMORY_WT; + break; + case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC: + *GcdAttributes |= EFI_MEMORY_WB; + break; + case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE: + *GcdAttributes |= EFI_MEMORY_WC; + break; + case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC: + *GcdAttributes |= EFI_MEMORY_WB; + break; + case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE: + *GcdAttributes |= EFI_MEMORY_UC; + break; + default: + return EFI_UNSUPPORTED; + } + + // determine protection attributes + switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) { + case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write + //*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP; + break; + + case TT_DESCRIPTOR_PAGE_AP_RW_NO: + case TT_DESCRIPTOR_PAGE_AP_RW_RW: + // normal read/write access, do not add additional attributes + break; + + // read only cases map to write-protect + case TT_DESCRIPTOR_PAGE_AP_RO_NO: + case TT_DESCRIPTOR_PAGE_AP_RO_RO: + *GcdAttributes |= EFI_MEMORY_RO; + break; + + default: + return EFI_UNSUPPORTED; + } + + // now process eXectue Never attribute + if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0 ) { + *GcdAttributes |= EFI_MEMORY_XP; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +SyncCacheConfigPage ( + IN UINT32 SectionIndex, + IN UINT32 FirstLevelDescriptor, + IN UINTN NumberOfDescriptors, + IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, + IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase, + IN OUT UINT64 *NextRegionLength, + IN OUT UINT32 *NextSectionAttributes + ) +{ + EFI_STATUS Status; + UINT32 i; + volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable; + UINT32 NextPageAttributes = 0; + UINT32 PageAttributes = 0; + UINT32 BaseAddress; + UINT64 GcdAttributes; + + // Get the Base Address from FirstLevelDescriptor; + BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT); + + // Convert SectionAttributes into PageAttributes + NextPageAttributes = + TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) | + TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes); + + // obtain page table base + SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK); + + for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) { + if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) { + // extract attributes (cacheability and permissions) + PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK); + + if (NextPageAttributes == 0) { + // start on a new region + *NextRegionLength = 0; + *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT); + NextPageAttributes = PageAttributes; + } else if (PageAttributes != NextPageAttributes) { + // Convert Section Attributes into GCD Attributes + Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes); + ASSERT_EFI_ERROR (Status); + + // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) + SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes); + + // start on a new region + *NextRegionLength = 0; + *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT); + NextPageAttributes = PageAttributes; + } + } else if (NextPageAttributes != 0) { + // Convert Page Attributes into GCD Attributes + Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes); + ASSERT_EFI_ERROR (Status); + + // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) + SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes); + + *NextRegionLength = 0; + *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT); + NextPageAttributes = 0; + } + *NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE; + } + + // Convert back PageAttributes into SectionAttributes + *NextSectionAttributes = + TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) | + TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes); + + return EFI_SUCCESS; +} + +EFI_STATUS +SyncCacheConfig ( + IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol + ) +{ + EFI_STATUS Status; + UINT32 i; + EFI_PHYSICAL_ADDRESS NextRegionBase; + UINT64 NextRegionLength; + UINT32 NextSectionAttributes = 0; + UINT32 SectionAttributes = 0; + UINT64 GcdAttributes; + volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; + UINTN NumberOfDescriptors; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; + + + DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n")); + + // This code assumes MMU is enabled and filed with section translations + ASSERT (ArmMmuEnabled ()); + + // + // Get the memory space map from GCD + // + MemorySpaceMap = NULL; + Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); + ASSERT_EFI_ERROR (Status); + + + // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs + // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a + // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were + // a client) to update its copy of the attributes. This is bad architecture and should be replaced + // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead. + + // obtain page table base + FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ()); + + // Get the first region + NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK); + + // iterate through each 1MB descriptor + NextRegionBase = NextRegionLength = 0; + for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) { + if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) { + // extract attributes (cacheability and permissions) + SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK); + + if (NextSectionAttributes == 0) { + // start on a new region + NextRegionLength = 0; + NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT); + NextSectionAttributes = SectionAttributes; + } else if (SectionAttributes != NextSectionAttributes) { + // Convert Section Attributes into GCD Attributes + Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes); + ASSERT_EFI_ERROR (Status); + + // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) + SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes); + + // start on a new region + NextRegionLength = 0; + NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT); + NextSectionAttributes = SectionAttributes; + } + NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE; + } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) { + // In this case any bits set in the 'NextSectionAttributes' are garbage and were set from + // bits that are actually part of the pagetable address. We clear it out to zero so that + // the SyncCacheConfigPage will use the page attributes instead of trying to convert the + // section attributes into page attributes + NextSectionAttributes = 0; + Status = SyncCacheConfigPage ( + i,FirstLevelTable[i], + NumberOfDescriptors, MemorySpaceMap, + &NextRegionBase,&NextRegionLength,&NextSectionAttributes); + ASSERT_EFI_ERROR (Status); + } else { + // We do not support yet 16MB sections + ASSERT ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) != TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION); + + // start on a new region + if (NextSectionAttributes != 0) { + // Convert Section Attributes into GCD Attributes + Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes); + ASSERT_EFI_ERROR (Status); + + // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) + SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes); + + NextRegionLength = 0; + NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT); + NextSectionAttributes = 0; + } + NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE; + } + } // section entry loop + + if (NextSectionAttributes != 0) { + // Convert Section Attributes into GCD Attributes + Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes); + ASSERT_EFI_ERROR (Status); + + // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) + SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes); + } + + FreePool (MemorySpaceMap); + + return EFI_SUCCESS; +} + +UINT64 +EfiAttributeToArmAttribute ( + IN UINT64 EfiAttributes + ) +{ + UINT64 ArmAttributes; + + switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) { + case EFI_MEMORY_UC: + // Map to strongly ordered + ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 + break; + + case EFI_MEMORY_WC: + // Map to normal non-cachable + ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 + break; + + case EFI_MEMORY_WT: + // Write through with no-allocate + ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 + break; + + case EFI_MEMORY_WB: + // Write back (with allocate) + ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 + break; + + case EFI_MEMORY_UCE: + default: + ArmAttributes = TT_DESCRIPTOR_SECTION_TYPE_FAULT; + break; + } + + // Determine protection attributes + if (EfiAttributes & EFI_MEMORY_RO) { + ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RO_RO; + } else { + ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RW_RW; + } + + // Determine eXecute Never attribute + if (EfiAttributes & EFI_MEMORY_XP) { + ArmAttributes |= TT_DESCRIPTOR_SECTION_XN_MASK; + } + + return ArmAttributes; +} + +EFI_STATUS +GetMemoryRegionPage ( + IN UINT32 *PageTable, + IN OUT UINTN *BaseAddress, + OUT UINTN *RegionLength, + OUT UINTN *RegionAttributes + ) +{ + UINT32 PageAttributes; + UINT32 TableIndex; + UINT32 PageDescriptor; + + // Convert the section attributes into page attributes + PageAttributes = ConvertSectionAttributesToPageAttributes (*RegionAttributes, 0); + + // Calculate index into first level translation table for start of modification + TableIndex = ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; + ASSERT (TableIndex < TRANSLATION_TABLE_PAGE_COUNT); + + // Go through the page table to find the end of the section + for (; TableIndex < TRANSLATION_TABLE_PAGE_COUNT; TableIndex++) { + // Get the section at the given index + PageDescriptor = PageTable[TableIndex]; + + if ((PageDescriptor & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_FAULT) { + // Case: End of the boundary of the region + return EFI_SUCCESS; + } else if ((PageDescriptor & TT_DESCRIPTOR_PAGE_TYPE_PAGE) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) { + if ((PageDescriptor & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK) == PageAttributes) { + *RegionLength = *RegionLength + TT_DESCRIPTOR_PAGE_SIZE; + } else { + // Case: End of the boundary of the region + return EFI_SUCCESS; + } + } else { + // We do not support Large Page yet. We return EFI_SUCCESS that means end of the region. + ASSERT(0); + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +EFI_STATUS +GetMemoryRegion ( + IN OUT UINTN *BaseAddress, + OUT UINTN *RegionLength, + OUT UINTN *RegionAttributes + ) +{ + EFI_STATUS Status; + UINT32 TableIndex; + UINT32 PageAttributes; + UINT32 PageTableIndex; + UINT32 SectionDescriptor; + ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; + UINT32 *PageTable; + + // Initialize the arguments + *RegionLength = 0; + + // Obtain page table base + FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress (); + + // Calculate index into first level translation table for start of modification + TableIndex = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (*BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; + ASSERT (TableIndex < TRANSLATION_TABLE_SECTION_COUNT); + + // Get the section at the given index + SectionDescriptor = FirstLevelTable[TableIndex]; + + // If 'BaseAddress' belongs to the section then round it to the section boundary + if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) || + ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION)) + { + *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK; + *RegionAttributes = SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK; + } else { + // Otherwise, we round it to the page boundary + *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK; + + // Get the attribute at the page table level (Level 2) + PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK); + + // Calculate index into first level translation table for start of modification + PageTableIndex = ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; + ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT); + + PageAttributes = PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK; + *RegionAttributes = TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (PageAttributes, 0) | + TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttributes); + } + + for (;TableIndex < TRANSLATION_TABLE_SECTION_COUNT; TableIndex++) { + // Get the section at the given index + SectionDescriptor = FirstLevelTable[TableIndex]; + + // If the entry is a level-2 page table then we scan it to find the end of the region + if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (SectionDescriptor)) { + // Extract the page table location from the descriptor + PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK); + + // Scan the page table to find the end of the region. + Status = GetMemoryRegionPage (PageTable, BaseAddress, RegionLength, RegionAttributes); + + // If we have found the end of the region (Status == EFI_SUCCESS) then we exit the for-loop + if (Status == EFI_SUCCESS) { + break; + } + } else if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) || + ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION)) { + if ((SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK) != *RegionAttributes) { + // If the attributes of the section differ from the one targeted then we exit the loop + break; + } else { + *RegionLength = *RegionLength + TT_DESCRIPTOR_SECTION_SIZE; + } + } else { + // If we are on an invalid section then it means it is the end of our section. + break; + } + } + + return EFI_SUCCESS; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.c new file mode 100644 index 00000000..5e923d45 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.c @@ -0,0 +1,289 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2011, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CpuDxe.h" + +#include + +BOOLEAN mIsFlushingGCD; + +/** + This function flushes the range of addresses from Start to Start+Length + from the processor's data cache. If Start is not aligned to a cache line + boundary, then the bytes before Start to the preceding cache line boundary + are also flushed. If Start+Length is not aligned to a cache line boundary, + then the bytes past Start+Length to the end of the next cache line boundary + are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be + supported. If the data cache is fully coherent with all DMA operations, then + this function can just return EFI_SUCCESS. If the processor does not support + flushing a range of the data cache, then the entire data cache can be flushed. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param Start The beginning physical address to flush from the processor's data + cache. + @param Length The number of bytes to flush from the processor's data cache. This + function may flush more bytes than Length specifies depending upon + the granularity of the flush operation that the processor supports. + @param FlushType Specifies the type of flush operation to perform. + + @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from + the processor's data cache. + @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified + by FlushType. + @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed + from the processor's data cache. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ) +{ + + switch (FlushType) { + case EfiCpuFlushTypeWriteBack: + WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); + break; + case EfiCpuFlushTypeInvalidate: + InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); + break; + case EfiCpuFlushTypeWriteBackInvalidate: + WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); + break; + default: + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + + +/** + This function enables interrupt processing by the processor. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS Interrupts are enabled on the processor. + @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + ArmEnableInterrupts (); + + return EFI_SUCCESS; +} + + +/** + This function disables interrupt processing by the processor. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS Interrupts are disabled on the processor. + @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + ArmDisableInterrupts (); + + return EFI_SUCCESS; +} + + +/** + This function retrieves the processor's current interrupt state a returns it in + State. If interrupts are currently enabled, then TRUE is returned. If interrupts + are currently disabled, then FALSE is returned. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param State A pointer to the processor's current interrupt state. Set to TRUE if + interrupts are enabled and FALSE if interrupts are disabled. + + @retval EFI_SUCCESS The processor's current interrupt state was returned in State. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ) +{ + if (State == NULL) { + return EFI_INVALID_PARAMETER; + } + + *State = ArmGetInterruptState(); + return EFI_SUCCESS; +} + + +/** + This function generates an INIT on the processor. If this function succeeds, then the + processor will be reset, and control will not be returned to the caller. If InitType is + not supported by this processor, or the processor cannot programmatically generate an + INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error + occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param InitType The type of processor INIT to perform. + + @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen. + @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported + by this processor. + @retval EFI_DEVICE_ERROR The processor INIT failed. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + return RegisterInterruptHandler (InterruptType, InterruptHandler); +} + +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Callback function for idle events. + + @param Event Event whose notification function is being invoked. + @param Context The pointer to the notification function's context, + which is implementation-dependent. + +**/ +VOID +EFIAPI +IdleLoopEventCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + CpuSleep (); +} + +// +// Globals used to initialize the protocol +// +EFI_HANDLE mCpuHandle = NULL; +EFI_CPU_ARCH_PROTOCOL mCpu = { + CpuFlushCpuDataCache, + CpuEnableInterrupt, + CpuDisableInterrupt, + CpuGetInterruptState, + CpuInit, + CpuRegisterInterruptHandler, + CpuGetTimerValue, + CpuSetMemoryAttributes, + 0, // NumberOfTimers + 2048, // DmaBufferAlignment +}; + +STATIC +VOID +InitializeDma ( + IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol + ) +{ + CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule (); +} + +EFI_STATUS +CpuDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT IdleLoopEvent; + + InitializeExceptions (&mCpu); + + InitializeDma (&mCpu); + + Status = gBS->InstallMultipleProtocolInterfaces ( + &mCpuHandle, + &gEfiCpuArchProtocolGuid, &mCpu, + NULL + ); + + // + // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes () + // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go + // after the protocol is installed + // + mIsFlushingGCD = TRUE; + SyncCacheConfig (&mCpu); + mIsFlushingGCD = FALSE; + + // If the platform is a MPCore system then install the Configuration Table describing the + // secondary core states + if (ArmIsMpCore()) { + PublishArmProcessorTable(); + } + + // + // Setup a callback for idle events + // + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + IdleLoopEventCallback, + NULL, + &gIdleLoopEventGuid, + &IdleLoopEvent + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.h new file mode 100644 index 00000000..a0f71e69 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -0,0 +1,160 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __CPU_DXE_ARM_EXCEPTION_H__ +#define __CPU_DXE_ARM_EXCEPTION_H__ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +extern BOOLEAN mIsFlushingGCD; + +/** + This function registers and enables the handler specified by InterruptHandler for a processor + interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the + handler for the processor interrupt or exception type specified by InterruptType is uninstalled. + The installed handler is called once for each processor interrupt or exception. + + @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts + are enabled and FALSE if interrupts are disabled. + @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. If this parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported. + +**/ +EFI_STATUS +RegisterInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ); + + +/** + This function registers and enables the handler specified by InterruptHandler for a processor + interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the + handler for the processor interrupt or exception type specified by InterruptType is uninstalled. + The installed handler is called once for each processor interrupt or exception. + + @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts + are enabled and FALSE if interrupts are disabled. + @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. If this parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported. + +**/ +EFI_STATUS +RegisterDebuggerInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ); + + +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +EFI_STATUS +InitializeExceptions ( + IN EFI_CPU_ARCH_PROTOCOL *Cpu + ); + +EFI_STATUS +SyncCacheConfig ( + IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol + ); + +/** + * Publish ARM Processor Data table in UEFI SYSTEM Table. + * @param HobStart Pointer to the beginning of the HOB List from PEI. + * + * Description : This function iterates through HOB list and finds ARM processor Table Entry HOB. + * If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory + * and a pointer is assigned to it in ARM processor table. Then the ARM processor table is + * installed in EFI configuration table. +**/ +VOID +EFIAPI +PublishArmProcessorTable( + VOID + ); + +// The ARM Attributes might be defined on 64-bit (case of the long format description table) +UINT64 +EfiAttributeToArmAttribute ( + IN UINT64 EfiAttributes + ); + +EFI_STATUS +GetMemoryRegion ( + IN OUT UINTN *BaseAddress, + OUT UINTN *RegionLength, + OUT UINTN *RegionAttributes + ); + +VOID +GetRootTranslationTableInfo ( + IN UINTN T0SZ, + OUT UINTN *TableLevel, + OUT UINTN *TableEntryCount + ); + +EFI_STATUS +SetGcdMemorySpaceAttributes ( + IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, + IN UINTN NumberOfDescriptors, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +#endif // __CPU_DXE_ARM_EXCEPTION_H__ diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf new file mode 100644 index 00000000..d068e068 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf @@ -0,0 +1,79 @@ +#/** @file +# +# DXE CPU driver +# +# Copyright (c) 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmCpuDxe + FILE_GUID = B8D9777E-D72A-451F-9BDB-BAFB52A68415 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = CpuDxeInitialize + +[Sources.Common] + CpuDxe.c + CpuDxe.h + CpuMpCore.c + CpuMmuCommon.c + Exception.c + +[Sources.ARM] + Arm/Mmu.c + +[Sources.AARCH64] + AArch64/Mmu.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + ArmLib + ArmMmuLib + BaseMemoryLib + CacheMaintenanceLib + CpuLib + CpuExceptionHandlerLib + DebugLib + DefaultExceptionHandlerLib + DxeServicesTableLib + HobLib + PeCoffGetEntryPointLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gEfiCpuArchProtocolGuid + gEfiDebugSupportPeriodicCallbackProtocolGuid + +[Guids] + gEfiDebugImageInfoTableGuid + gArmMpCoreInfoGuid + gIdleLoopEventGuid + gEfiVectorHandoffTableGuid + +[Pcd.common] + gArmTokenSpaceGuid.PcdVFPEnabled + +[FeaturePcd.common] + gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport + gArmTokenSpaceGuid.PcdDebuggerExceptionSupport + +[Depex] + TRUE diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c new file mode 100644 index 00000000..81504862 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c @@ -0,0 +1,217 @@ +/** @file +* +* Copyright (c) 2013, ARM Limited. All rights reserved. +* Copyright (c) 2017, Intel Corporation. All rights reserved.
+* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "CpuDxe.h" + +/** + Searches memory descriptors covered by given memory range. + + This function searches into the Gcd Memory Space for descriptors + (from StartIndex to EndIndex) that contains the memory range + specified by BaseAddress and Length. + + @param MemorySpaceMap Gcd Memory Space Map as array. + @param NumberOfDescriptors Number of descriptors in map. + @param BaseAddress BaseAddress for the requested range. + @param Length Length for the requested range. + @param StartIndex Start index into the Gcd Memory Space Map. + @param EndIndex End index into the Gcd Memory Space Map. + + @retval EFI_SUCCESS Search successfully. + @retval EFI_NOT_FOUND The requested descriptors does not exist. + +**/ +EFI_STATUS +SearchGcdMemorySpaces ( + IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, + IN UINTN NumberOfDescriptors, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + OUT UINTN *StartIndex, + OUT UINTN *EndIndex + ) +{ + UINTN Index; + + *StartIndex = 0; + *EndIndex = 0; + for (Index = 0; Index < NumberOfDescriptors; Index++) { + if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) && + (BaseAddress < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) { + *StartIndex = Index; + } + if (((BaseAddress + Length - 1) >= MemorySpaceMap[Index].BaseAddress) && + ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) { + *EndIndex = Index; + return EFI_SUCCESS; + } + } + return EFI_NOT_FOUND; +} + + +/** + Sets the attributes for a specified range in Gcd Memory Space Map. + + This function sets the attributes for a specified range in + Gcd Memory Space Map. + + @param MemorySpaceMap Gcd Memory Space Map as array + @param NumberOfDescriptors Number of descriptors in map + @param BaseAddress BaseAddress for the range + @param Length Length for the range + @param Attributes Attributes to set + + @retval EFI_SUCCESS Memory attributes set successfully + @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space + +**/ +EFI_STATUS +SetGcdMemorySpaceAttributes ( + IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, + IN UINTN NumberOfDescriptors, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + EFI_STATUS Status; + UINTN Index; + UINTN StartIndex; + UINTN EndIndex; + EFI_PHYSICAL_ADDRESS RegionStart; + UINT64 RegionLength; + + DEBUG ((DEBUG_GCD, "SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n", + BaseAddress, BaseAddress + Length, Attributes)); + + // We do not support a smaller granularity than 4KB on ARM Architecture + if ((Length & EFI_PAGE_MASK) != 0) { + DEBUG ((DEBUG_WARN, + "Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n", + Length)); + } + + // + // Get all memory descriptors covered by the memory range + // + Status = SearchGcdMemorySpaces ( + MemorySpaceMap, + NumberOfDescriptors, + BaseAddress, + Length, + &StartIndex, + &EndIndex + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Go through all related descriptors and set attributes accordingly + // + for (Index = StartIndex; Index <= EndIndex; Index++) { + if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) { + continue; + } + // + // Calculate the start and end address of the overlapping range + // + if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) { + RegionStart = BaseAddress; + } else { + RegionStart = MemorySpaceMap[Index].BaseAddress; + } + if ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)) { + RegionLength = BaseAddress + Length - RegionStart; + } else { + RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart; + } + // + // Set memory attributes according to MTRR attribute and the original attribute of descriptor + // + gDS->SetMemorySpaceAttributes ( + RegionStart, + RegionLength, + (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes) + ); + } + + return EFI_SUCCESS; +} + +/** + This function modifies the attributes for the memory region specified by BaseAddress and + Length from their current attributes to the attributes specified by Attributes. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param BaseAddress The physical address that is the start address of a memory region. + @param Length The size in bytes of the memory region. + @param Attributes The bit mask of attributes to set for the memory region. + + @retval EFI_SUCCESS The attributes were set for the memory region. + @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by + BaseAddress and Length cannot be modified. + @retval EFI_INVALID_PARAMETER Length is zero. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of + the memory resource range. + @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory + resource range specified by BaseAddress and Length. + The bit mask of attributes is not support for the memory resource + range specified by BaseAddress and Length. + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 EfiAttributes + ) +{ + EFI_STATUS Status; + UINTN ArmAttributes; + UINTN RegionBaseAddress; + UINTN RegionLength; + UINTN RegionArmAttributes; + + if (mIsFlushingGCD) { + return EFI_SUCCESS; + } + + if ((BaseAddress & (SIZE_4KB - 1)) != 0) { + // Minimum granularity is SIZE_4KB (4KB on ARM) + DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes)); + return EFI_UNSUPPORTED; + } + + // Convert the 'Attribute' into ARM Attribute + ArmAttributes = EfiAttributeToArmAttribute (EfiAttributes); + + // Get the region starting from 'BaseAddress' and its 'Attribute' + RegionBaseAddress = BaseAddress; + Status = GetMemoryRegion (&RegionBaseAddress, &RegionLength, &RegionArmAttributes); + + // Data & Instruction Caches are flushed when we set new memory attributes. + // So, we only set the attributes if the new region is different. + if (EFI_ERROR (Status) || (RegionArmAttributes != ArmAttributes) || + ((BaseAddress + Length) > (RegionBaseAddress + RegionLength))) + { + return ArmSetMemoryAttributes (BaseAddress, Length, EfiAttributes); + } else { + return EFI_SUCCESS; + } +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuMpCore.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuMpCore.c new file mode 100644 index 00000000..81d858ea --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/CpuMpCore.c @@ -0,0 +1,103 @@ +/** @file +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include + +#include + +ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = { + { + EFI_ARM_PROCESSOR_TABLE_SIGNATURE, + 0, + EFI_ARM_PROCESSOR_TABLE_REVISION, + EFI_ARM_PROCESSOR_TABLE_OEM_ID, + EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID, + EFI_ARM_PROCESSOR_TABLE_OEM_REVISION, + EFI_ARM_PROCESSOR_TABLE_CREATOR_ID, + EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION, + { 0 }, + 0 + }, //ARM Processor table header + 0, // Number of entries in ARM processor Table + NULL // ARM Processor Table +}; + +/** Publish ARM Processor Data table in UEFI SYSTEM Table. + * @param: HobStart Pointer to the beginning of the HOB List from PEI. + * + * Description : This function iterates through HOB list and finds ARM processor Table Entry HOB. + * If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory + * and a pointer is assigned to it in ARM processor table. Then the ARM processor table is + * installed in EFI configuration table. +**/ +VOID +EFIAPI +PublishArmProcessorTable ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + + Hob.Raw = GetHobList (); + + // Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB + for (; !END_OF_HOB_LIST(Hob); Hob.Raw = GET_NEXT_HOB(Hob)) { + // Check for Correct HOB type + if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) { + // Check for correct GUID type + if (CompareGuid(&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) { + ARM_PROCESSOR_TABLE *ArmProcessorTable; + EFI_STATUS Status; + + // Allocate Runtime memory for ARM processor table + ArmProcessorTable = (ARM_PROCESSOR_TABLE*)AllocateRuntimePool(sizeof(ARM_PROCESSOR_TABLE)); + + // Check if the memory allocation is succesful or not + ASSERT(NULL != ArmProcessorTable); + + // Set ARM processor table to default values + CopyMem(ArmProcessorTable,&mArmProcessorTableTemplate,sizeof(ARM_PROCESSOR_TABLE)); + + // Fill in Length fields of ARM processor table + ArmProcessorTable->Header.Length = sizeof(ARM_PROCESSOR_TABLE); + ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE(Hob); + + // Fill in Identifier(ARM processor table GUID) + ArmProcessorTable->Header.Identifier = gArmMpCoreInfoGuid; + + // Set Number of ARM core entries in the Table + ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE(Hob)/sizeof(ARM_CORE_INFO); + + // Allocate runtime memory for ARM processor Table entries + ArmProcessorTable->ArmCpus = (ARM_CORE_INFO*)AllocateRuntimePool ( + ArmProcessorTable->NumberOfEntries * sizeof(ARM_CORE_INFO)); + + // Check if the memory allocation is succesful or not + ASSERT(NULL != ArmProcessorTable->ArmCpus); + + // Copy ARM Processor Table data from HOB list to newly allocated memory + CopyMem(ArmProcessorTable->ArmCpus,GET_GUID_HOB_DATA(Hob), ArmProcessorTable->Header.DataLen); + + // Install the ARM Processor table into EFI system configuration table + Status = gBS->InstallConfigurationTable (&gArmMpCoreInfoGuid, ArmProcessorTable); + + ASSERT_EFI_ERROR (Status); + } + } + } +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/Exception.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/Exception.c new file mode 100644 index 00000000..d806a5fd --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuDxe/Exception.c @@ -0,0 +1,104 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CpuDxe.h" +#include +#include + +EFI_STATUS +InitializeExceptions ( + IN EFI_CPU_ARCH_PROTOCOL *Cpu + ) { + EFI_STATUS Status; + EFI_VECTOR_HANDOFF_INFO *VectorInfoList; + EFI_VECTOR_HANDOFF_INFO *VectorInfo; + BOOLEAN IrqEnabled; + BOOLEAN FiqEnabled; + + VectorInfo = (EFI_VECTOR_HANDOFF_INFO *)NULL; + Status = EfiGetSystemConfigurationTable(&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList); + if (Status == EFI_SUCCESS && VectorInfoList != NULL) { + VectorInfo = VectorInfoList; + } + + // intialize the CpuExceptionHandlerLib so we take over the exception vector table from the DXE Core + InitializeCpuExceptionHandlers(VectorInfo); + + Status = EFI_SUCCESS; + + // + // Disable interrupts + // + Cpu->GetInterruptState (Cpu, &IrqEnabled); + Cpu->DisableInterrupt (Cpu); + + // + // EFI does not use the FIQ, but a debugger might so we must disable + // as we take over the exception vectors. + // + FiqEnabled = ArmGetFiqState (); + ArmDisableFiq (); + + if (FiqEnabled) { + ArmEnableFiq (); + } + + if (IrqEnabled) { + // + // Restore interrupt state + // + Status = Cpu->EnableInterrupt (Cpu); + } + + // + // On a DEBUG build, unmask SErrors so they are delivered right away rather + // than when the OS unmasks them. This gives us a better chance of figuring + // out the cause. + // + DEBUG_CODE ( + ArmEnableAsynchronousAbort (); + ); + + return Status; +} + +/** +This function registers and enables the handler specified by InterruptHandler for a processor +interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the +handler for the processor interrupt or exception type specified by InterruptType is uninstalled. +The installed handler is called once for each processor interrupt or exception. + +@param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts +are enabled and FALSE if interrupts are disabled. +@param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called +when a processor interrupt occurs. If this parameter is NULL, then the handler +will be uninstalled. + +@retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled. +@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was +previously installed. +@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not +previously installed. +@retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported. + +**/ +EFI_STATUS +RegisterInterruptHandler( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) { + // pass down to CpuExceptionHandlerLib + return (EFI_STATUS)RegisterCpuInterruptHandler(InterruptType, InterruptHandler); +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuPei/CpuPei.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuPei/CpuPei.c new file mode 100644 index 00000000..d54f42ac --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuPei/CpuPei.c @@ -0,0 +1,91 @@ +/**@file + +Copyright (c) 2006, Intel Corporation. All rights reserved.
+Copyright (c) 2011 Hewlett Packard Corporation. All rights reserved.
+Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +Module Name: + + MemoryInit.c + +Abstract: + + PEIM to provide fake memory init + +**/ + + + +// +// The package level header files this module uses +// +#include +// +// The protocols, PPI and GUID defintions for this module +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include + +/*++ + +Routine Description: + +Arguments: + + FileHandle - Handle of the file being invoked. + PeiServices - Describes the list of possible PEI Services. + +Returns: + + Status - EFI_SUCCESS if the boot mode could be set + +--*/ +EFI_STATUS +EFIAPI +InitializeCpuPeim ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi; + UINTN ArmCoreCount; + ARM_CORE_INFO *ArmCoreInfoTable; + + // Enable program flow prediction, if supported. + ArmEnableBranchPrediction (); + + // Publish the CPU memory and io spaces sizes + BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize)); + + // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid + Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID**)&ArmMpCoreInfoPpi); + if (!EFI_ERROR(Status)) { + // Build the MP Core Info Table + ArmCoreCount = 0; + Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable); + if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) { + // Build MPCore Info HOB + BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount); + } + } + + return EFI_SUCCESS; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuPei/CpuPei.inf b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuPei/CpuPei.inf new file mode 100644 index 00000000..eafccd60 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/CpuPei/CpuPei.inf @@ -0,0 +1,58 @@ +## @file +# Component description file for BootMode module +# +# This module provides platform specific function to detect boot mode. +# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = CpuPei + FILE_GUID = 2FD8B7AD-F8FA-4021-9FC0-0AA572147CDC + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeCpuPeim + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = ARM +# + +[Sources] + CpuPei.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + PeimEntryPoint + DebugLib + HobLib + ArmLib + +[Ppis] + gArmMpCoreInfoPpiGuid + +[Guids] + gArmMpCoreInfoGuid + +[FixedPcd] + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize + +[Depex] + gEfiPeiMemoryDiscoveredPpiGuid + diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h new file mode 100644 index 00000000..9e2aebcf --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h @@ -0,0 +1,29 @@ +/** @file +* +* Copyright (c) 2013-2017, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD +* License which accompanies this distribution. The full text of the license +* may be found at http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ +#ifndef __GENERIC_WATCHDOG_H__ +#define __GENERIC_WATCHDOG_H__ + +// Refresh Frame: +#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000) + +// Control Frame: +#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000) +#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008) +#define GENERIC_WDOG_COMPARE_VALUE_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010) + +// Values of bit 0 of the Control/Status Register +#define GENERIC_WDOG_ENABLED 1 +#define GENERIC_WDOG_DISABLED 0 + +#endif // __GENERIC_WATCHDOG_H__ diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c new file mode 100644 index 00000000..54a1625a --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -0,0 +1,354 @@ +/** @file +* +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD +* License which accompanies this distribution. The full text of the license +* may be found at http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "GenericWatchdog.h" + +// The number of 100ns periods (the unit of time passed to these functions) +// in a second +#define TIME_UNITS_PER_SECOND 10000000 + +// Tick frequency of the generic timer that is the basis of the generic watchdog +UINTN mTimerFrequencyHz = 0; + +// In cases where the compare register was set manually, information about +// how long the watchdog was asked to wait cannot be retrieved from hardware. +// It is therefore stored here. 0 means the timer is not running. +UINT64 mNumTimerTicks = 0; + +EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterruptProtocol; + +EFI_STATUS +WatchdogWriteOffsetRegister ( + UINT32 Value + ) +{ + return MmioWrite32 (GENERIC_WDOG_OFFSET_REG, Value); +} + +EFI_STATUS +WatchdogWriteCompareRegister ( + UINT64 Value + ) +{ + return MmioWrite64 (GENERIC_WDOG_COMPARE_VALUE_REG, Value); +} + +EFI_STATUS +WatchdogEnable ( + VOID + ) +{ + return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_ENABLED); +} + +EFI_STATUS +WatchdogDisable ( + VOID + ) +{ + return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_DISABLED); +} + +/** + On exiting boot services we must make sure the Watchdog Timer + is stopped. +**/ +VOID +EFIAPI +WatchdogExitBootServicesEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + WatchdogDisable (); + mNumTimerTicks = 0; +} + +/* + This function is called when the watchdog's first signal (WS0) goes high. + It uses the ResetSystem Runtime Service to reset the board. +*/ +VOID +EFIAPI +WatchdogInterruptHandler ( + IN HARDWARE_INTERRUPT_SOURCE Source, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + STATIC CONST CHAR16 ResetString[] = L"The generic watchdog timer ran out."; + + WatchdogDisable (); + + mInterruptProtocol->EndOfInterrupt (mInterruptProtocol, Source); + + gRT->ResetSystem ( + EfiResetCold, + EFI_TIMEOUT, + StrSize (ResetString), + (VOID *) &ResetString + ); + + // If we got here then the reset didn't work + ASSERT (FALSE); +} + +/** + This function registers the handler NotifyFunction so it is called every time + the watchdog timer expires. It also passes the amount of time since the last + handler call to the NotifyFunction. + If NotifyFunction is not NULL and a handler is not already registered, + then the new handler is registered and EFI_SUCCESS is returned. + If NotifyFunction is NULL, and a handler is already registered, + then that handler is unregistered. + If an attempt is made to register a handler when a handler is already registered, + then EFI_ALREADY_STARTED is returned. + If an attempt is made to unregister a handler when a handler is not registered, + then EFI_INVALID_PARAMETER is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fires. + This function executes at TPL_HIGH_LEVEL. The DXE + Core will register a handler for the timer interrupt, + so it can know how much time has passed. This + information is used to signal timer based events. + NULL will unregister the handler. + + @retval EFI_SUCCESS The watchdog timer handler was registered. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not + previously registered. + +**/ +EFI_STATUS +EFIAPI +WatchdogRegisterHandler ( + IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction + ) +{ + // ERROR: This function is not supported. + // The watchdog will reset the board + return EFI_UNSUPPORTED; +} + +/** + This function sets the amount of time to wait before firing the watchdog + timer to TimerPeriod 100 nS units. If TimerPeriod is 0, then the watchdog + timer is disabled. + + @param This The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The amount of time in 100 nS units to wait before the watchdog + timer is fired. If TimerPeriod is zero, then the watchdog + timer is disabled. + + @retval EFI_SUCCESS The watchdog timer has been programmed to fire in Time + 100 nS units. + @retval EFI_DEVICE_ERROR A watchdog timer could not be programmed due to a device + error. + +**/ +EFI_STATUS +EFIAPI +WatchdogSetTimerPeriod ( + IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod // In 100ns units + ) +{ + UINTN SystemCount; + EFI_STATUS Status; + + // if TimerPerdiod is 0, this is a request to stop the watchdog. + if (TimerPeriod == 0) { + mNumTimerTicks = 0; + return WatchdogDisable (); + } + + // Work out how many timer ticks will equate to TimerPeriod + mNumTimerTicks = (mTimerFrequencyHz * TimerPeriod) / TIME_UNITS_PER_SECOND; + + // + // If the number of required ticks is greater than the max number the + // watchdog's offset register (WOR) can hold, we need to manually compute and + // set the compare register (WCV) + // + if (mNumTimerTicks > MAX_UINT32) { + // + // We need to enable the watchdog *before* writing to the compare register, + // because enabling the watchdog causes an "explicit refresh", which + // clobbers the compare register (WCV). In order to make sure this doesn't + // trigger an interrupt, set the offset to max. + // + Status = WatchdogWriteOffsetRegister (MAX_UINT32); + if (EFI_ERROR (Status)) { + return Status; + } + WatchdogEnable (); + SystemCount = ArmGenericTimerGetSystemCount (); + Status = WatchdogWriteCompareRegister (SystemCount + mNumTimerTicks); + } else { + Status = WatchdogWriteOffsetRegister ((UINT32)mNumTimerTicks); + WatchdogEnable (); + } + + return Status; +} + +/** + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is + returned, then the timer is currently disabled. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 + ns units. If 0 is returned, then the timer is + currently disabled. + + + @retval EFI_SUCCESS The timer period was returned in TimerPeriod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +WatchdogGetTimerPeriod ( + IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + if (TimerPeriod == NULL) { + return EFI_INVALID_PARAMETER; + } + + *TimerPeriod = ((TIME_UNITS_PER_SECOND / mTimerFrequencyHz) * mNumTimerTicks); + + return EFI_SUCCESS; +} + +/** + Interface structure for the Watchdog Architectural Protocol. + + @par Protocol Description: + This protocol provides a service to set the amount of time to wait + before firing the watchdog timer, and it also provides a service to + register a handler that is invoked when the watchdog timer fires. + + @par When the watchdog timer fires, control will be passed to a handler + if one has been registered. If no handler has been registered, + or the registered handler returns, then the system will be + reset by calling the Runtime Service ResetSystem(). + + @param RegisterHandler + Registers a handler that will be called each time the + watchdogtimer interrupt fires. TimerPeriod defines the minimum + time between timer interrupts, so TimerPeriod will also + be the minimum time between calls to the registered + handler. + NOTE: If the watchdog resets the system in hardware, then + this function will not have any chance of executing. + + @param SetTimerPeriod + Sets the period of the timer interrupt in 100 nS units. + This function is optional, and may return EFI_UNSUPPORTED. + If this function is supported, then the timer period will + be rounded up to the nearest supported timer period. + + @param GetTimerPeriod + Retrieves the period of the timer interrupt in 100 nS units. + +**/ +EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer = { + (EFI_WATCHDOG_TIMER_REGISTER_HANDLER) WatchdogRegisterHandler, + (EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD) WatchdogSetTimerPeriod, + (EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD) WatchdogGetTimerPeriod +}; + +EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL; + +EFI_STATUS +EFIAPI +GenericWatchdogEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + // + // Make sure the Watchdog Timer Architectural Protocol has not been installed + // in the system yet. + // This will avoid conflicts with the universal watchdog + // + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid); + + mTimerFrequencyHz = ArmGenericTimerGetTimerFreq (); + ASSERT (mTimerFrequencyHz != 0); + + // Register for an ExitBootServicesEvent + Status = gBS->CreateEvent ( + EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, + WatchdogExitBootServicesEvent, NULL, &EfiExitBootServicesEvent + ); + if (!EFI_ERROR (Status)) { + // Install interrupt handler + Status = gBS->LocateProtocol ( + &gHardwareInterruptProtocolGuid, + NULL, + (VOID **)&mInterruptProtocol + ); + if (!EFI_ERROR (Status)) { + Status = mInterruptProtocol->RegisterInterruptSource ( + mInterruptProtocol, + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), + WatchdogInterruptHandler + ); + if (!EFI_ERROR (Status)) { + // Install the Timer Architectural Protocol onto a new handle + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer, + NULL + ); + } + } + } + + if (EFI_ERROR (Status)) { + // The watchdog failed to initialize + ASSERT (FALSE); + } + + mNumTimerTicks = 0; + WatchdogDisable (); + + return Status; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf new file mode 100644 index 00000000..fece14cc --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf @@ -0,0 +1,53 @@ +# +# Copyright (c) 2013-2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x00010016 + BASE_NAME = GenericWatchdogDxe + FILE_GUID = 0619f5c2-4858-4caa-a86a-73a21a18df6b + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = GenericWatchdogEntry + +[Sources.common] + GenericWatchdogDxe.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + ArmGenericTimerCounterLib + BaseLib + BaseMemoryLib + DebugLib + IoLib + PcdLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + +[Pcd.common] + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + +[Protocols] + gEfiWatchdogTimerArchProtocolGuid + gHardwareInterruptProtocolGuid + +[Depex] + gHardwareInterruptProtocolGuid diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.c new file mode 100644 index 00000000..2416c90f --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.c @@ -0,0 +1,435 @@ +/** @file + Timer Architecture Protocol driver of the ARM flavor + + Copyright (c) 2011-2013 ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +// The notification function to call on every timer interrupt. +EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL; +EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL; + +// The current period of the timer interrupt +UINT64 mTimerPeriod = 0; +// The latest Timer Tick calculated for mTimerPeriod +UINT64 mTimerTicks = 0; +// Number of elapsed period since the last Timer interrupt +UINT64 mElapsedPeriod = 1; + +// Cached copy of the Hardware Interrupt protocol instance +EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL; + +/** + This function registers the handler NotifyFunction so it is called every time + the timer interrupt fires. It also passes the amount of time since the last + handler call to the NotifyFunction. If NotifyFunction is NULL, then the + handler is unregistered. If the handler is registered, then EFI_SUCCESS is + returned. If the CPU does not support registering a timer interrupt handler, + then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler + when a handler is already registered, then EFI_ALREADY_STARTED is returned. + If an attempt is made to unregister a handler when a handler is not registered, + then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to + register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR + is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fires. This + function executes at TPL_HIGH_LEVEL. The DXE Core will + register a handler for the timer interrupt, so it can know + how much time has passed. This information is used to + signal timer based events. NULL will unregister the handler. + @retval EFI_SUCCESS The timer handler was registered. + @retval EFI_UNSUPPORTED The platform does not support timer interrupts. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not + previously registered. + @retval EFI_DEVICE_ERROR The timer handler could not be registered. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +{ + if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) { + return EFI_ALREADY_STARTED; + } + + mTimerNotifyFunction = NotifyFunction; + + return EFI_SUCCESS; +} + +/** + Disable the timer +**/ +VOID +EFIAPI +ExitBootServicesEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + ArmGenericTimerDisableTimer (); +} + +/** + + This function adjusts the period of timer interrupts to the value specified + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust the + interrupt controller so that a CPU interrupt is not generated when the timer + interrupt fires. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If + the timer hardware is not programmable, then EFI_UNSUPPORTED is + returned. If the timer is programmable, then the timer period + will be rounded up to the nearest timer period that is supported + by the timer hardware. If TimerPeriod is set to 0, then the + timer interrupts will be disabled. + + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +{ + UINT64 CounterValue; + UINT64 TimerTicks; + EFI_TPL OriginalTPL; + + // Always disable the timer + ArmGenericTimerDisableTimer (); + + if (TimerPeriod != 0) { + // mTimerTicks = TimerPeriod in 1ms unit x Frequency.10^-3 + // = TimerPeriod.10^-4 x Frequency.10^-3 + // = (TimerPeriod x Frequency) x 10^-7 + TimerTicks = MultU64x32 (TimerPeriod, ArmGenericTimerGetTimerFreq ()); + TimerTicks = DivU64x32 (TimerTicks, 10000000U); + + // Raise TPL to update the mTimerTicks and mTimerPeriod to ensure these values + // are coherent in the interrupt handler + OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL); + + mTimerTicks = TimerTicks; + mTimerPeriod = TimerPeriod; + mElapsedPeriod = 1; + + gBS->RestoreTPL (OriginalTPL); + + // Get value of the current timer + CounterValue = ArmGenericTimerGetSystemCount (); + // Set the interrupt in Current Time + mTimerTick + ArmGenericTimerSetCompareVal (CounterValue + mTimerTicks); + + // Enable the timer + ArmGenericTimerEnableTimer (); + } else { + // Save the new timer period + mTimerPeriod = TimerPeriod; + // Reset the elapsed period + mElapsedPeriod = 1; + } + + return EFI_SUCCESS; +} + +/** + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is + returned, then the timer is currently disabled. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If + 0 is returned, then the timer is currently disabled. + + + @retval EFI_SUCCESS The timer period was returned in TimerPeriod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + if (TimerPeriod == NULL) { + return EFI_INVALID_PARAMETER; + } + + *TimerPeriod = mTimerPeriod; + return EFI_SUCCESS; +} + +/** + This function generates a soft timer interrupt. If the platform does not support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler() + service, then a soft timer interrupt will be generated. If the timer interrupt is + enabled when this service is called, then the registered handler will be invoked. The + registered handler should not be able to distinguish a hardware-generated timer + interrupt from a software-generated timer interrupt. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Interface structure for the Timer Architectural Protocol. + + @par Protocol Description: + This protocol provides the services to initialize a periodic timer + interrupt, and to register a handler that is called each time the timer + interrupt fires. It may also provide a service to adjust the rate of the + periodic timer interrupt. When a timer interrupt occurs, the handler is + passed the amount of time that has passed since the previous timer + interrupt. + + @param RegisterHandler + Registers a handler that will be called each time the + timer interrupt fires. TimerPeriod defines the minimum + time between timer interrupts, so TimerPeriod will also + be the minimum time between calls to the registered + handler. + + @param SetTimerPeriod + Sets the period of the timer interrupt in 100 nS units. + This function is optional, and may return EFI_UNSUPPORTED. + If this function is supported, then the timer period will + be rounded up to the nearest supported timer period. + + + @param GetTimerPeriod + Retrieves the period of the timer interrupt in 100 nS units. + + @param GenerateSoftInterrupt + Generates a soft timer interrupt that simulates the firing of + the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for + a period of time. + +**/ +EFI_TIMER_ARCH_PROTOCOL gTimer = { + TimerDriverRegisterHandler, + TimerDriverSetTimerPeriod, + TimerDriverGetTimerPeriod, + TimerDriverGenerateSoftInterrupt +}; + +/** + + C Interrupt Handler called in the interrupt context when Source interrupt is active. + + + @param Source Source of the interrupt. Hardware routing off a specific platform defines + what source means. + + @param SystemContext Pointer to system register context. Mostly used by debuggers and will + update the system context after the return from the interrupt if + modified. Don't change these values unless you know what you are doing + +**/ +VOID +EFIAPI +TimerInterruptHandler ( + IN HARDWARE_INTERRUPT_SOURCE Source, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + EFI_TPL OriginalTPL; + UINT64 CurrentValue; + UINT64 CompareValue; + + // + // DXE core uses this callback for the EFI timer tick. The DXE core uses locks + // that raise to TPL_HIGH and then restore back to current level. Thus we need + // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick. + // + OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL); + + // Check if the timer interrupt is active + if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) { + + // Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers + gInterrupt->EndOfInterrupt (gInterrupt, Source); + + if (mTimerNotifyFunction) { + mTimerNotifyFunction (mTimerPeriod * mElapsedPeriod); + } + + // + // Reload the Timer + // + + // Get current counter value + CurrentValue = ArmGenericTimerGetSystemCount (); + // Get the counter value to compare with + CompareValue = ArmGenericTimerGetCompareVal (); + + // This loop is needed in case we missed interrupts (eg: case when the interrupt handling + // has taken longer than mTickPeriod). + // Note: Physical Counter is counting up + mElapsedPeriod = 0; + do { + CompareValue += mTimerTicks; + mElapsedPeriod++; + } while (CompareValue < CurrentValue); + + // Set next compare value + ArmGenericTimerSetCompareVal (CompareValue); + ArmGenericTimerEnableTimer (); + } + + // Enable timer interrupts + gInterrupt->EnableInterruptSource (gInterrupt, Source); + + gBS->RestoreTPL (OriginalTPL); +} + + +/** + Initialize the state information for the Timer Architectural Protocol and + the Timer Debug support protocol that allows the debugger to break into a + running program. + + @param ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Protocol registered + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Hardware problems + +**/ +EFI_STATUS +EFIAPI +TimerInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_HANDLE Handle = NULL; + EFI_STATUS Status; + UINTN TimerCtrlReg; + UINT32 TimerHypIntrNum; + + if (ArmIsArchTimerImplemented () == 0) { + DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence cann't use this Driver \n")); + ASSERT (0); + } + + // Find the interrupt controller protocol. ASSERT if not found. + Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt); + ASSERT_EFI_ERROR (Status); + + // Disable the timer + TimerCtrlReg = ArmGenericTimerGetTimerCtrlReg (); + TimerCtrlReg |= ARM_ARCH_TIMER_IMASK; + TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE; + ArmGenericTimerSetTimerCtrlReg (TimerCtrlReg); + Status = TimerDriverSetTimerPeriod (&gTimer, 0); + ASSERT_EFI_ERROR (Status); + + // Install secure and Non-secure interrupt handlers + // Note: Because it is not possible to determine the security state of the + // CPU dynamically, we just install interrupt handler for both sec and non-sec + // timer PPI + Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerVirtIntrNum), TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + + // + // The hypervisor timer interrupt may be omitted by implementations that + // execute under virtualization. + // + TimerHypIntrNum = PcdGet32 (PcdArmArchTimerHypIntrNum); + if (TimerHypIntrNum != 0) { + Status = gInterrupt->RegisterInterruptSource (gInterrupt, TimerHypIntrNum, TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + } + + Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerSecIntrNum), TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + + Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum), TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + + // Set up default timer + Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD + ASSERT_EFI_ERROR (Status); + + // Install the Timer Architectural Protocol onto a new handle + Status = gBS->InstallMultipleProtocolInterfaces( + &Handle, + &gEfiTimerArchProtocolGuid, &gTimer, + NULL + ); + ASSERT_EFI_ERROR(Status); + + // Everything is ready, unmask and enable timer interrupts + TimerCtrlReg = ARM_ARCH_TIMER_ENABLE; + ArmGenericTimerSetTimerCtrlReg (TimerCtrlReg); + + // Register for an ExitBootServicesEvent + Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.inf b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.inf new file mode 100644 index 00000000..3f345156 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.inf @@ -0,0 +1,60 @@ +#/** @file +# +# Component description file for Timer DXE module +# +# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmTimerDxe + FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = TimerInitialize + +[Sources.common] + TimerDxe.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + ArmLib + BaseLib + UefiRuntimeServicesTableLib + UefiLib + UefiBootServicesTableLib + BaseMemoryLib + DebugLib + UefiDriverEntryPoint + IoLib + ArmGenericTimerCounterLib + +[Guids] + +[Protocols] + gEfiTimerArchProtocolGuid + gHardwareInterruptProtocolGuid + +[Pcd.common] + gEmbeddedTokenSpaceGuid.PcdTimerPeriod + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + +[Depex] + gHardwareInterruptProtocolGuid diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c new file mode 100644 index 00000000..92aa5f8b --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c @@ -0,0 +1,1209 @@ +/** @file + Support a Semi Host file system over a debuggers JTAG + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "SemihostFs.h" + +#define DEFAULT_SEMIHOST_FS_LABEL L"SemihostFs" + +STATIC CHAR16 *mSemihostFsLabel; + +EFI_SIMPLE_FILE_SYSTEM_PROTOCOL gSemihostFs = { + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION, + VolumeOpen +}; + +EFI_FILE gSemihostFsFile = { + EFI_FILE_PROTOCOL_REVISION, + FileOpen, + FileClose, + FileDelete, + FileRead, + FileWrite, + FileGetPosition, + FileSetPosition, + FileGetInfo, + FileSetInfo, + FileFlush +}; + +// +// Device path for semi-hosting. It contains our autogened Caller ID GUID. +// +typedef struct { + VENDOR_DEVICE_PATH Guid; + EFI_DEVICE_PATH_PROTOCOL End; +} SEMIHOST_DEVICE_PATH; + +SEMIHOST_DEVICE_PATH gDevicePath = { + { + { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 } }, + EFI_CALLER_ID_GUID + }, + { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } } +}; + +typedef struct { + LIST_ENTRY Link; + UINT64 Signature; + EFI_FILE File; + CHAR8 *FileName; + UINT64 OpenMode; + UINT32 Position; + UINTN SemihostHandle; + BOOLEAN IsRoot; + EFI_FILE_INFO Info; +} SEMIHOST_FCB; + +#define SEMIHOST_FCB_SIGNATURE SIGNATURE_32( 'S', 'H', 'F', 'C' ) +#define SEMIHOST_FCB_FROM_THIS(a) CR(a, SEMIHOST_FCB, File, SEMIHOST_FCB_SIGNATURE) +#define SEMIHOST_FCB_FROM_LINK(a) CR(a, SEMIHOST_FCB, Link, SEMIHOST_FCB_SIGNATURE); + +EFI_HANDLE gInstallHandle = NULL; +LIST_ENTRY gFileList = INITIALIZE_LIST_HEAD_VARIABLE (gFileList); + +SEMIHOST_FCB * +AllocateFCB ( + VOID + ) +{ + SEMIHOST_FCB *Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB)); + + if (Fcb != NULL) { + CopyMem (&Fcb->File, &gSemihostFsFile, sizeof (gSemihostFsFile)); + Fcb->Signature = SEMIHOST_FCB_SIGNATURE; + } + + return Fcb; +} + +VOID +FreeFCB ( + IN SEMIHOST_FCB *Fcb + ) +{ + // Remove Fcb from gFileList. + RemoveEntryList (&Fcb->Link); + + // To help debugging... + Fcb->Signature = 0; + + FreePool (Fcb); +} + + + +EFI_STATUS +VolumeOpen ( + IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This, + OUT EFI_FILE **Root + ) +{ + SEMIHOST_FCB *RootFcb = NULL; + + if (Root == NULL) { + return EFI_INVALID_PARAMETER; + } + + RootFcb = AllocateFCB (); + if (RootFcb == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + RootFcb->IsRoot = TRUE; + RootFcb->Info.Attribute = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY; + + InsertTailList (&gFileList, &RootFcb->Link); + + *Root = &RootFcb->File; + + return EFI_SUCCESS; +} + +/** + Open a file on the host system by means of the semihosting interface. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is + the file handle to source location. + @param[out] NewHandle A pointer to the location to return the opened + handle for the new file. + @param[in] FileName The Null-terminated string of the name of the file + to be opened. + @param[in] OpenMode The mode to open the file : Read or Read/Write or + Read/Write/Create + @param[in] Attributes Only valid for EFI_FILE_MODE_CREATE, in which case these + are the attribute bits for the newly created file. The + mnemonics of the attribute bits are : EFI_FILE_READ_ONLY, + EFI_FILE_HIDDEN, EFI_FILE_SYSTEM, EFI_FILE_RESERVED, + EFI_FILE_DIRECTORY and EFI_FILE_ARCHIVE. + + @retval EFI_SUCCESS The file was open. + @retval EFI_NOT_FOUND The specified file could not be found. + @retval EFI_DEVICE_ERROR The last issued semi-hosting operation failed. + @retval EFI_WRITE_PROTECTED Attempt to create a directory. This is not possible + with the semi-hosting interface. + @retval EFI_OUT_OF_RESOURCES Not enough resources were available to open the file. + @retval EFI_INVALID_PARAMETER At least one of the parameters is invalid. + +**/ +EFI_STATUS +FileOpen ( + IN EFI_FILE *This, + OUT EFI_FILE **NewHandle, + IN CHAR16 *FileName, + IN UINT64 OpenMode, + IN UINT64 Attributes + ) +{ + SEMIHOST_FCB *FileFcb; + RETURN_STATUS Return; + EFI_STATUS Status; + UINTN SemihostHandle; + CHAR8 *AsciiFileName; + UINT32 SemihostMode; + UINTN Length; + + if ((FileName == NULL) || (NewHandle == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if ( (OpenMode != EFI_FILE_MODE_READ) && + (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE)) && + (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE)) ) { + return EFI_INVALID_PARAMETER; + } + + if ((OpenMode & EFI_FILE_MODE_CREATE) && + (Attributes & EFI_FILE_DIRECTORY) ) { + return EFI_WRITE_PROTECTED; + } + + Length = StrLen (FileName) + 1; + AsciiFileName = AllocatePool (Length); + if (AsciiFileName == NULL) { + return EFI_OUT_OF_RESOURCES; + } + UnicodeStrToAsciiStrS (FileName, AsciiFileName, Length); + + // Opening '/', '\', '.', or the NULL pathname is trying to open the root directory + if ((AsciiStrCmp (AsciiFileName, "\\") == 0) || + (AsciiStrCmp (AsciiFileName, "/") == 0) || + (AsciiStrCmp (AsciiFileName, "") == 0) || + (AsciiStrCmp (AsciiFileName, ".") == 0) ) { + FreePool (AsciiFileName); + return (VolumeOpen (&gSemihostFs, NewHandle)); + } + + // + // No control is done here concerning the file path. It is passed + // as it is to the host operating system through the semi-hosting + // interface. We first try to open the file in the read or update + // mode even if the file creation has been asked for. That way, if + // the file already exists, it is not truncated to zero length. In + // write mode (bit SEMIHOST_FILE_MODE_WRITE up), if the file already + // exists, it is reset to an empty file. + // + if (OpenMode == EFI_FILE_MODE_READ) { + SemihostMode = SEMIHOST_FILE_MODE_READ | SEMIHOST_FILE_MODE_BINARY; + } else { + SemihostMode = SEMIHOST_FILE_MODE_READ | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE; + } + Return = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle); + + if (RETURN_ERROR (Return)) { + if (OpenMode & EFI_FILE_MODE_CREATE) { + // + // In the create if does not exist case, if the opening in update + // mode failed, create it and open it in update mode. The update + // mode allows for both read and write from and to the file. + // + Return = SemihostFileOpen ( + AsciiFileName, + SEMIHOST_FILE_MODE_WRITE | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE, + &SemihostHandle + ); + if (RETURN_ERROR (Return)) { + Status = EFI_DEVICE_ERROR; + goto Error; + } + } else { + Status = EFI_NOT_FOUND; + goto Error; + } + } + + // Allocate a control block and fill it + FileFcb = AllocateFCB (); + if (FileFcb == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto Error; + } + + FileFcb->FileName = AsciiFileName; + FileFcb->SemihostHandle = SemihostHandle; + FileFcb->Position = 0; + FileFcb->IsRoot = 0; + FileFcb->OpenMode = OpenMode; + + Return = SemihostFileLength (SemihostHandle, &Length); + if (RETURN_ERROR (Return)) { + Status = EFI_DEVICE_ERROR; + FreeFCB (FileFcb); + goto Error; + } + + FileFcb->Info.FileSize = Length; + FileFcb->Info.PhysicalSize = Length; + FileFcb->Info.Attribute = (OpenMode & EFI_FILE_MODE_CREATE) ? Attributes : 0; + + InsertTailList (&gFileList, &FileFcb->Link); + + *NewHandle = &FileFcb->File; + + return EFI_SUCCESS; + +Error: + + FreePool (AsciiFileName); + + return Status; +} + +/** + Worker function that truncate a file specified by its name to a given size. + + @param[in] FileName The Null-terminated string of the name of the file to be opened. + @param[in] Size The target size for the file. + + @retval EFI_SUCCESS The file was truncated. + @retval EFI_DEVICE_ERROR The last issued semi-hosting operation failed. + +**/ +STATIC +EFI_STATUS +TruncateFile ( + IN CHAR8 *FileName, + IN UINTN Size + ) +{ + EFI_STATUS Status; + RETURN_STATUS Return; + UINTN FileHandle; + UINT8 *Buffer; + UINTN Remaining; + UINTN Read; + UINTN ToRead; + + Status = EFI_DEVICE_ERROR; + FileHandle = 0; + Buffer = NULL; + + Return = SemihostFileOpen ( + FileName, + SEMIHOST_FILE_MODE_READ | SEMIHOST_FILE_MODE_BINARY, + &FileHandle + ); + if (RETURN_ERROR (Return)) { + goto Error; + } + + Buffer = AllocatePool (Size); + if (Buffer == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto Error; + } + + Read = 0; + Remaining = Size; + while (Remaining > 0) { + ToRead = Remaining; + Return = SemihostFileRead (FileHandle, &ToRead, Buffer + Read); + if (RETURN_ERROR (Return)) { + goto Error; + } + Remaining -= ToRead; + Read += ToRead; + } + + Return = SemihostFileClose (FileHandle); + FileHandle = 0; + if (RETURN_ERROR (Return)) { + goto Error; + } + + Return = SemihostFileOpen ( + FileName, + SEMIHOST_FILE_MODE_WRITE | SEMIHOST_FILE_MODE_BINARY, + &FileHandle + ); + if (RETURN_ERROR (Return)) { + goto Error; + } + + if (Size > 0) { + Return = SemihostFileWrite (FileHandle, &Size, Buffer); + if (RETURN_ERROR (Return)) { + goto Error; + } + } + + Status = EFI_SUCCESS; + +Error: + + if (FileHandle != 0) { + SemihostFileClose (FileHandle); + } + if (Buffer != NULL) { + FreePool (Buffer); + } + + return (Status); + +} + +/** + Close a specified file handle. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to close. + + @retval EFI_SUCCESS The file was closed. + @retval EFI_INVALID_PARAMETER The parameter "This" is NULL. + +**/ +EFI_STATUS +FileClose ( + IN EFI_FILE *This + ) +{ + SEMIHOST_FCB *Fcb; + + if (This == NULL) { + return EFI_INVALID_PARAMETER; + } + + Fcb = SEMIHOST_FCB_FROM_THIS(This); + + if (!Fcb->IsRoot) { + SemihostFileClose (Fcb->SemihostHandle); + // + // The file size might have been reduced from its actual + // size on the host file system with FileSetInfo(). In + // that case, the file has to be truncated. + // + if (Fcb->Info.FileSize < Fcb->Info.PhysicalSize) { + TruncateFile (Fcb->FileName, Fcb->Info.FileSize); + } + FreePool (Fcb->FileName); + } + + FreeFCB (Fcb); + + return EFI_SUCCESS; +} + +/** + Close and delete a file. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to delete. + + @retval EFI_SUCCESS The file was closed and deleted. + @retval EFI_WARN_DELETE_FAILURE The handle was closed, but the file was not deleted. + @retval EFI_INVALID_PARAMETER The parameter "This" is NULL. + +**/ +EFI_STATUS +FileDelete ( + IN EFI_FILE *This + ) +{ + SEMIHOST_FCB *Fcb; + RETURN_STATUS Return; + CHAR8 *FileName; + UINTN NameSize; + + if (This == NULL) { + return EFI_INVALID_PARAMETER; + } + + Fcb = SEMIHOST_FCB_FROM_THIS (This); + + if (!Fcb->IsRoot) { + // Get the filename from the Fcb + NameSize = AsciiStrLen (Fcb->FileName); + FileName = AllocatePool (NameSize + 1); + + AsciiStrCpyS (FileName, NameSize + 1, Fcb->FileName); + + // Close the file if it's open. Disregard return status, + // since it might give an error if the file isn't open. + This->Close (This); + + // Call the semihost interface to delete the file. + Return = SemihostFileRemove (FileName); + if (RETURN_ERROR (Return)) { + return EFI_WARN_DELETE_FAILURE; + } + return EFI_SUCCESS; + } else { + return EFI_WARN_DELETE_FAILURE; + } +} + +/** + Read data from an open file. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that + is the file handle to read data from. + @param[in out] BufferSize On input, the size of the Buffer. On output, the + amount of data returned in Buffer. In both cases, + the size is measured in bytes. + @param[out] Buffer The buffer into which the data is read. + + @retval EFI_SUCCESS The data was read. + @retval EFI_DEVICE_ERROR On entry, the current file position is + beyond the end of the file, or the semi-hosting + interface reported an error while performing the + read operation. + @retval EFI_INVALID_PARAMETER At least one of the three input pointers is NULL. + +**/ +EFI_STATUS +FileRead ( + IN EFI_FILE *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ) +{ + SEMIHOST_FCB *Fcb; + EFI_STATUS Status; + RETURN_STATUS Return; + + if ((This == NULL) || (BufferSize == NULL) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Fcb = SEMIHOST_FCB_FROM_THIS (This); + + if (Fcb->IsRoot) { + // The semi-hosting interface does not allow to list files on the host machine. + Status = EFI_UNSUPPORTED; + } else { + Status = EFI_SUCCESS; + if (Fcb->Position >= Fcb->Info.FileSize) { + *BufferSize = 0; + if (Fcb->Position > Fcb->Info.FileSize) { + Status = EFI_DEVICE_ERROR; + } + } else { + Return = SemihostFileRead (Fcb->SemihostHandle, BufferSize, Buffer); + if (RETURN_ERROR (Return)) { + Status = EFI_DEVICE_ERROR; + } else { + Fcb->Position += *BufferSize; + } + } + } + + return Status; +} + +/** + Worker function that extends the size of an open file. + + The extension is filled with zeros. + + @param[in] Fcb Internal description of the opened file + @param[in] Size The number of bytes, the file has to be extended. + + @retval EFI_SUCCESS The file was extended. + @retval EFI_DEVICE_ERROR The last issued semi-hosting operation failed. + +**/ +STATIC +EFI_STATUS +ExtendFile ( + IN SEMIHOST_FCB *Fcb, + IN UINTN Size + ) +{ + RETURN_STATUS Return; + UINTN Remaining; + CHAR8 WriteBuffer[128]; + UINTN WriteNb; + UINTN WriteSize; + + Return = SemihostFileSeek (Fcb->SemihostHandle, Fcb->Info.FileSize); + if (RETURN_ERROR (Return)) { + return EFI_DEVICE_ERROR; + } + + Remaining = Size; + SetMem (WriteBuffer, 0, sizeof(WriteBuffer)); + while (Remaining > 0) { + WriteNb = MIN (Remaining, sizeof(WriteBuffer)); + WriteSize = WriteNb; + Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, WriteBuffer); + if (RETURN_ERROR (Return)) { + return EFI_DEVICE_ERROR; + } + Remaining -= WriteNb; + } + + return EFI_SUCCESS; +} + +/** + Write data to an open file. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that + is the file handle to write data to. + @param[in out] BufferSize On input, the size of the Buffer. On output, the + size of the data actually written. In both cases, + the size is measured in bytes. + @param[in] Buffer The buffer of data to write. + + @retval EFI_SUCCESS The data was written. + @retval EFI_ACCESS_DENIED Attempt to write into a read only file or + in a file opened in read only mode. + @retval EFI_DEVICE_ERROR The last issued semi-hosting operation failed. + @retval EFI_INVALID_PARAMETER At least one of the three input pointers is NULL. + +**/ +EFI_STATUS +FileWrite ( + IN EFI_FILE *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ) +{ + SEMIHOST_FCB *Fcb; + EFI_STATUS Status; + UINTN WriteSize; + RETURN_STATUS Return; + UINTN Length; + + if ((This == NULL) || (BufferSize == NULL) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Fcb = SEMIHOST_FCB_FROM_THIS (This); + + // We cannot write a read-only file + if ((Fcb->Info.Attribute & EFI_FILE_READ_ONLY) + || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE)) { + return EFI_ACCESS_DENIED; + } + + // + // If the position has been set past the end of the file, first grow the + // file from its current size "Fcb->Info.FileSize" to "Fcb->Position" + // size, filling the gap with zeros. + // + if (Fcb->Position > Fcb->Info.FileSize) { + Status = ExtendFile (Fcb, Fcb->Position - Fcb->Info.FileSize); + if (EFI_ERROR (Status)) { + return Status; + } + Fcb->Info.FileSize = Fcb->Position; + } + + WriteSize = *BufferSize; + Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, Buffer); + if (RETURN_ERROR (Return)) { + return EFI_DEVICE_ERROR; + } + + Fcb->Position += *BufferSize; + if (Fcb->Position > Fcb->Info.FileSize) { + Fcb->Info.FileSize = Fcb->Position; + } + + Return = SemihostFileLength (Fcb->SemihostHandle, &Length); + if (RETURN_ERROR (Return)) { + return EFI_DEVICE_ERROR; + } + Fcb->Info.PhysicalSize = Length; + + return EFI_SUCCESS; +} + +/** + Return a file's current position. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is + the file handle to get the current position on. + @param[out] Position The address to return the file's current position value. + + @retval EFI_SUCCESS The position was returned. + @retval EFI_INVALID_PARAMETER The parameter "This" or "Position" is NULL. + +**/ +EFI_STATUS +FileGetPosition ( + IN EFI_FILE *This, + OUT UINT64 *Position + ) +{ + SEMIHOST_FCB *Fcb; + + if ((This == NULL) || (Position == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Fcb = SEMIHOST_FCB_FROM_THIS(This); + + *Position = Fcb->Position; + + return EFI_SUCCESS; +} + +/** + Set a file's current position. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is + the file handle to set the requested position on. + @param[in] Position The byte position from the start of the file to set. + + @retval EFI_SUCCESS The position was set. + @retval EFI_DEVICE_ERROR The semi-hosting positionning operation failed. + @retval EFI_UNSUPPORTED The seek request for nonzero is not valid on open + directories. + @retval EFI_INVALID_PARAMETER The parameter "This" is NULL. + +**/ +EFI_STATUS +FileSetPosition ( + IN EFI_FILE *This, + IN UINT64 Position + ) +{ + SEMIHOST_FCB *Fcb; + RETURN_STATUS Return; + + if (This == NULL) { + return EFI_INVALID_PARAMETER; + } + + Fcb = SEMIHOST_FCB_FROM_THIS (This); + + if (Fcb->IsRoot) { + if (Position != 0) { + return EFI_UNSUPPORTED; + } + } + else { + // + // UEFI Spec section 12.5: + // "Seeking to position 0xFFFFFFFFFFFFFFFF causes the current position to + // be set to the end of the file." + // + if (Position == 0xFFFFFFFFFFFFFFFF) { + Position = Fcb->Info.FileSize; + } + Return = SemihostFileSeek (Fcb->SemihostHandle, MIN (Position, Fcb->Info.FileSize)); + if (RETURN_ERROR (Return)) { + return EFI_DEVICE_ERROR; + } + } + + Fcb->Position = Position; + + return EFI_SUCCESS; +} + +/** + Return information about a file. + + @param[in] Fcb A pointer to the description of an open file. + @param[in out] BufferSize The size, in bytes, of Buffer. + @param[out] Buffer A pointer to the data buffer to return. Not NULL if + "*BufferSize" is greater than 0. + + @retval EFI_SUCCESS The information was returned. + @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to return the information. + BufferSize has been updated with the size needed to + complete the request. +**/ +STATIC +EFI_STATUS +GetFileInfo ( + IN SEMIHOST_FCB *Fcb, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ) +{ + EFI_FILE_INFO *Info = NULL; + UINTN NameSize = 0; + UINTN ResultSize; + UINTN Index; + + if (Fcb->IsRoot == TRUE) { + ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof(CHAR16); + } else { + NameSize = AsciiStrLen (Fcb->FileName) + 1; + ResultSize = SIZE_OF_EFI_FILE_INFO + NameSize * sizeof (CHAR16); + } + + if (*BufferSize < ResultSize) { + *BufferSize = ResultSize; + return EFI_BUFFER_TOO_SMALL; + } + + Info = Buffer; + + // Copy the current file info + CopyMem (Info, &Fcb->Info, SIZE_OF_EFI_FILE_INFO); + + // Fill in the structure + Info->Size = ResultSize; + + if (Fcb->IsRoot == TRUE) { + Info->FileName[0] = L'\0'; + } else { + for (Index = 0; Index < NameSize; Index++) { + Info->FileName[Index] = Fcb->FileName[Index]; + } + } + + *BufferSize = ResultSize; + + return EFI_SUCCESS; +} + +/** + Return information about a file system. + + @param[in] Fcb A pointer to the description of an open file + which belongs to the file system, the information + is requested for. + @param[in out] BufferSize The size, in bytes, of Buffer. + @param[out] Buffer A pointer to the data buffer to return. Not NULL if + "*BufferSize" is greater than 0. + + @retval EFI_SUCCESS The information was returned. + @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to return the information. + BufferSize has been updated with the size needed to + complete the request. + +**/ +STATIC +EFI_STATUS +GetFilesystemInfo ( + IN SEMIHOST_FCB *Fcb, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ) +{ + EFI_FILE_SYSTEM_INFO *Info; + EFI_STATUS Status; + UINTN ResultSize; + UINTN StringSize; + + StringSize = StrSize (mSemihostFsLabel); + ResultSize = SIZE_OF_EFI_FILE_SYSTEM_INFO + StringSize; + + if (*BufferSize >= ResultSize) { + ZeroMem (Buffer, ResultSize); + Status = EFI_SUCCESS; + + Info = Buffer; + + Info->Size = ResultSize; + Info->ReadOnly = FALSE; + Info->VolumeSize = 0; + Info->FreeSpace = 0; + Info->BlockSize = 0; + + CopyMem (Info->VolumeLabel, mSemihostFsLabel, StringSize); + } else { + Status = EFI_BUFFER_TOO_SMALL; + } + + *BufferSize = ResultSize; + return Status; +} + +/** + Return information about a file or a file system. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that + is the file handle the requested information is for. + @param[in] InformationType The type identifier for the information being requested : + EFI_FILE_INFO_ID or EFI_FILE_SYSTEM_INFO_ID or + EFI_FILE_SYSTEM_VOLUME_LABEL_ID + @param[in out] BufferSize The size, in bytes, of Buffer. + @param[out] Buffer A pointer to the data buffer to return. The type of the + data inside the buffer is indicated by InformationType. + + @retval EFI_SUCCESS The information was returned. + @retval EFI_UNSUPPORTED The InformationType is not known. + @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to return the information. + BufferSize has been updated with the size needed to + complete the request. + @retval EFI_INVALID_PARAMETER The parameter "This" or "InformationType" or "BufferSize" + is NULL or "Buffer" is NULL and "*Buffersize" is greater + than 0. + +**/ +EFI_STATUS +FileGetInfo ( + IN EFI_FILE *This, + IN EFI_GUID *InformationType, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ) +{ + SEMIHOST_FCB *Fcb; + EFI_STATUS Status; + UINTN ResultSize; + + if ((This == NULL) || + (InformationType == NULL) || + (BufferSize == NULL) || + ((Buffer == NULL) && (*BufferSize > 0)) ) { + return EFI_INVALID_PARAMETER; + } + + Fcb = SEMIHOST_FCB_FROM_THIS(This); + + if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) { + Status = GetFilesystemInfo (Fcb, BufferSize, Buffer); + } else if (CompareGuid (InformationType, &gEfiFileInfoGuid)) { + Status = GetFileInfo (Fcb, BufferSize, Buffer); + } else if (CompareGuid (InformationType, &gEfiFileSystemVolumeLabelInfoIdGuid)) { + ResultSize = StrSize (mSemihostFsLabel); + + if (*BufferSize >= ResultSize) { + CopyMem (Buffer, mSemihostFsLabel, ResultSize); + Status = EFI_SUCCESS; + } else { + Status = EFI_BUFFER_TOO_SMALL; + } + + *BufferSize = ResultSize; + } else { + Status = EFI_UNSUPPORTED; + } + + return Status; +} + +/** + Set information about a file. + + @param[in] Fcb A pointer to the description of the open file. + @param[in] Info A pointer to the file information to write. + + @retval EFI_SUCCESS The information was set. + @retval EFI_ACCESS_DENIED An attempt is made to change the name of a file + to a file that is already present. + @retval EFI_ACCESS_DENIED An attempt is being made to change the + EFI_FILE_DIRECTORY Attribute. + @retval EFI_ACCESS_DENIED The file is a read-only file or has been + opened in read-only mode and an attempt is + being made to modify a field other than + Attribute. + @retval EFI_WRITE_PROTECTED An attempt is being made to modify a + read-only attribute. + @retval EFI_DEVICE_ERROR The last issued semi-hosting operation failed. + @retval EFI_OUT_OF_RESOURCES A allocation needed to process the request failed. + +**/ +STATIC +EFI_STATUS +SetFileInfo ( + IN SEMIHOST_FCB *Fcb, + IN EFI_FILE_INFO *Info + ) +{ + EFI_STATUS Status; + RETURN_STATUS Return; + BOOLEAN FileSizeIsDifferent; + BOOLEAN FileNameIsDifferent; + BOOLEAN ReadOnlyIsDifferent; + CHAR8 *AsciiFileName; + UINTN FileSize; + UINTN Length; + UINTN SemihostHandle; + + // + // A directory can not be changed to a file and a file can + // not be changed to a directory. + // + if (((Info->Attribute & EFI_FILE_DIRECTORY) != 0) != Fcb->IsRoot) { + return EFI_ACCESS_DENIED; + } + + Length = StrLen (Info->FileName) + 1; + AsciiFileName = AllocatePool (Length); + if (AsciiFileName == NULL) { + return EFI_OUT_OF_RESOURCES; + } + UnicodeStrToAsciiStrS (Info->FileName, AsciiFileName, Length); + + FileSizeIsDifferent = (Info->FileSize != Fcb->Info.FileSize); + FileNameIsDifferent = (AsciiStrCmp (AsciiFileName, Fcb->FileName) != 0); + ReadOnlyIsDifferent = CompareMem ( + &Info->CreateTime, + &Fcb->Info.CreateTime, + 3 * sizeof (EFI_TIME) + ) != 0; + + // + // For a read-only file or a file opened in read-only mode, only + // the Attribute field can be modified. As the root directory is + // read-only (i.e. VolumeOpen()), this protects the root directory + // description. + // + if ((Fcb->OpenMode == EFI_FILE_MODE_READ) || + (Fcb->Info.Attribute & EFI_FILE_READ_ONLY) ) { + if (FileSizeIsDifferent || FileNameIsDifferent || ReadOnlyIsDifferent) { + Status = EFI_ACCESS_DENIED; + goto Error; + } + } + + if (ReadOnlyIsDifferent) { + Status = EFI_WRITE_PROTECTED; + goto Error; + } + + Status = EFI_DEVICE_ERROR; + + if (FileSizeIsDifferent) { + FileSize = Info->FileSize; + if (Fcb->Info.FileSize < FileSize) { + Status = ExtendFile (Fcb, FileSize - Fcb->Info.FileSize); + if (EFI_ERROR (Status)) { + goto Error; + } + // + // The read/write position from the host file system point of view + // is at the end of the file. If the position from this module + // point of view is smaller than the new file size, then + // ask the host file system to move to that position. + // + if (Fcb->Position < FileSize) { + FileSetPosition (&Fcb->File, Fcb->Position); + } + } + Fcb->Info.FileSize = FileSize; + + Return = SemihostFileLength (Fcb->SemihostHandle, &Length); + if (RETURN_ERROR (Return)) { + goto Error; + } + Fcb->Info.PhysicalSize = Length; + } + + // + // Note down in RAM the Attribute field but we can not ask + // for its modification to the host file system as the + // semi-host interface does not provide this feature. + // + Fcb->Info.Attribute = Info->Attribute; + + if (FileNameIsDifferent) { + Return = SemihostFileOpen ( + AsciiFileName, + SEMIHOST_FILE_MODE_READ | SEMIHOST_FILE_MODE_BINARY, + &SemihostHandle + ); + if (!RETURN_ERROR (Return)) { + SemihostFileClose (SemihostHandle); + Status = EFI_ACCESS_DENIED; + goto Error; + } + + Return = SemihostFileRename (Fcb->FileName, AsciiFileName); + if (RETURN_ERROR (Return)) { + goto Error; + } + FreePool (Fcb->FileName); + Fcb->FileName = AsciiFileName; + AsciiFileName = NULL; + } + + Status = EFI_SUCCESS; + +Error: + if (AsciiFileName != NULL) { + FreePool (AsciiFileName); + } + + return Status; +} + +/** + Set information about a file or a file system. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that + is the file handle the information is for. + @param[in] InformationType The type identifier for the information being set : + EFI_FILE_INFO_ID or EFI_FILE_SYSTEM_INFO_ID or + EFI_FILE_SYSTEM_VOLUME_LABEL_ID + @param[in] BufferSize The size, in bytes, of Buffer. + @param[in] Buffer A pointer to the data buffer to write. The type of the + data inside the buffer is indicated by InformationType. + + @retval EFI_SUCCESS The information was set. + @retval EFI_UNSUPPORTED The InformationType is not known. + @retval EFI_DEVICE_ERROR The last issued semi-hosting operation failed. + @retval EFI_ACCESS_DENIED An attempt is being made to change the + EFI_FILE_DIRECTORY Attribute. + @retval EFI_ACCESS_DENIED InformationType is EFI_FILE_INFO_ID and + the file is a read-only file or has been + opened in read-only mode and an attempt is + being made to modify a field other than + Attribute. + @retval EFI_ACCESS_DENIED An attempt is made to change the name of a file + to a file that is already present. + @retval EFI_WRITE_PROTECTED An attempt is being made to modify a + read-only attribute. + @retval EFI_BAD_BUFFER_SIZE The size of the buffer is lower than that indicated by + the data inside the buffer. + @retval EFI_OUT_OF_RESOURCES An allocation needed to process the request failed. + @retval EFI_INVALID_PARAMETER At least one of the parameters is invalid. + +**/ +EFI_STATUS +FileSetInfo ( + IN EFI_FILE *This, + IN EFI_GUID *InformationType, + IN UINTN BufferSize, + IN VOID *Buffer + ) +{ + SEMIHOST_FCB *Fcb; + EFI_FILE_INFO *Info; + EFI_FILE_SYSTEM_INFO *SystemInfo; + CHAR16 *VolumeLabel; + + if ((This == NULL) || (InformationType == NULL) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Fcb = SEMIHOST_FCB_FROM_THIS (This); + + if (CompareGuid (InformationType, &gEfiFileInfoGuid)) { + Info = Buffer; + if (Info->Size < (SIZE_OF_EFI_FILE_INFO + StrSize (Info->FileName))) { + return EFI_INVALID_PARAMETER; + } + if (BufferSize < Info->Size) { + return EFI_BAD_BUFFER_SIZE; + } + return SetFileInfo (Fcb, Info); + } else if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) { + SystemInfo = Buffer; + if (SystemInfo->Size < + (SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize (SystemInfo->VolumeLabel))) { + return EFI_INVALID_PARAMETER; + } + if (BufferSize < SystemInfo->Size) { + return EFI_BAD_BUFFER_SIZE; + } + Buffer = SystemInfo->VolumeLabel; + + if (StrSize (Buffer) > 0) { + VolumeLabel = AllocateCopyPool (StrSize (Buffer), Buffer); + if (VolumeLabel != NULL) { + FreePool (mSemihostFsLabel); + mSemihostFsLabel = VolumeLabel; + return EFI_SUCCESS; + } else { + return EFI_OUT_OF_RESOURCES; + } + } else { + return EFI_INVALID_PARAMETER; + } + } else if (!CompareGuid (InformationType, &gEfiFileSystemVolumeLabelInfoIdGuid)) { + return EFI_UNSUPPORTED; + } else { + return EFI_UNSUPPORTED; + } +} + +EFI_STATUS +FileFlush ( + IN EFI_FILE *File + ) +{ + SEMIHOST_FCB *Fcb; + + Fcb = SEMIHOST_FCB_FROM_THIS(File); + + if (Fcb->IsRoot) { + return EFI_SUCCESS; + } else { + if ((Fcb->Info.Attribute & EFI_FILE_READ_ONLY) + || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE)) { + return EFI_ACCESS_DENIED; + } else { + return EFI_SUCCESS; + } + } +} + +EFI_STATUS +SemihostFsEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = EFI_NOT_FOUND; + + if (SemihostConnectionSupported ()) { + mSemihostFsLabel = AllocateCopyPool (StrSize (DEFAULT_SEMIHOST_FS_LABEL), DEFAULT_SEMIHOST_FS_LABEL); + if (mSemihostFsLabel == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status = gBS->InstallMultipleProtocolInterfaces ( + &gInstallHandle, + &gEfiSimpleFileSystemProtocolGuid, &gSemihostFs, + &gEfiDevicePathProtocolGuid, &gDevicePath, + NULL + ); + + if (EFI_ERROR(Status)) { + FreePool (mSemihostFsLabel); + } + } + + return Status; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h new file mode 100644 index 00000000..93395743 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h @@ -0,0 +1,252 @@ +/** @file + Support a Semi Host file system over a debuggers JTAG + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SEMIHOST_FS_H__ +#define __SEMIHOST_FS_H__ + +EFI_STATUS +VolumeOpen ( + IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This, + OUT EFI_FILE **Root + ); + +/** + Open a file on the host system by means of the semihosting interface. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is + the file handle to source location. + @param[out] NewHandle A pointer to the location to return the opened + handle for the new file. + @param[in] FileName The Null-terminated string of the name of the file + to be opened. + @param[in] OpenMode The mode to open the file : Read or Read/Write or + Read/Write/Create + @param[in] Attributes Only valid for EFI_FILE_MODE_CREATE, in which case these + are the attribute bits for the newly created file. The + mnemonics of the attribute bits are : EFI_FILE_READ_ONLY, + EFI_FILE_HIDDEN, EFI_FILE_SYSTEM, EFI_FILE_RESERVED, + EFI_FILE_DIRECTORY and EFI_FILE_ARCHIVE. + + @retval EFI_SUCCESS The file was open. + @retval EFI_NOT_FOUND The specified file could not be found. + @retval EFI_DEVICE_ERROR The last issued semi-hosting operation failed. + @retval EFI_WRITE_PROTECTED Attempt to create a directory. This is not possible + with the semi-hosting interface. + @retval EFI_OUT_OF_RESOURCES Not enough resources were available to open the file. + @retval EFI_INVALID_PARAMETER At least one of the parameters is invalid. + +**/ +EFI_STATUS +FileOpen ( + IN EFI_FILE *This, + OUT EFI_FILE **NewHandle, + IN CHAR16 *FileName, + IN UINT64 OpenMode, + IN UINT64 Attributes + ); + +/** + Close a specified file handle. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to close. + + @retval EFI_SUCCESS The file was closed. + @retval EFI_INVALID_PARAMETER The parameter "This" is NULL. + +**/ +EFI_STATUS +FileClose ( + IN EFI_FILE *This + ); + +/** + Close and delete a file. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to delete. + + @retval EFI_SUCCESS The file was closed and deleted. + @retval EFI_WARN_DELETE_FAILURE The handle was closed, but the file was not deleted. + @retval EFI_INVALID_PARAMETER The parameter "This" is NULL. + +**/ +EFI_STATUS +FileDelete ( + IN EFI_FILE *This + ); + +/** + Read data from an open file. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that + is the file handle to read data from. + @param[in out] BufferSize On input, the size of the Buffer. On output, the + amount of data returned in Buffer. In both cases, + the size is measured in bytes. + @param[out] Buffer The buffer into which the data is read. + + @retval EFI_SUCCESS The data was read. + @retval EFI_DEVICE_ERROR On entry, the current file position is + beyond the end of the file, or the semi-hosting + interface reported an error while performing the + read operation. + @retval EFI_INVALID_PARAMETER The parameter "This" or the parameter "Buffer" + is NULL. +**/ +EFI_STATUS +FileRead ( + IN EFI_FILE *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + Write data to an open file. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that + is the file handle to write data to. + @param[in out] BufferSize On input, the size of the Buffer. On output, the + size of the data actually written. In both cases, + the size is measured in bytes. + @param[in] Buffer The buffer of data to write. + + @retval EFI_SUCCESS The data was written. + @retval EFI_ACCESS_DENIED Attempt to write into a read only file or + in a file opened in read only mode. + @retval EFI_DEVICE_ERROR The last issued semi-hosting operation failed. + @retval EFI_INVALID_PARAMETER The parameter "This" or the parameter "Buffer" + is NULL. + +**/ +EFI_STATUS +FileWrite ( + IN EFI_FILE *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ); + +/** + Return a file's current position. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is + the file handle to get the current position on. + @param[out] Position The address to return the file's current position value. + + @retval EFI_SUCCESS The position was returned. + @retval EFI_INVALID_PARAMETER Position is a NULL pointer. + +**/ +EFI_STATUS +FileGetPosition ( + IN EFI_FILE *File, + OUT UINT64 *Position + ); + +/** + Set a file's current position. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is + the file handle to set the requested position on. + @param[in] Position The byte position from the start of the file to set. + + @retval EFI_SUCCESS The position was set. + @retval EFI_DEVICE_ERROR The semi-hosting positionning operation failed. + @retval EFI_UNSUPPORTED The seek request for nonzero is not valid on open + directories. + +**/ +EFI_STATUS +FileSetPosition ( + IN EFI_FILE *File, + IN UINT64 Position + ); + +/** + Return information about a file or a file system. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that + is the file handle the requested information is for. + @param[in] InformationType The type identifier for the information being requested : + EFI_FILE_INFO_ID or EFI_FILE_SYSTEM_INFO_ID or + EFI_FILE_SYSTEM_VOLUME_LABEL_ID + @param[in out] BufferSize The size, in bytes, of Buffer. + @param[out] Buffer A pointer to the data buffer to return. The type of the + data inside the buffer is indicated by InformationType. + + @retval EFI_SUCCESS The information was returned. + @retval EFI_UNSUPPORTED The InformationType is not known. + @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to return the information. + BufferSize has been updated with the size needed to + complete the request. + @retval EFI_INVALID_PARAMETER The parameter "This" or the parameter "Buffer" + is NULL. + +**/ +EFI_STATUS +FileGetInfo ( + IN EFI_FILE *This, + IN EFI_GUID *InformationType, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + Set information about a file or a file system. + + @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that + is the file handle the information is for. + @param[in] InformationType The type identifier for the information being set : + EFI_FILE_INFO_ID or EFI_FILE_SYSTEM_INFO_ID or + EFI_FILE_SYSTEM_VOLUME_LABEL_ID + @param[in] BufferSize The size, in bytes, of Buffer. + @param[in] Buffer A pointer to the data buffer to write. The type of the + data inside the buffer is indicated by InformationType. + + @retval EFI_SUCCESS The information was set. + @retval EFI_UNSUPPORTED The InformationType is not known. + @retval EFI_DEVICE_ERROR The last issued semi-hosting operation failed. + @retval EFI_ACCESS_DENIED An attempt is being made to change the + EFI_FILE_DIRECTORY Attribute. + @retval EFI_ACCESS_DENIED InformationType is EFI_FILE_INFO_ID and + the file is a read-only file or has been + opened in read-only mode and an attempt is + being made to modify a field other than + Attribute. + @retval EFI_ACCESS_DENIED An attempt is made to change the name of a file + to a file that is already present. + @retval EFI_WRITE_PROTECTED An attempt is being made to modify a + read-only attribute. + @retval EFI_BAD_BUFFER_SIZE The size of the buffer is lower than that indicated by + the data inside the buffer. + @retval EFI_OUT_OF_RESOURCES An allocation needed to process the request failed. + @retval EFI_INVALID_PARAMETER At least one of the parameters is invalid. + +**/ +EFI_STATUS +FileSetInfo ( + IN EFI_FILE *This, + IN EFI_GUID *InformationType, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +EFI_STATUS +FileFlush ( + IN EFI_FILE *File + ); + +#endif // __SEMIHOST_FS_H__ + diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf new file mode 100644 index 00000000..164df2d8 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf @@ -0,0 +1,48 @@ +#/** @file +# Support a Semi Host file system over a debuggers JTAG +# +# Copyright (c) 2009, Apple Inc. All rights reserved.
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SemihostFs + FILE_GUID = C5B9C74A-6D72-4719-99AB-C59F199091EB + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = SemihostFsEntryPoint + +[Sources.ARM, Sources.AARCH64] + Arm/SemihostFs.c + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + BaseLib + MemoryAllocationLib + SemihostLib + UefiDriverEntryPoint + UefiLib + +[Guids] + gEfiFileSystemInfoGuid + gEfiFileInfoGuid + gEfiFileSystemVolumeLabelInfoIdGuid + +[Protocols] + gEfiSimpleFileSystemProtocolGuid + gEfiDevicePathProtocolGuid + diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroExport.inc b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroExport.inc new file mode 100644 index 00000000..818d6b2c --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroExport.inc @@ -0,0 +1,29 @@ +;%HEADER% +;/** @file +; Macros to centralize the EXPORT, AREA, and definition of an assembly +; function. The AREA prefix is required to put the function in its own +; section so that removal of unused functions in the final link is performed. +; This provides equivalent functionality to the compiler's --split-sections +; option. +; +; Copyright (c) 2015 HP Development Company, L.P. +; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;**/ + + + MACRO + RVCT_ASM_EXPORT $func + EXPORT $func + AREA s_$func, CODE, READONLY +$func + MEND + + END diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroIoLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroIoLib.h new file mode 100644 index 00000000..16d2a307 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroIoLib.h @@ -0,0 +1,45 @@ +/** @file + Macros to work around lack of Apple support for LDR register, =expr + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +#ifndef __MACRO_IO_LIB_H__ +#define __MACRO_IO_LIB_H__ + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + .p2align 2 ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) + +#define MOV32(Reg, Val) \ + movw Reg, #(Val) & 0xffff ; \ + movt Reg, #(Val) >> 16 + +#define ADRL(Reg, Sym) \ + movw Reg, #:lower16:(Sym) - (. + 16) ; \ + movt Reg, #:upper16:(Sym) - (. + 12) ; \ + add Reg, Reg, pc + +#define LDRL(Reg, Sym) \ + movw Reg, #:lower16:(Sym) - (. + 16) ; \ + movt Reg, #:upper16:(Sym) - (. + 12) ; \ + ldr Reg, [pc, Reg] + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroIoLib.inc b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroIoLib.inc new file mode 100644 index 00000000..ce7a1488 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroIoLib.inc @@ -0,0 +1,39 @@ +;%HEADER% +;/** @file +; Macros to work around lack of Apple support for LDR register, =expr +; +; Copyright (c) 2009, Apple Inc. All rights reserved.
+; Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;**/ + + + MACRO + adrll $Reg, $Symbol + add $Reg, pc, #-8 + RELOC R_ARM_ALU_PC_G0_NC, $Symbol + add $Reg, $Reg, #-4 + RELOC R_ARM_ALU_PC_G1_NC, $Symbol + add $Reg, $Reg, #0 + RELOC R_ARM_ALU_PC_G2, $Symbol + MEND + + MACRO + ldrl $Reg, $Symbol + add $Reg, pc, #-8 + RELOC R_ARM_ALU_PC_G0_NC, $Symbol + add $Reg, $Reg, #-4 + RELOC R_ARM_ALU_PC_G1_NC, $Symbol + ldr $Reg, [$Reg, #0] + RELOC R_ARM_LDR_PC_G2, $Symbol + MEND + + END diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroIoLibV8.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroIoLibV8.h new file mode 100644 index 00000000..db43d3b5 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/AsmMacroIoLibV8.h @@ -0,0 +1,63 @@ +/** @file + Macros to work around lack of Clang support for LDR register, =expr + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +#ifndef __MACRO_IO_LIBV8_H__ +#define __MACRO_IO_LIBV8_H__ + +// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1 +// This only selects between EL1 and EL2, else we die. +// Provide the Macro with a safe temp xreg to use. +#define EL1_OR_EL2(SAFE_XREG) \ + mrs SAFE_XREG, CurrentEL ;\ + cmp SAFE_XREG, #0x8 ;\ + b.gt . ;\ + b.eq 2f ;\ + cbnz SAFE_XREG, 1f ;\ + b . ;// We should never get here + + +// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1 +// This only selects between EL1 and EL2 and EL3, else we die. +// Provide the Macro with a safe temp xreg to use. +#define EL1_OR_EL2_OR_EL3(SAFE_XREG) \ + mrs SAFE_XREG, CurrentEL ;\ + cmp SAFE_XREG, #0x8 ;\ + b.gt 3f ;\ + b.eq 2f ;\ + cbnz SAFE_XREG, 1f ;\ + b . ;// We should never get here + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) + +#define MOV32(Reg, Val) \ + movz Reg, (Val) >> 16, lsl #16 ; \ + movk Reg, (Val) & 0xffff + +#define MOV64(Reg, Val) \ + movz Reg, (Val) >> 48, lsl #48 ; \ + movk Reg, ((Val) >> 32) & 0xffff, lsl #32 ; \ + movk Reg, ((Val) >> 16) & 0xffff, lsl #16 ; \ + movk Reg, (Val) & 0xffff + +#endif // __MACRO_IO_LIBV8_H__ diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/AArch64.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/AArch64.h new file mode 100644 index 00000000..cebfc5da --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/AArch64.h @@ -0,0 +1,238 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __AARCH64_H__ +#define __AARCH64_H__ + +#include + +// ARM Interrupt ID in Exception Table +#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ + +// CPACR - Coprocessor Access Control Register definitions +#define CPACR_TTA_EN (1UL << 28) +#define CPACR_FPEN_EL1 (1UL << 20) +#define CPACR_FPEN_FULL (3UL << 20) +#define CPACR_CP_FULL_ACCESS 0x300000 + +// Coprocessor Trap Register (CPTR) +#define AARCH64_CPTR_TFP (1 << 10) + +// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions +#define AARCH64_PFR0_FP (0xF << 16) +#define AARCH64_PFR0_GIC (0xF << 24) + +// SCR - Secure Configuration Register definitions +#define SCR_NS (1 << 0) +#define SCR_IRQ (1 << 1) +#define SCR_FIQ (1 << 2) +#define SCR_EA (1 << 3) +#define SCR_FW (1 << 4) +#define SCR_AW (1 << 5) + +// MIDR - Main ID Register definitions +#define ARM_CPU_TYPE_SHIFT 4 +#define ARM_CPU_TYPE_MASK 0xFFF +#define ARM_CPU_TYPE_AEMv8 0xD0F +#define ARM_CPU_TYPE_A53 0xD03 +#define ARM_CPU_TYPE_A57 0xD07 +#define ARM_CPU_TYPE_A72 0xD08 +#define ARM_CPU_TYPE_A15 0xC0F +#define ARM_CPU_TYPE_A9 0xC09 +#define ARM_CPU_TYPE_A7 0xC07 +#define ARM_CPU_TYPE_A5 0xC05 + +#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) ) +#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF)) + +// Hypervisor Configuration Register +#define ARM_HCR_FMO BIT3 +#define ARM_HCR_IMO BIT4 +#define ARM_HCR_AMO BIT5 +#define ARM_HCR_TSC BIT19 +#define ARM_HCR_TGE BIT27 + +// Exception Syndrome Register +#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr)) +#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr)) + +#define AARCH64_ESR_EC_SMC32 (0x13 << 26) +#define AARCH64_ESR_EC_SMC64 (0x17 << 26) + +// AArch64 Exception Level +#define AARCH64_EL3 0xC +#define AARCH64_EL2 0x8 +#define AARCH64_EL1 0x4 + +// Saved Program Status Register definitions +#define SPSR_A BIT8 +#define SPSR_I BIT7 +#define SPSR_F BIT6 + +#define SPSR_AARCH32 BIT4 + +#define SPSR_AARCH32_MODE_USER 0x0 +#define SPSR_AARCH32_MODE_FIQ 0x1 +#define SPSR_AARCH32_MODE_IRQ 0x2 +#define SPSR_AARCH32_MODE_SVC 0x3 +#define SPSR_AARCH32_MODE_ABORT 0x7 +#define SPSR_AARCH32_MODE_UNDEF 0xB +#define SPSR_AARCH32_MODE_SYS 0xF + +// Counter-timer Hypervisor Control register definitions +#define CNTHCTL_EL2_EL1PCTEN BIT0 +#define CNTHCTL_EL2_EL1PCEN BIT1 + +#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1) + +// Vector table offset definitions +#define ARM_VECTOR_CUR_SP0_SYNC 0x000 +#define ARM_VECTOR_CUR_SP0_IRQ 0x080 +#define ARM_VECTOR_CUR_SP0_FIQ 0x100 +#define ARM_VECTOR_CUR_SP0_SERR 0x180 + +#define ARM_VECTOR_CUR_SPx_SYNC 0x200 +#define ARM_VECTOR_CUR_SPx_IRQ 0x280 +#define ARM_VECTOR_CUR_SPx_FIQ 0x300 +#define ARM_VECTOR_CUR_SPx_SERR 0x380 + +#define ARM_VECTOR_LOW_A64_SYNC 0x400 +#define ARM_VECTOR_LOW_A64_IRQ 0x480 +#define ARM_VECTOR_LOW_A64_FIQ 0x500 +#define ARM_VECTOR_LOW_A64_SERR 0x580 + +#define ARM_VECTOR_LOW_A32_SYNC 0x600 +#define ARM_VECTOR_LOW_A32_IRQ 0x680 +#define ARM_VECTOR_LOW_A32_FIQ 0x700 +#define ARM_VECTOR_LOW_A32_SERR 0x780 + +#define VECTOR_BASE(tbl) \ + .section .text.##tbl##,"ax"; \ + .align 11; \ + .org 0x0; \ + GCC_ASM_EXPORT(tbl); \ + ASM_PFX(tbl): \ + +#define VECTOR_ENTRY(tbl, off) \ + .org off + +#define VECTOR_END(tbl) \ + .org 0x800; \ + .previous + +VOID +EFIAPI +ArmEnableSWPInstruction ( + VOID + ); + +UINTN +EFIAPI +ArmReadCbar ( + VOID + ); + +UINTN +EFIAPI +ArmReadTpidrurw ( + VOID + ); + +VOID +EFIAPI +ArmWriteTpidrurw ( + UINTN Value + ); + +UINTN +EFIAPI +ArmGetTCR ( + VOID + ); + +VOID +EFIAPI +ArmSetTCR ( + UINTN Value + ); + +UINTN +EFIAPI +ArmGetMAIR ( + VOID + ); + +VOID +EFIAPI +ArmSetMAIR ( + UINTN Value + ); + +VOID +EFIAPI +ArmDisableAlignmentCheck ( + VOID + ); + +VOID +EFIAPI +ArmEnableAlignmentCheck ( + VOID + ); + +VOID +EFIAPI +ArmDisableStackAlignmentCheck ( + VOID + ); + +VOID +EFIAPI +ArmEnableStackAlignmentCheck ( + VOID + ); + +VOID +EFIAPI +ArmDisableAllExceptions ( + VOID + ); + +VOID +ArmWriteHcr ( + IN UINTN Hcr + ); + +UINTN +ArmReadHcr ( + VOID + ); + +UINTN +ArmReadCurrentEL ( + VOID + ); + +UINT64 +PageAttributeToGcdAttribute ( + IN UINT64 PageAttributes + ); + +UINTN +ArmWriteCptr ( + IN UINT64 Cptr + ); + +#endif // __AARCH64_H__ diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h new file mode 100644 index 00000000..ff77b16b --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h @@ -0,0 +1,204 @@ +/** @file +* +* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __AARCH64_MMU_H_ +#define __AARCH64_MMU_H_ + +// +// Memory Attribute Indirection register Definitions +// +#define MAIR_ATTR_DEVICE_MEMORY 0x0ULL +#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL +#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL +#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL + +#define MAIR_ATTR(n,value) ((value) << (((n) >> 2)*8)) + +// +// Long-descriptor Translation Table format +// + +// Return the smallest offset from the table level. +// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0 +#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9)) + +#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level)) + +// Get the associated entry in the given Translation Table +#define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \ + ((UINTN)(TranslationTable) + ((((UINTN)(Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64))) + +// Return the smallest address granularity from the table level. +// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0 +#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel)) + +#define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \ + ((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64)))) + +// There are 512 entries per table when 4K Granularity +#define TT_ENTRY_COUNT 512 +#define TT_ALIGNMENT_BLOCK_ENTRY BIT12 +#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12 + +#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12) +#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12) + +#define TT_TYPE_MASK 0x3 +#define TT_TYPE_TABLE_ENTRY 0x3 +#define TT_TYPE_BLOCK_ENTRY 0x1 +#define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3 + +#define TT_ATTR_INDX_MASK (0x7 << 2) +#define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2) +#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2) +#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2) +#define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2) + +#define TT_AP_MASK (0x3UL << 6) +#define TT_AP_NO_RW (0x0UL << 6) +#define TT_AP_RW_RW (0x1UL << 6) +#define TT_AP_NO_RO (0x2UL << 6) +#define TT_AP_RO_RO (0x3UL << 6) + +#define TT_NS BIT5 +#define TT_AF BIT10 + +#define TT_SH_NON_SHAREABLE (0x0 << 8) +#define TT_SH_OUTER_SHAREABLE (0x2 << 8) +#define TT_SH_INNER_SHAREABLE (0x3 << 8) +#define TT_SH_MASK (0x3 << 8) + +#define TT_PXN_MASK BIT53 +#define TT_UXN_MASK BIT54 // EL1&0 +#define TT_XN_MASK BIT54 // EL2 / EL3 + +#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2)) + +#define TT_TABLE_PXN BIT59 +#define TT_TABLE_UXN BIT60 // EL1&0 +#define TT_TABLE_XN BIT60 // EL2 / EL3 +#define TT_TABLE_NS BIT63 + +#define TT_TABLE_AP_MASK (BIT62 | BIT61) +#define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61) +#define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61) +#define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61) + +// +// Translation Control Register +// +#define TCR_T0SZ_MASK 0x3FUL + +#define TCR_PS_4GB (0UL << 16) +#define TCR_PS_64GB (1UL << 16) +#define TCR_PS_1TB (2UL << 16) +#define TCR_PS_4TB (3UL << 16) +#define TCR_PS_16TB (4UL << 16) +#define TCR_PS_256TB (5UL << 16) + +#define TCR_TG0_4KB (0UL << 14) +#define TCR_TG1_4KB (2UL << 30) + +#define TCR_IPS_4GB (0ULL << 32) +#define TCR_IPS_64GB (1ULL << 32) +#define TCR_IPS_1TB (2ULL << 32) +#define TCR_IPS_4TB (3ULL << 32) +#define TCR_IPS_16TB (4ULL << 32) +#define TCR_IPS_256TB (5ULL << 32) + +#define TCR_EPD1 (1UL << 23) + +#define TTBR_ASID_FIELD (48) +#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD) +#define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits + +#define TCR_EL1_T0SZ_FIELD (0) +#define TCR_EL1_EPD0_FIELD (7) +#define TCR_EL1_IRGN0_FIELD (8) +#define TCR_EL1_ORGN0_FIELD (10) +#define TCR_EL1_SH0_FIELD (12) +#define TCR_EL1_TG0_FIELD (14) +#define TCR_EL1_T1SZ_FIELD (16) +#define TCR_EL1_A1_FIELD (22) +#define TCR_EL1_EPD1_FIELD (23) +#define TCR_EL1_IRGN1_FIELD (24) +#define TCR_EL1_ORGN1_FIELD (26) +#define TCR_EL1_SH1_FIELD (28) +#define TCR_EL1_TG1_FIELD (30) +#define TCR_EL1_IPS_FIELD (32) +#define TCR_EL1_AS_FIELD (36) +#define TCR_EL1_TBI0_FIELD (37) +#define TCR_EL1_TBI1_FIELD (38) +#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD) +#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD) +#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD) +#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD) +#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD) +#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD) +#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD) +#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD) +#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD) +#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD) +#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD) +#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD) +#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD) +#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD) +#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD) +#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD) +#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD) + + +#define TCR_EL23_T0SZ_FIELD (0) +#define TCR_EL23_IRGN0_FIELD (8) +#define TCR_EL23_ORGN0_FIELD (10) +#define TCR_EL23_SH0_FIELD (12) +#define TCR_EL23_TG0_FIELD (14) +#define TCR_EL23_PS_FIELD (16) +#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD) +#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD) +#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD) +#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD) +#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD) +#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD) + + +#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10) +#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10) +#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10) +#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10) + +#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8) +#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8) +#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8) +#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8) + +#define TCR_SH_NON_SHAREABLE (0x0UL << 12) +#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12) +#define TCR_SH_INNER_SHAREABLE (0x3UL << 12) + +#define TCR_PASZ_32BITS_4GB (0x0UL) +#define TCR_PASZ_36BITS_64GB (0x1UL) +#define TCR_PASZ_40BITS_1TB (0x2UL) +#define TCR_PASZ_42BITS_4TB (0x3UL) +#define TCR_PASZ_44BITS_16TB (0x4UL) +#define TCR_PASZ_48BITS_256TB (0x5UL) + +// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit +// Virtual address range for 512GB of virtual space sets T*SZ to 25 +#define INPUT_ADDRESS_SIZE_TO_TxSZ(a) (64 - a) + +// Uses LPAE Page Table format + +#endif // __AARCH64_MMU_H_ + diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmCortexA5x.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmCortexA5x.h new file mode 100644 index 00000000..ba3d5197 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmCortexA5x.h @@ -0,0 +1,50 @@ +/** @file + + Copyright (c) 2012-2014, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ARM_CORTEX_A5x_H__ +#define __ARM_CORTEX_A5x_H__ + +// +// Cortex A5x feature bit definitions +// +#define A5X_FEATURE_SMP (1 << 6) + +// +// Helper functions to access CPU Extended Control Register +// +UINT64 +EFIAPI +ArmReadCpuExCr ( + VOID + ); + +VOID +EFIAPI +ArmWriteCpuExCr ( + IN UINT64 Val + ); + +VOID +EFIAPI +ArmSetCpuExCrBit ( + IN UINT64 Bits + ); + +VOID +EFIAPI +ArmUnsetCpuExCrBit ( + IN UINT64 Bits + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmCortexA9.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmCortexA9.h new file mode 100644 index 00000000..af9a3007 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmCortexA9.h @@ -0,0 +1,65 @@ +/** @file + + Copyright (c) 2011, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ARM_CORTEX_A9_H__ +#define __ARM_CORTEX_A9_H__ + +#include + +// +// Cortex A9 feature bit definitions +// +#define A9_FEATURE_PARITY (1<<9) +#define A9_FEATURE_AOW (1<<8) +#define A9_FEATURE_EXCL (1<<7) +#define A9_FEATURE_SMP (1<<6) +#define A9_FEATURE_FOZ (1<<3) +#define A9_FEATURE_DPREF (1<<2) +#define A9_FEATURE_HINT (1<<1) +#define A9_FEATURE_FWD (1<<0) + +// +// Cortex A9 Watchdog +// +#define ARM_A9_WATCHDOG_REGION 0x600 + +#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20 +#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28 + +#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3) +#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3) +#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1) +#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1) +#define ARM_A9_WATCHDOG_ENABLE 1 + +// +// SCU register offsets & masks +// +#define A9_SCU_CONTROL_OFFSET 0x0 +#define A9_SCU_CONFIG_OFFSET 0x4 +#define A9_SCU_INVALL_OFFSET 0xC +#define A9_SCU_FILT_START_OFFSET 0x40 +#define A9_SCU_FILT_END_OFFSET 0x44 +#define A9_SCU_SACR_OFFSET 0x50 +#define A9_SCU_SSACR_OFFSET 0x54 + + +UINTN +EFIAPI +ArmGetScuBaseAddress ( + VOID + ); + +#endif + diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmV7.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmV7.h new file mode 100644 index 00000000..ee4ac437 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmV7.h @@ -0,0 +1,129 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ARM_V7_H__ +#define __ARM_V7_H__ + +#include + +// ARM Interrupt ID in Exception Table +#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ + +// ID_PFR1 - ARM Processor Feature Register 1 definitions +#define ARM_PFR1_SEC (0xFUL << 4) +#define ARM_PFR1_TIMER (0xFUL << 16) +#define ARM_PFR1_GIC (0xFUL << 28) + +// Domain Access Control Register +#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a))) +#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a))) +#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a))) +#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a))) +#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a))) + +// CPSR - Coprocessor Status Register definitions +#define CPSR_MODE_USER 0x10 +#define CPSR_MODE_FIQ 0x11 +#define CPSR_MODE_IRQ 0x12 +#define CPSR_MODE_SVC 0x13 +#define CPSR_MODE_ABORT 0x17 +#define CPSR_MODE_HYP 0x1A +#define CPSR_MODE_UNDEFINED 0x1B +#define CPSR_MODE_SYSTEM 0x1F +#define CPSR_MODE_MASK 0x1F +#define CPSR_ASYNC_ABORT (1 << 8) +#define CPSR_IRQ (1 << 7) +#define CPSR_FIQ (1 << 6) + + +// CPACR - Coprocessor Access Control Register definitions +#define CPACR_CP_DENIED(cp) 0x00 +#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF) +#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF) +#define CPACR_ASEDIS (1 << 31) +#define CPACR_D32DIS (1 << 30) +#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF + +// NSACR - Non-Secure Access Control Register definitions +#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF) +#define NSACR_NSD32DIS (1 << 14) +#define NSACR_NSASEDIS (1 << 15) +#define NSACR_PLE (1 << 16) +#define NSACR_TL (1 << 17) +#define NSACR_NS_SMP (1 << 18) +#define NSACR_RFR (1 << 19) + +// SCR - Secure Configuration Register definitions +#define SCR_NS (1 << 0) +#define SCR_IRQ (1 << 1) +#define SCR_FIQ (1 << 2) +#define SCR_EA (1 << 3) +#define SCR_FW (1 << 4) +#define SCR_AW (1 << 5) + +// MIDR - Main ID Register definitions +#define ARM_CPU_TYPE_SHIFT 4 +#define ARM_CPU_TYPE_MASK 0xFFF +#define ARM_CPU_TYPE_AEMv8 0xD0F +#define ARM_CPU_TYPE_A53 0xD03 +#define ARM_CPU_TYPE_A57 0xD07 +#define ARM_CPU_TYPE_A15 0xC0F +#define ARM_CPU_TYPE_A12 0xC0D +#define ARM_CPU_TYPE_A9 0xC09 +#define ARM_CPU_TYPE_A7 0xC07 +#define ARM_CPU_TYPE_A5 0xC05 + +#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) ) +#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF)) + +#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1) + +VOID +EFIAPI +ArmEnableSWPInstruction ( + VOID + ); + +UINTN +EFIAPI +ArmReadCbar ( + VOID + ); + +UINTN +EFIAPI +ArmReadTpidrurw ( + VOID + ); + +VOID +EFIAPI +ArmWriteTpidrurw ( + UINTN Value + ); + +UINT32 +EFIAPI +ArmReadNsacr ( + VOID + ); + +VOID +EFIAPI +ArmWriteNsacr ( + IN UINT32 Nsacr + ); + +#endif // __ARM_V7_H__ diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmV7Mmu.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmV7Mmu.h new file mode 100644 index 00000000..4d913824 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -0,0 +1,244 @@ +/** @file +* +* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARMV7_MMU_H_ +#define __ARMV7_MMU_H_ + +#define TTBR_NOT_OUTER_SHAREABLE BIT5 +#define TTBR_RGN_OUTER_NON_CACHEABLE 0 +#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3 +#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4 +#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4) +#define TTBR_SHAREABLE BIT1 +#define TTBR_NON_SHAREABLE 0 +#define TTBR_INNER_CACHEABLE BIT0 +#define TTBR_INNER_NON_CACHEABLE 0 +#define TTBR_RGN_INNER_NON_CACHEABLE 0 +#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6 +#define TTBR_RGN_INNER_WRITE_THROUGH BIT0 +#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6) + +#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE) +#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE) +#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE ) +#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE) + +#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE) +#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE) +#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE ) +#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE) + + +#define TRANSLATION_TABLE_SECTION_COUNT 4096 +#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT) +#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT) +#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1) + +#define TRANSLATION_TABLE_PAGE_COUNT 256 +#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT) +#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT) +#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1) + +#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20)) + +// Translation table descriptor types +#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0)) +#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0) +#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0) +#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0)) +#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0)) +#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE) + +// Translation table descriptor types +#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0) +#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0) +#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0) +#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0) +#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0) + +// Section descriptor definitions +#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000) + +#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19) +#define TT_DESCRIPTOR_SECTION_NS (1UL << 19) + +#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17) +#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17) +#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17) + +#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11) +#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11) +#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11) + +#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16) +#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16) +#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16) + +#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10) +#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10) +#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10) + +#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10)) +#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10)) +#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10)) +#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10)) +#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10)) +#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10)) +#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10)) + +#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4)) +#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4)) +#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4)) +#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4)) +#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4)) +#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4)) +#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4)) + +#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4) +#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0) +#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15) + +#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3) +#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2)) +#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2)) +#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2)) +#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2)) + +#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000) + +#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3) +#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2)) +#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2)) +#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2)) +#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2)) + +#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2)) +#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2)) +#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2)) +#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2)) +#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2)) + +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK) +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK) +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK) +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc,IsLargePage) ((IsLargePage)? \ + ((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_LARGEPAGE_XN_MASK): \ + ((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK)) +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \ + (((Desc) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK): \ + (((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2))))) + +#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK) + +#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \ + (((Desc) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK): \ + (((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2))))) + +#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \ + TT_DESCRIPTOR_SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \ + TT_DESCRIPTOR_SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) + +#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \ + TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \ + TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) + +#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5) +#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5) + +#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000) +#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00) +#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK) +#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20 + +#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000) +#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000) +#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) +#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12 + +#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \ + ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \ + TT_DESCRIPTOR_SECTION_NG_GLOBAL | \ + TT_DESCRIPTOR_SECTION_S_SHARED | \ + TT_DESCRIPTOR_SECTION_DOMAIN(0) | \ + TT_DESCRIPTOR_SECTION_AP_RW_RW | \ + TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC) +#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \ + ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \ + TT_DESCRIPTOR_SECTION_NG_GLOBAL | \ + TT_DESCRIPTOR_SECTION_S_SHARED | \ + TT_DESCRIPTOR_SECTION_DOMAIN(0) | \ + TT_DESCRIPTOR_SECTION_AP_RW_RW | \ + TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC) +#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \ + ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \ + TT_DESCRIPTOR_SECTION_NG_GLOBAL | \ + TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \ + TT_DESCRIPTOR_SECTION_DOMAIN(0) | \ + TT_DESCRIPTOR_SECTION_AP_RW_RW | \ + TT_DESCRIPTOR_SECTION_XN_MASK | \ + TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE) +#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \ + ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \ + TT_DESCRIPTOR_SECTION_NG_GLOBAL | \ + TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \ + TT_DESCRIPTOR_SECTION_DOMAIN(0) | \ + TT_DESCRIPTOR_SECTION_AP_RW_RW | \ + TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE) + +#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \ + TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ + TT_DESCRIPTOR_PAGE_S_SHARED | \ + TT_DESCRIPTOR_PAGE_AP_RW_RW | \ + TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC) +#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \ + TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ + TT_DESCRIPTOR_PAGE_S_SHARED | \ + TT_DESCRIPTOR_PAGE_AP_RW_RW | \ + TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC) +#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \ + TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ + TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ + TT_DESCRIPTOR_PAGE_AP_RW_RW | \ + TT_DESCRIPTOR_PAGE_XN_MASK | \ + TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE) +#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \ + TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ + TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ + TT_DESCRIPTOR_PAGE_AP_RW_RW | \ + TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE) + +// First Level Descriptors +typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR; + +// Second Level Descriptors +typedef UINT32 ARM_PAGE_TABLE_ENTRY; + +UINT32 +ConvertSectionAttributesToPageAttributes ( + IN UINT32 SectionAttributes, + IN BOOLEAN IsLargePage + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Guid/ArmMpCoreInfo.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Guid/ArmMpCoreInfo.h new file mode 100644 index 00000000..07dec5dc --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Guid/ArmMpCoreInfo.h @@ -0,0 +1,66 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARM_MP_CORE_INFO_GUID_H_ +#define __ARM_MP_CORE_INFO_GUID_H_ + +#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04 +#define SCU_CONFIG_REG_OFFSET 0x04 +#define MPIDR_U_BIT_MASK 0x40000000 + +typedef struct { + UINT32 ClusterId; + UINT32 CoreId; + + // MP Core Mailbox + EFI_PHYSICAL_ADDRESS MailboxSetAddress; + EFI_PHYSICAL_ADDRESS MailboxGetAddress; + EFI_PHYSICAL_ADDRESS MailboxClearAddress; + UINT64 MailboxClearValue; +} ARM_CORE_INFO; + +typedef struct{ + UINT64 Signature; + UINT32 Length; + UINT32 Revision; + UINT64 OemId; + UINT64 OemTableId; + UINTN OemRevision; + UINTN CreatorId; + UINTN CreatorRevision; + EFI_GUID Identifier; + UINTN DataLen; +} ARM_PROCESSOR_TABLE_HEADER; + +typedef struct { + ARM_PROCESSOR_TABLE_HEADER Header; + UINTN NumberOfEntries; + ARM_CORE_INFO *ArmCpus; +} ARM_PROCESSOR_TABLE; + + +#define ARM_MP_CORE_INFO_GUID \ + { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} } + +#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E') +#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000 //1.0 +#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ') +#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L') +#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001 +#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5 +#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001 + +extern EFI_GUID gArmMpCoreInfoGuid; + +#endif /* MPCOREINFO_H_ */ diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/IndustryStandard/ArmStdSmc.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/IndustryStandard/ArmStdSmc.h new file mode 100644 index 00000000..593a3ce7 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/IndustryStandard/ArmStdSmc.h @@ -0,0 +1,96 @@ +/** @file +* +* Copyright (c) 2012-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARM_STD_SMC_H__ +#define __ARM_STD_SMC_H__ + +/* + * SMC function IDs for Standard Service queries + */ + +#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00 +#define ARM_SMC_ID_STD_UID 0x8400ff01 +/* 0x8400ff02 is reserved */ +#define ARM_SMC_ID_STD_REVISION 0x8400ff03 + +/* + * The 'Standard Service Call UID' is supposed to return the Standard + * Service UUID. This is a 128-bit value. + */ +#define ARM_SMC_STD_UUID0 0x108d905b +#define ARM_SMC_STD_UUID1 0x47e8f863 +#define ARM_SMC_STD_UUID2 0xfbc02dae +#define ARM_SMC_STD_UUID3 0xe2f64156 + +/* + * ARM Standard Service Calls revision numbers + * The current revision is: 0.1 + */ +#define ARM_SMC_STD_REVISION_MAJOR 0x0 +#define ARM_SMC_STD_REVISION_MINOR 0x1 + +/* + * Power State Coordination Interface (PSCI) calls cover a subset of the + * Standard Service Call range. + * The list below is not exhaustive. + */ +#define ARM_SMC_ID_PSCI_VERSION 0x84000000 +#define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH64 0xc4000001 +#define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH32 0x84000001 +#define ARM_SMC_ID_PSCI_CPU_OFF 0x84000002 +#define ARM_SMC_ID_PSCI_CPU_ON_AARCH64 0xc4000003 +#define ARM_SMC_ID_PSCI_CPU_ON_AARCH32 0x84000003 +#define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH64 0xc4000004 +#define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH32 0x84000004 +#define ARM_SMC_ID_PSCI_MIGRATE_AARCH64 0xc4000005 +#define ARM_SMC_ID_PSCI_MIGRATE_AARCH32 0x84000005 +#define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x84000008 +#define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x84000009 + +/* The current PSCI version is: 0.2 */ +#define ARM_SMC_PSCI_VERSION_MAJOR 0 +#define ARM_SMC_PSCI_VERSION_MINOR 2 +#define ARM_SMC_PSCI_VERSION \ + ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR) + +/* PSCI return error codes */ +#define ARM_SMC_PSCI_RET_SUCCESS 0 +#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1 +#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2 +#define ARM_SMC_PSCI_RET_DENIED -3 +#define ARM_SMC_PSCI_RET_ALREADY_ON -4 +#define ARM_SMC_PSCI_RET_ON_PENDING -5 +#define ARM_SMC_PSCI_RET_INTERN_FAIL -6 +#define ARM_SMC_PSCI_RET_NOT_PRESENT -7 +#define ARM_SMC_PSCI_RET_DISABLED -8 + +#define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \ + ((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF)) + +#define ARM_SMC_PSCI_TARGET_CPU64(Aff3, Aff2, Aff1, Aff0) \ + ((((Aff3) & 0xFFULL) << 32) | (((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF)) + +#define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF) +#define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF) + +#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0 +#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1 +#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2 +#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3 + +#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0 +#define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1 +#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON_PENDING 2 + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/IndustryStandard/ArmTrustZoneSmc.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/IndustryStandard/ArmTrustZoneSmc.h new file mode 100644 index 00000000..71b4327e --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/IndustryStandard/ArmTrustZoneSmc.h @@ -0,0 +1,161 @@ +/** @file +* +* Copyright (c) 2012-2013, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARM_TRUSTZONE_SMC_H__ +#define __ARM_TRUSTZONE_SMC_H__ + +#define ARM_TRUSTZONE_UID_4LETTERID 0x1 +#define ARM_TRUSTZONE_UID_MD5 0x2 + +#define ARM_TRUSTZONE_ARM_UID 0x40524d48 // "ARMH" + +#define IS_ARM_TRUSTZONE_SUPPORTED_SMC(Rx,Region) (((UINTN)(Rx) >= (UINTN)ARM_TRUSTZONE_##Region##_SMC_ID_START) && ((UINTN)(Rx) <= (UINTN)ARM_TRUSTZONE_##Region##_SMC_ID_END)) + +#define IS_ARM_TRUSTZONE_DEPRECIATED_SMC(Rx) ((UINTN)(Rx) <= (UINTN)ARM_TRUSTZONE_DEPRECIATED_SMC_ID_END) +#define IS_ARM_TRUSTZONE_TRUSTED_OS_SMC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC(Rx,TRUSTED_OS) +#define IS_ARM_TRUSTZONE_ARM_FAST_SMC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC(Rx,ARM_FAST) +#define IS_ARM_TRUSTZONE_SIP_FAST_SMC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC(Rx,SIP_FAST) +#define IS_ARM_TRUSTZONE_ODM_FAST_SMC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC(Rx,ODM_FAST) +#define IS_ARM_TRUSTZONE_OEM_FAST_SMC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC(Rx,OEM_FAST) +#define IS_ARM_TRUSTZONE_TRUSTED_USER_FAST_SMC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC(Rx,TRUSTED_USER_FAST) +#define IS_ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC(Rx,TRUSTED_OS_FAST) + +#define IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_PRESENCE(Rx,Region) ((Rx) == ARM_TRUSTZONE_##Region##_SMC_ID_PRESENCE) +#define IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID(Rx,Region) (((Rx) == ARM_TRUSTZONE_##Region##_SMC_ID_UID) || \ + ((Rx) == ARM_TRUSTZONE_##Region##_SMC_ID_UID+1) || \ + ((Rx) == ARM_TRUSTZONE_##Region##_SMC_ID_UID+2) || \ + ((Rx) == ARM_TRUSTZONE_##Region##_SMC_ID_UID+3) || \ + ((Rx) == ARM_TRUSTZONE_##Region##_SMC_ID_UID+4)) +#define IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION(Rx,Region) (((Rx) == ARM_TRUSTZONE_##Region##_SMC_ID_REVISION) || \ + ((Rx) == ARM_TRUSTZONE_##Region##_SMC_ID_REVISION+1)) +#define IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC(Rx,Region) (((Rx) >= ARM_TRUSTZONE_##Region##_SMC_ID_RPC_START) && \ + ((Rx) <= ARM_TRUSTZONE_##Region##_SMC_ID_RPC_END)) + +#define ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID_INDEX(Rx,Region) ((Rx) - ARM_TRUSTZONE_##Region##_SMC_ID_UID) +#define ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION_INDEX(Rx,Region) ((Rx) - ARM_TRUSTZONE_##Region##_SMC_ID_REVISION) +#define ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC_INDEX(Rx,Region) ((Rx) - ARM_TRUSTZONE_##Region##_SMC_ID_RPC_START) + +#define ARM_TRUSTZONE_TRUSTED_OS_SMC_ID_RPC_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC_INDEX(Rx,TRUSTED_OS) + +#define IS_ARM_TRUSTZONE_ARM_FAST_SMC_ID_PRESENCE(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_PRESENCE(Rx,ARM_FAST) +#define IS_ARM_TRUSTZONE_ARM_FAST_SMC_ID_UID(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID(Rx,ARM_FAST) +#define IS_ARM_TRUSTZONE_ARM_FAST_SMC_ID_REVISION(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION(Rx,ARM_FAST) +#define IS_ARM_TRUSTZONE_ARM_FAST_SMC_ID_RPC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC(Rx,ARM_FAST) +#define ARM_TRUSTZONE_ARM_FAST_SMC_ID_UID_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID_INDEX(Rx,ARM_FAST) +#define ARM_TRUSTZONE_ARM_FAST_SMC_ID_REVISION_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION_INDEX(Rx,ARM_FAST) +#define ARM_TRUSTZONE_ARM_FAST_SMC_ID_RPC_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC_INDEX(Rx,ARM_FAST) + +#define IS_ARM_TRUSTZONE_ODM_FAST_SMC_ID_PRESENCE(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_PRESENCE(Rx,ODM_FAST) +#define IS_ARM_TRUSTZONE_ODM_FAST_SMC_ID_UID(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID(Rx,ODM_FAST) +#define IS_ARM_TRUSTZONE_ODM_FAST_SMC_ID_REVISION(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION(Rx,ODM_FAST) +#define IS_ARM_TRUSTZONE_ODM_FAST_SMC_ID_RPC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC(Rx,ODM_FAST) +#define ARM_TRUSTZONE_ODM_FAST_SMC_ID_UID_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID_INDEX(Rx,ODM_FAST) +#define ARM_TRUSTZONE_ODM_FAST_SMC_ID_REVISION_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION_INDEX(Rx,ODM_FAST) +#define ARM_TRUSTZONE_ODM_FAST_SMC_ID_RPC_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC_INDEX(Rx,ODM_FAST) + +#define IS_ARM_TRUSTZONE_OEM_FAST_SMC_ID_PRESENCE(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_PRESENCE(Rx,OEM_FAST) +#define IS_ARM_TRUSTZONE_OEM_FAST_SMC_ID_UID(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID(Rx,OEM_FAST) +#define IS_ARM_TRUSTZONE_OEM_FAST_SMC_ID_REVISION(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION(Rx,OEM_FAST) +#define IS_ARM_TRUSTZONE_OEM_FAST_SMC_ID_RPC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC(Rx,OEM_FAST) +#define ARM_TRUSTZONE_OEM_FAST_SMC_ID_UID_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID_INDEX(Rx,OEM_FAST) +#define ARM_TRUSTZONE_OEM_FAST_SMC_ID_REVISION_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION_INDEX(Rx,OEM_FAST) +#define ARM_TRUSTZONE_OEM_FAST_SMC_ID_RPC_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC_INDEX(Rx,OEM_FAST) + +#define IS_ARM_TRUSTZONE_SIP_FAST_SMC_ID_PRESENCE(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_PRESENCE(Rx,SIP_FAST) +#define IS_ARM_TRUSTZONE_SIP_FAST_SMC_ID_UID(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID(Rx,SIP_FAST) +#define IS_ARM_TRUSTZONE_SIP_FAST_SMC_ID_REVISION(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION(Rx,SIP_FAST) +#define IS_ARM_TRUSTZONE_SIP_FAST_SMC_ID_RPC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC(Rx,SIP_FAST) +#define ARM_TRUSTZONE_SIP_FAST_SMC_ID_UID_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID_INDEX(Rx,SIP_FAST) +#define ARM_TRUSTZONE_SIP_FAST_SMC_ID_REVISION_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION_INDEX(Rx,SIP_FAST) +#define ARM_TRUSTZONE_SIP_FAST_SMC_ID_RPC_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC_INDEX(Rx,SIP_FAST) + +#define ARM_TRUSTZONE_TRUSTED_USER_FAST_SMC_ID_RPC_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC_INDEX(Rx,TRUSTED_USER_FAST) + +#define IS_ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_PRESENCE(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_PRESENCE(Rx,TRUSTED_OS_FAST) +#define IS_ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_UID(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID(Rx,TRUSTED_OS_FAST) +#define IS_ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_REVISION(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION(Rx,TRUSTED_OS_FAST) +#define IS_ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_RPC(Rx) IS_ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC(Rx,TRUSTED_OS_FAST) +#define ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_UID_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_UID_INDEX(Rx,TRUSTED_OS_FAST) +#define ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_REVISION_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_REVISION_INDEX(Rx,TRUSTED_OS_FAST) +#define ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_RPC_INDEX(Rx) ARM_TRUSTZONE_SUPPORTED_SMC_ID_RPC_INDEX(Rx,TRUSTED_OS_FAST) + + +#define ARM_TRUSTZONE_DEPRECIATED_SMC_ID_START 0x00000000 +#define ARM_TRUSTZONE_DEPRECIATED_SMC_ID_END 0x01FFFFFF + + +#define ARM_TRUSTZONE_TRUSTED_OS_SMC_ID_START 0x02000000 +#define ARM_TRUSTZONE_TRUSTED_OS_SMC_ID_END 0x1FFFFFFF + +#define ARM_TRUSTZONE_TRUSTED_OS_SMC_ID_RPC_START 0x02000000 +#define ARM_TRUSTZONE_TRUSTED_OS_SMC_ID_RPC_END 0x1FFFFFFF + + +#define ARM_TRUSTZONE_ARM_FAST_SMC_ID_START 0x80000000 +#define ARM_TRUSTZONE_ARM_FAST_SMC_ID_END 0x80FFFFFF + +#define ARM_TRUSTZONE_ARM_FAST_SMC_ID_RPC_START 0x80000000 +#define ARM_TRUSTZONE_ARM_FAST_SMC_ID_RPC_END 0x80FFFEFF +#define ARM_TRUSTZONE_ARM_FAST_SMC_ID_PRESENCE 0x80FFFF00 +#define ARM_TRUSTZONE_ARM_FAST_SMC_ID_UID 0x80FFFF10 +#define ARM_TRUSTZONE_ARM_FAST_SMC_ID_REVISION 0x80FFFF20 + + +#define ARM_TRUSTZONE_SIP_FAST_SMC_ID_START 0x81000000 +#define ARM_TRUSTZONE_SIP_FAST_SMC_ID_END 0x81FFFFFF + +#define ARM_TRUSTZONE_SIP_FAST_SMC_ID_RPC_START 0x81000000 +#define ARM_TRUSTZONE_SIP_FAST_SMC_ID_RPC_END 0x81FFFEFF +#define ARM_TRUSTZONE_SIP_FAST_SMC_ID_PRESENCE 0x81FFFF00 +#define ARM_TRUSTZONE_SIP_FAST_SMC_ID_UID 0x81FFFF10 +#define ARM_TRUSTZONE_SIP_FAST_SMC_ID_REVISION 0x81FFFF20 + + +#define ARM_TRUSTZONE_ODM_FAST_SMC_ID_START 0x82000000 +#define ARM_TRUSTZONE_ODM_FAST_SMC_ID_END 0x82FFFFFF + +#define ARM_TRUSTZONE_ODM_FAST_SMC_ID_RPC_START 0x82000000 +#define ARM_TRUSTZONE_ODM_FAST_SMC_ID_RPC_END 0x82FFFEFF +#define ARM_TRUSTZONE_ODM_FAST_SMC_ID_PRESENCE 0x82FFFF00 +#define ARM_TRUSTZONE_ODM_FAST_SMC_ID_UID 0x82FFFF10 +#define ARM_TRUSTZONE_ODM_FAST_SMC_ID_REVISION 0x82FFFF20 + + +#define ARM_TRUSTZONE_OEM_FAST_SMC_ID_START 0x83000000 +#define ARM_TRUSTZONE_OEM_FAST_SMC_ID_END 0x83FFFFFF + +#define ARM_TRUSTZONE_OEM_FAST_SMC_ID_RPC_START 0x83000000 +#define ARM_TRUSTZONE_OEM_FAST_SMC_ID_RPC_END 0x83FFFEFF +#define ARM_TRUSTZONE_OEM_FAST_SMC_ID_PRESENCE 0x83FFFF00 +#define ARM_TRUSTZONE_OEM_FAST_SMC_ID_UID 0x83FFFF10 +#define ARM_TRUSTZONE_OEM_FAST_SMC_ID_REVISION 0x83FFFF20 + + +#define ARM_TRUSTZONE_TRUSTED_USER_FAST_SMC_ID_START 0xF0000000 +#define ARM_TRUSTZONE_TRUSTED_USER_FAST_SMC_ID_END 0xF1FFFFFF + +#define ARM_TRUSTZONE_TRUSTED_USER_FAST_SMC_ID_RPC_START 0xF0000000 +#define ARM_TRUSTZONE_TRUSTED_USER_FAST_SMC_ID_RPC_END 0xF1FFFEFF + + +#define ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_START 0xF2000000 +#define ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_END 0xFFFFFFFF + +#define ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_RPC_START 0xF2000000 +#define ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_RPC_END 0xFFFFFEFF +#define ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_PRESENCE 0xF2FFFF00 +#define ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_UID 0xF2FFFF10 +#define ARM_TRUSTZONE_TRUSTED_OS_FAST_SMC_ID_REVISION 0xF2FFFF20 + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmDisassemblerLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmDisassemblerLib.h new file mode 100644 index 00000000..d6a493f2 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmDisassemblerLib.h @@ -0,0 +1,43 @@ +/** @file + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ARM_DISASSEBLER_LIB_H__ +#define __ARM_DISASSEBLER_LIB_H__ + +/** + Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to + point to next instructin. + + We cheat and only decode instructions that access + memory. If the instruction is not found we dump the instruction in hex. + + @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble. + @param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream + @param Extended TRUE dump hex for instruction too. + @param ItBlock Size of IT Block + @param Buf Buffer to sprintf disassembly into. + @param Size Size of Buf in bytes. + +**/ +VOID +DisassembleInstruction ( + IN UINT8 **OpCodePtr, + IN BOOLEAN Thumb, + IN BOOLEAN Extended, + IN OUT UINT32 *ItBlock, + OUT CHAR8 *Buf, + OUT UINTN Size + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h new file mode 100644 index 00000000..805025ba --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h @@ -0,0 +1,85 @@ +/** @file + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2014, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ARM_GENERIC_TIMER_COUNTER_LIB_H__ +#define __ARM_GENERIC_TIMER_COUNTER_LIB_H__ + +VOID +EFIAPI +ArmGenericTimerEnableTimer ( + VOID + ); + +VOID +EFIAPI +ArmGenericTimerDisableTimer ( + VOID + ); + +VOID +EFIAPI +ArmGenericTimerSetTimerFreq ( + IN UINTN FreqInHz + ); + +UINTN +EFIAPI +ArmGenericTimerGetTimerFreq ( + VOID + ); + +VOID +EFIAPI +ArmGenericTimerSetTimerVal ( + IN UINTN Value + ); + +UINTN +EFIAPI +ArmGenericTimerGetTimerVal ( + VOID + ); + +UINT64 +EFIAPI +ArmGenericTimerGetSystemCount ( + VOID + ); + +UINTN +EFIAPI +ArmGenericTimerGetTimerCtrlReg ( + VOID + ); + +VOID +EFIAPI +ArmGenericTimerSetTimerCtrlReg ( + UINTN Value + ); + +UINT64 +EFIAPI +ArmGenericTimerGetCompareVal ( + VOID + ); + +VOID +EFIAPI +ArmGenericTimerSetCompareVal ( + IN UINT64 Value + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmGicArchLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmGicArchLib.h new file mode 100644 index 00000000..e6964a2d --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmGicArchLib.h @@ -0,0 +1,33 @@ +/** @file +* +* Copyright (c) 2015, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARM_GIC_ARCH_LIB_H__ +#define __ARM_GIC_ARCH_LIB_H__ + +// +// GIC definitions +// +typedef enum { + ARM_GIC_ARCH_REVISION_2, + ARM_GIC_ARCH_REVISION_3 +} ARM_GIC_ARCH_REVISION; + + +ARM_GIC_ARCH_REVISION +EFIAPI +ArmGicGetSupportedArchRevision ( + VOID + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmGicLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmGicLib.h new file mode 100644 index 00000000..4364f3ff --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmGicLib.h @@ -0,0 +1,317 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARMGIC_H +#define __ARMGIC_H + +#include + +// +// GIC Distributor +// +#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register +#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register +#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register + +// Each reg base below repeats for Number of interrupts / 4 (see GIC spec) +#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers +#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers +#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers +#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers +#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers +#define ARM_GIC_ICDABR 0x300 // Active Bit Registers + +// Each reg base below repeats for Number of interrupts / 4 +#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers + +// Each reg base below repeats for Number of interrupts +#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers +#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers + +#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register + +// just one of these +#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register + +// GICv3 specific registers +#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers + +// GICD_CTLR bits +#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE) +#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS) + +// +// GIC Redistributor +// + +#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB +#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB + +// GIC Redistributor Control frame +#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register + +// GIC SGI & PPI Redistributor frame +#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers +#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers + +// +// GIC Cpu interface +// +#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register +#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register +#define ARM_GIC_ICCBPR 0x08 // Binary Point Register +#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register +#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register +#define ARM_GIC_ICCRPR 0x14 // Running Priority Register +#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register +#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register +#define ARM_GIC_ICCIIDR 0xFC // Identification Register + +#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0 +#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1 +#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2 + +// Bit-masks to configure the CPU Interface Control register +#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01 +#define ARM_GIC_ICCICR_ENABLE_NS 0x02 +#define ARM_GIC_ICCICR_ACK_CTL 0x04 +#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08 +#define ARM_GIC_ICCICR_USE_SBPR 0x10 + +// Bit Mask for GICC_IIDR +#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF) +#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF) +#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF) +#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF) + +// Bit Mask for +#define ARM_GIC_ICCIAR_ACKINTID 0x3FF + +UINTN +EFIAPI +ArmGicGetInterfaceIdentification ( + IN INTN GicInterruptInterfaceBase + ); + +// +// GIC Secure interfaces +// +VOID +EFIAPI +ArmGicSetupNonSecure ( + IN UINTN MpId, + IN INTN GicDistributorBase, + IN INTN GicInterruptInterfaceBase + ); + +VOID +EFIAPI +ArmGicSetSecureInterrupts ( + IN UINTN GicDistributorBase, + IN UINTN* GicSecureInterruptMask, + IN UINTN GicSecureInterruptMaskSize + ); + +VOID +EFIAPI +ArmGicEnableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ); + +VOID +EFIAPI +ArmGicDisableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ); + +VOID +EFIAPI +ArmGicEnableDistributor ( + IN INTN GicDistributorBase + ); + +VOID +EFIAPI +ArmGicDisableDistributor ( + IN INTN GicDistributorBase + ); + +UINTN +EFIAPI +ArmGicGetMaxNumInterrupts ( + IN INTN GicDistributorBase + ); + +VOID +EFIAPI +ArmGicSendSgiTo ( + IN INTN GicDistributorBase, + IN INTN TargetListFilter, + IN INTN CPUTargetList, + IN INTN SgiId + ); + +/* + * Acknowledge and return the value of the Interrupt Acknowledge Register + * + * InterruptId is returned separately from the register value because in + * the GICv2 the register value contains the CpuId and InterruptId while + * in the GICv3 the register value is only the InterruptId. + * + * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface + * @param InterruptId InterruptId read from the Interrupt Acknowledge Register + * + * @retval value returned by the Interrupt Acknowledge Register + * + */ +UINTN +EFIAPI +ArmGicAcknowledgeInterrupt ( + IN UINTN GicInterruptInterfaceBase, + OUT UINTN *InterruptId + ); + +VOID +EFIAPI +ArmGicEndOfInterrupt ( + IN UINTN GicInterruptInterfaceBase, + IN UINTN Source + ); + +UINTN +EFIAPI +ArmGicSetPriorityMask ( + IN INTN GicInterruptInterfaceBase, + IN INTN PriorityMask + ); + +VOID +EFIAPI +ArmGicEnableInterrupt ( + IN UINTN GicDistributorBase, + IN UINTN GicRedistributorBase, + IN UINTN Source + ); + +VOID +EFIAPI +ArmGicDisableInterrupt ( + IN UINTN GicDistributorBase, + IN UINTN GicRedistributorBase, + IN UINTN Source + ); + +BOOLEAN +EFIAPI +ArmGicIsInterruptEnabled ( + IN UINTN GicDistributorBase, + IN UINTN GicRedistributorBase, + IN UINTN Source + ); + +// +// GIC revision 2 specific declarations +// + +// Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts) +#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023)) + +VOID +EFIAPI +ArmGicV2SetupNonSecure ( + IN UINTN MpId, + IN INTN GicDistributorBase, + IN INTN GicInterruptInterfaceBase + ); + +VOID +EFIAPI +ArmGicV2EnableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ); + +VOID +EFIAPI +ArmGicV2DisableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ); + +UINTN +EFIAPI +ArmGicV2AcknowledgeInterrupt ( + IN UINTN GicInterruptInterfaceBase + ); + +VOID +EFIAPI +ArmGicV2EndOfInterrupt ( + IN UINTN GicInterruptInterfaceBase, + IN UINTN Source + ); + +// +// GIC revision 3 specific declarations +// + +#define ICC_SRE_EL2_SRE (1 << 0) + +#define ARM_GICD_IROUTER_IRM BIT31 + +UINT32 +EFIAPI +ArmGicV3GetControlSystemRegisterEnable ( + VOID + ); + +VOID +EFIAPI +ArmGicV3SetControlSystemRegisterEnable ( + IN UINT32 ControlSystemRegisterEnable + ); + +VOID +EFIAPI +ArmGicV3EnableInterruptInterface ( + VOID + ); + +VOID +EFIAPI +ArmGicV3DisableInterruptInterface ( + VOID + ); + +UINTN +EFIAPI +ArmGicV3AcknowledgeInterrupt ( + VOID + ); + +VOID +EFIAPI +ArmGicV3EndOfInterrupt ( + IN UINTN Source + ); + +VOID +ArmGicV3SetBinaryPointer ( + IN UINTN BinaryPoint + ); + +VOID +ArmGicV3SetPriorityMask ( + IN UINTN Priority + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmHvcLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmHvcLib.h new file mode 100644 index 00000000..4e9d1c40 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmHvcLib.h @@ -0,0 +1,46 @@ +/** @file +* +* Copyright (c) 2012-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARM_HVC_LIB__ +#define __ARM_HVC_LIB__ + +/** + * The size of the HVC arguments are different between AArch64 and AArch32. + * The native size is used for the arguments. + */ +typedef struct { + UINTN Arg0; + UINTN Arg1; + UINTN Arg2; + UINTN Arg3; + UINTN Arg4; + UINTN Arg5; + UINTN Arg6; + UINTN Arg7; +} ARM_HVC_ARGS; + +/** + Trigger an HVC call + + HVC calls can take up to 8 arguments and return up to 4 return values. + Therefore, the 4 first fields in the ARM_HVC_ARGS structure are used + for both input and output values. + +**/ +VOID +ArmCallHvc ( + IN OUT ARM_HVC_ARGS *Args + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmLib.h new file mode 100644 index 00000000..24ffe9f1 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmLib.h @@ -0,0 +1,722 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ARM_LIB__ +#define __ARM_LIB__ + +#include + +#ifdef MDE_CPU_ARM + #include +#elif defined(MDE_CPU_AARCH64) + #include +#else + #error "Unknown chipset." +#endif + +#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \ + EFI_MEMORY_WT | EFI_MEMORY_WB | \ + EFI_MEMORY_UCE) + +/** + * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes. + * + * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only + * be used in Secure World to distinguished Secure to Non-Secure memory. + */ +typedef enum { + ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0, + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED, + ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK, + ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH, + ARM_MEMORY_REGION_ATTRIBUTE_DEVICE, + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE +} ARM_MEMORY_REGION_ATTRIBUTES; + +#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1) + +typedef struct { + EFI_PHYSICAL_ADDRESS PhysicalBase; + EFI_VIRTUAL_ADDRESS VirtualBase; + UINT64 Length; + ARM_MEMORY_REGION_ATTRIBUTES Attributes; +} ARM_MEMORY_REGION_DESCRIPTOR; + +typedef VOID (*CACHE_OPERATION)(VOID); +typedef VOID (*LINE_OPERATION)(UINTN); + +// +// ARM Processor Mode +// +typedef enum { + ARM_PROCESSOR_MODE_USER = 0x10, + ARM_PROCESSOR_MODE_FIQ = 0x11, + ARM_PROCESSOR_MODE_IRQ = 0x12, + ARM_PROCESSOR_MODE_SUPERVISOR = 0x13, + ARM_PROCESSOR_MODE_ABORT = 0x17, + ARM_PROCESSOR_MODE_HYP = 0x1A, + ARM_PROCESSOR_MODE_UNDEFINED = 0x1B, + ARM_PROCESSOR_MODE_SYSTEM = 0x1F, + ARM_PROCESSOR_MODE_MASK = 0x1F +} ARM_PROCESSOR_MODE; + +// +// ARM Cpu IDs +// +#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24) +#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24) +#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24) +#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24) +#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24) +#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24) + +#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4) +#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4) +#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4) +#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4) +#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4) +#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4) + +// +// ARM MP Core IDs +// +#define ARM_CORE_AFF0 0xFF +#define ARM_CORE_AFF1 (0xFF << 8) +#define ARM_CORE_AFF2 (0xFF << 16) +#define ARM_CORE_AFF3 (0xFFULL << 32) + +#define ARM_CORE_MASK ARM_CORE_AFF0 +#define ARM_CLUSTER_MASK ARM_CORE_AFF1 +#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK) +#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8) +#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) +#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK) + +UINTN +EFIAPI +ArmDataCacheLineLength ( + VOID + ); + +UINTN +EFIAPI +ArmInstructionCacheLineLength ( + VOID + ); + +UINTN +EFIAPI +ArmCacheWritebackGranule ( + VOID + ); + +UINTN +EFIAPI +ArmIsArchTimerImplemented ( + VOID + ); + +UINTN +EFIAPI +ArmReadIdPfr0 ( + VOID + ); + +UINTN +EFIAPI +ArmReadIdPfr1 ( + VOID + ); + +UINTN +EFIAPI +ArmCacheInfo ( + VOID + ); + +BOOLEAN +EFIAPI +ArmIsMpCore ( + VOID + ); + +VOID +EFIAPI +ArmInvalidateDataCache ( + VOID + ); + + +VOID +EFIAPI +ArmCleanInvalidateDataCache ( + VOID + ); + +VOID +EFIAPI +ArmCleanDataCache ( + VOID + ); + +VOID +EFIAPI +ArmInvalidateInstructionCache ( + VOID + ); + +VOID +EFIAPI +ArmInvalidateDataCacheEntryByMVA ( + IN UINTN Address + ); + +VOID +EFIAPI +ArmCleanDataCacheEntryToPoUByMVA ( + IN UINTN Address + ); + +VOID +EFIAPI +ArmInvalidateInstructionCacheEntryToPoUByMVA ( + IN UINTN Address + ); + +VOID +EFIAPI +ArmCleanDataCacheEntryByMVA ( +IN UINTN Address +); + +VOID +EFIAPI +ArmCleanInvalidateDataCacheEntryByMVA ( + IN UINTN Address + ); + +VOID +EFIAPI +ArmInvalidateDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + +VOID +EFIAPI +ArmCleanDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + +VOID +EFIAPI +ArmCleanInvalidateDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + +VOID +EFIAPI +ArmEnableDataCache ( + VOID + ); + +VOID +EFIAPI +ArmDisableDataCache ( + VOID + ); + +VOID +EFIAPI +ArmEnableInstructionCache ( + VOID + ); + +VOID +EFIAPI +ArmDisableInstructionCache ( + VOID + ); + +VOID +EFIAPI +ArmEnableMmu ( + VOID + ); + +VOID +EFIAPI +ArmDisableMmu ( + VOID + ); + +VOID +EFIAPI +ArmEnableCachesAndMmu ( + VOID + ); + +VOID +EFIAPI +ArmDisableCachesAndMmu ( + VOID + ); + +VOID +EFIAPI +ArmEnableInterrupts ( + VOID + ); + +UINTN +EFIAPI +ArmDisableInterrupts ( + VOID + ); + +BOOLEAN +EFIAPI +ArmGetInterruptState ( + VOID + ); + +VOID +EFIAPI +ArmEnableAsynchronousAbort ( + VOID + ); + +UINTN +EFIAPI +ArmDisableAsynchronousAbort ( + VOID + ); + +VOID +EFIAPI +ArmEnableIrq ( + VOID + ); + +UINTN +EFIAPI +ArmDisableIrq ( + VOID + ); + +VOID +EFIAPI +ArmEnableFiq ( + VOID + ); + +UINTN +EFIAPI +ArmDisableFiq ( + VOID + ); + +BOOLEAN +EFIAPI +ArmGetFiqState ( + VOID + ); + +/** + * Invalidate Data and Instruction TLBs + */ +VOID +EFIAPI +ArmInvalidateTlb ( + VOID + ); + +VOID +EFIAPI +ArmUpdateTranslationTableEntry ( + IN VOID *TranslationTableEntry, + IN VOID *Mva + ); + +VOID +EFIAPI +ArmSetDomainAccessControl ( + IN UINT32 Domain + ); + +VOID +EFIAPI +ArmSetTTBR0 ( + IN VOID *TranslationTableBase + ); + +VOID +EFIAPI +ArmSetTTBCR ( + IN UINT32 Bits + ); + +VOID * +EFIAPI +ArmGetTTBR0BaseAddress ( + VOID + ); + +BOOLEAN +EFIAPI +ArmMmuEnabled ( + VOID + ); + +VOID +EFIAPI +ArmEnableBranchPrediction ( + VOID + ); + +VOID +EFIAPI +ArmDisableBranchPrediction ( + VOID + ); + +VOID +EFIAPI +ArmSetLowVectors ( + VOID + ); + +VOID +EFIAPI +ArmSetHighVectors ( + VOID + ); + +VOID +EFIAPI +ArmDataMemoryBarrier ( + VOID + ); + +VOID +EFIAPI +ArmDataSynchronizationBarrier ( + VOID + ); + +VOID +EFIAPI +ArmInstructionSynchronizationBarrier ( + VOID + ); + +VOID +EFIAPI +ArmWriteVBar ( + IN UINTN VectorBase + ); + +UINTN +EFIAPI +ArmReadVBar ( + VOID + ); + +VOID +EFIAPI +ArmWriteAuxCr ( + IN UINT32 Bit + ); + +UINT32 +EFIAPI +ArmReadAuxCr ( + VOID + ); + +VOID +EFIAPI +ArmSetAuxCrBit ( + IN UINT32 Bits + ); + +VOID +EFIAPI +ArmUnsetAuxCrBit ( + IN UINT32 Bits + ); + +VOID +EFIAPI +ArmCallSEV ( + VOID + ); + +VOID +EFIAPI +ArmCallWFE ( + VOID + ); + +VOID +EFIAPI +ArmCallWFI ( + + VOID + ); + +UINTN +EFIAPI +ArmReadMpidr ( + VOID + ); + +UINTN +EFIAPI +ArmReadMidr ( + VOID + ); + +UINT32 +EFIAPI +ArmReadCpacr ( + VOID + ); + +VOID +EFIAPI +ArmWriteCpacr ( + IN UINT32 Access + ); + +VOID +EFIAPI +ArmEnableVFP ( + VOID + ); + +/** + Get the Secure Configuration Register value + + @return Value read from the Secure Configuration Register + +**/ +UINT32 +EFIAPI +ArmReadScr ( + VOID + ); + +/** + Set the Secure Configuration Register + + @param Value Value to write to the Secure Configuration Register + +**/ +VOID +EFIAPI +ArmWriteScr ( + IN UINT32 Value + ); + +UINT32 +EFIAPI +ArmReadMVBar ( + VOID + ); + +VOID +EFIAPI +ArmWriteMVBar ( + IN UINT32 VectorMonitorBase + ); + +UINT32 +EFIAPI +ArmReadSctlr ( + VOID + ); + +UINTN +EFIAPI +ArmReadHVBar ( + VOID + ); + +VOID +EFIAPI +ArmWriteHVBar ( + IN UINTN HypModeVectorBase + ); + + +// +// Helper functions for accessing CPU ACTLR +// + +UINTN +EFIAPI +ArmReadCpuActlr ( + VOID + ); + +VOID +EFIAPI +ArmWriteCpuActlr ( + IN UINTN Val + ); + +VOID +EFIAPI +ArmSetCpuActlrBit ( + IN UINTN Bits + ); + +VOID +EFIAPI +ArmUnsetCpuActlrBit ( + IN UINTN Bits + ); + +// +// Accessors for the architected generic timer registers +// + +#define ARM_ARCH_TIMER_ENABLE (1 << 0) +#define ARM_ARCH_TIMER_IMASK (1 << 1) +#define ARM_ARCH_TIMER_ISTATUS (1 << 2) + +UINTN +EFIAPI +ArmReadCntFrq ( + VOID + ); + +VOID +EFIAPI +ArmWriteCntFrq ( + UINTN FreqInHz + ); + +UINT64 +EFIAPI +ArmReadCntPct ( + VOID + ); + +UINTN +EFIAPI +ArmReadCntkCtl ( + VOID + ); + +VOID +EFIAPI +ArmWriteCntkCtl ( + UINTN Val + ); + +UINTN +EFIAPI +ArmReadCntpTval ( + VOID + ); + +VOID +EFIAPI +ArmWriteCntpTval ( + UINTN Val + ); + +UINTN +EFIAPI +ArmReadCntpCtl ( + VOID + ); + +VOID +EFIAPI +ArmWriteCntpCtl ( + UINTN Val + ); + +UINTN +EFIAPI +ArmReadCntvTval ( + VOID + ); + +VOID +EFIAPI +ArmWriteCntvTval ( + UINTN Val + ); + +UINTN +EFIAPI +ArmReadCntvCtl ( + VOID + ); + +VOID +EFIAPI +ArmWriteCntvCtl ( + UINTN Val + ); + +UINT64 +EFIAPI +ArmReadCntvCt ( + VOID + ); + +UINT64 +EFIAPI +ArmReadCntpCval ( + VOID + ); + +VOID +EFIAPI +ArmWriteCntpCval ( + UINT64 Val + ); + +UINT64 +EFIAPI +ArmReadCntvCval ( + VOID + ); + +VOID +EFIAPI +ArmWriteCntvCval ( + UINT64 Val + ); + +UINT64 +EFIAPI +ArmReadCntvOff ( + VOID + ); + +VOID +EFIAPI +ArmWriteCntvOff ( + UINT64 Val + ); + +#endif // __ARM_LIB__ diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmMmuLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmMmuLib.h new file mode 100644 index 00000000..fb7fd006 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmMmuLib.h @@ -0,0 +1,72 @@ +/** @file + + Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ARM_MMU_LIB__ +#define __ARM_MMU_LIB__ + +#include + +#include + +EFI_STATUS +EFIAPI +ArmConfigureMmu ( + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, + OUT VOID **TranslationTableBase OPTIONAL, + OUT UINTN *TranslationTableSize OPTIONAL + ); + +EFI_STATUS +EFIAPI +ArmSetMemoryRegionNoExec ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +EFI_STATUS +EFIAPI +ArmClearMemoryRegionNoExec ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +EFI_STATUS +EFIAPI +ArmSetMemoryRegionReadOnly ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +EFI_STATUS +EFIAPI +ArmClearMemoryRegionReadOnly ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +VOID +EFIAPI +ArmReplaceLiveTranslationEntry ( + IN UINT64 *Entry, + IN UINT64 Value + ); + +EFI_STATUS +ArmSetMemoryAttributes ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmSmcLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmSmcLib.h new file mode 100644 index 00000000..168e3bb4 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/ArmSmcLib.h @@ -0,0 +1,46 @@ +/** @file +* +* Copyright (c) 2012-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARM_SMC_LIB__ +#define __ARM_SMC_LIB__ + +/** + * The size of the SMC arguments are different between AArch64 and AArch32. + * The native size is used for the arguments. + */ +typedef struct { + UINTN Arg0; + UINTN Arg1; + UINTN Arg2; + UINTN Arg3; + UINTN Arg4; + UINTN Arg5; + UINTN Arg6; + UINTN Arg7; +} ARM_SMC_ARGS; + +/** + Trigger an SMC call + + SMC calls can take up to 7 arguments and return up to 4 return values. + Therefore, the 4 first fields in the ARM_SMC_ARGS structure are used + for both input and output values. + +**/ +VOID +ArmCallSmc ( + IN OUT ARM_SMC_ARGS *Args + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/BdsLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/BdsLib.h new file mode 100644 index 00000000..c58f47eb --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/BdsLib.h @@ -0,0 +1,209 @@ +/** @file +* +* Copyright (c) 2013-2015, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __BDS_ENTRY_H__ +#define __BDS_ENTRY_H__ + +/** + This is defined by the UEFI specs, don't change it +**/ +typedef struct { + UINT16 LoadOptionIndex; + EFI_LOAD_OPTION *LoadOption; + UINTN LoadOptionSize; + + UINT32 Attributes; + UINT16 FilePathListLength; + CHAR16 *Description; + EFI_DEVICE_PATH_PROTOCOL *FilePathList; + + VOID* OptionalData; + UINTN OptionalDataSize; +} BDS_LOAD_OPTION; + +/** + Connect a Device Path and return the handle of the driver that support this DevicePath + + @param DevicePath Device Path of the File to connect + @param Handle Handle of the driver that support this DevicePath + @param RemainingDevicePath Remaining DevicePath nodes that do not match the driver DevicePath + + @retval EFI_SUCCESS A driver that matches the Device Path has been found + @retval EFI_NOT_FOUND No handles match the search. + @retval EFI_INVALID_PARAMETER DevicePath or Handle is NULL + +**/ +EFI_STATUS +BdsConnectDevicePath ( + IN EFI_DEVICE_PATH_PROTOCOL* DevicePath, + OUT EFI_HANDLE *Handle, + OUT EFI_DEVICE_PATH_PROTOCOL **RemainingDevicePath + ); + +/** + Connect all DXE drivers + + @retval EFI_SUCCESS All drivers have been connected + @retval EFI_NOT_FOUND No handles match the search. + @retval EFI_OUT_OF_RESOURCES There is not resource pool memory to store the matching results. + +**/ +EFI_STATUS +BdsConnectAllDrivers ( + VOID + ); + +/** + Return the value of a global variable defined by its VariableName. + The variable must be defined with the VendorGuid gEfiGlobalVariableGuid. + + @param VariableName A Null-terminated string that is the name of the vendor's + variable. + @param DefaultValue Value returned by the function if the variable does not exist + @param DataSize On input, the size in bytes of the return Data buffer. + On output the size of data returned in Data. + @param Value Value read from the UEFI Variable or copy of the default value + if the UEFI Variable does not exist + + @retval EFI_SUCCESS All drivers have been connected + @retval EFI_NOT_FOUND No handles match the search. + @retval EFI_OUT_OF_RESOURCES There is not resource pool memory to store the matching results. + +**/ +EFI_STATUS +GetGlobalEnvironmentVariable ( + IN CONST CHAR16* VariableName, + IN VOID* DefaultValue, + IN OUT UINTN* Size, + OUT VOID** Value + ); + +/** + Return the value of the variable defined by its VariableName and VendorGuid + + @param VariableName A Null-terminated string that is the name of the vendor's + variable. + @param VendorGuid A unique identifier for the vendor. + @param DefaultValue Value returned by the function if the variable does not exist + @param DataSize On input, the size in bytes of the return Data buffer. + On output the size of data returned in Data. + @param Value Value read from the UEFI Variable or copy of the default value + if the UEFI Variable does not exist + + @retval EFI_SUCCESS All drivers have been connected + @retval EFI_NOT_FOUND No handles match the search. + @retval EFI_OUT_OF_RESOURCES There is not resource pool memory to store the matching results. + +**/ +EFI_STATUS +GetEnvironmentVariable ( + IN CONST CHAR16* VariableName, + IN EFI_GUID* VendorGuid, + IN VOID* DefaultValue, + IN OUT UINTN* Size, + OUT VOID** Value + ); + +EFI_STATUS +BootOptionFromLoadOptionIndex ( + IN UINT16 LoadOptionIndex, + OUT BDS_LOAD_OPTION** BdsLoadOption + ); + +EFI_STATUS +BootOptionFromLoadOptionVariable ( + IN CHAR16* BootVariableName, + OUT BDS_LOAD_OPTION** BdsLoadOption + ); + +EFI_STATUS +BootOptionToLoadOptionVariable ( + IN BDS_LOAD_OPTION* BdsLoadOption + ); + +UINT16 +BootOptionAllocateBootIndex ( + VOID + ); + +/** + Start an EFI Application from a Device Path + + @param ParentImageHandle Handle of the calling image + @param DevicePath Location of the EFI Application + + @retval EFI_SUCCESS All drivers have been connected + @retval EFI_NOT_FOUND The Linux kernel Device Path has not been found + @retval EFI_OUT_OF_RESOURCES There is not enough resource memory to store the matching results. + +**/ +EFI_STATUS +BdsStartEfiApplication ( + IN EFI_HANDLE ParentImageHandle, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN UINTN LoadOptionsSize, + IN VOID* LoadOptions + ); + +EFI_STATUS +BdsLoadImage ( + IN EFI_DEVICE_PATH *DevicePath, + IN EFI_ALLOCATE_TYPE Type, + IN OUT EFI_PHYSICAL_ADDRESS* Image, + OUT UINTN *FileSize + ); + +/** + * Call BS.ExitBootServices with the appropriate Memory Map information + */ +EFI_STATUS +ShutdownUefiBootServices ( + VOID + ); + +/** + Locate an EFI application in a the Firmware Volumes by its name + + @param EfiAppGuid Guid of the EFI Application into the Firmware Volume + @param DevicePath EFI Device Path of the EFI application + + @return EFI_SUCCESS The function completed successfully. + @return EFI_NOT_FOUND The protocol could not be located. + @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. + +**/ +EFI_STATUS +LocateEfiApplicationInFvByName ( + IN CONST CHAR16* EfiAppName, + OUT EFI_DEVICE_PATH **DevicePath + ); + +/** + Locate an EFI application in a the Firmware Volumes by its GUID + + @param EfiAppGuid Guid of the EFI Application into the Firmware Volume + @param DevicePath EFI Device Path of the EFI application + + @return EFI_SUCCESS The function completed successfully. + @return EFI_NOT_FOUND The protocol could not be located. + @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. + +**/ +EFI_STATUS +LocateEfiApplicationInFvByGuid ( + IN CONST EFI_GUID *EfiAppGuid, + OUT EFI_DEVICE_PATH **DevicePath + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h new file mode 100644 index 00000000..5c7d7e26 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h @@ -0,0 +1,31 @@ +/** @file + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __DEFAULT_EXCEPTION_HANDLER_LIB_H__ +#define __DEFAULT_EXCEPTION_HANDLER_LIB_H__ + +/** + This is the default action to take on an unexpected exception + + @param ExceptionType Type of the exception + @param SystemContext Register state at the time of the Exception + +**/ +VOID +DefaultExceptionHandler ( + IN EFI_EXCEPTION_TYPE ExceptionType, + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ); + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/SemihostLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/SemihostLib.h new file mode 100644 index 00000000..4a91593e --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/SemihostLib.h @@ -0,0 +1,138 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions copyright (c) 2011, 2012, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SEMIHOSTING_H__ +#define __SEMIHOSTING_H__ + +/* + * + * Please refer to ARM RVDS 3.0 Compiler and Libraries Guide for more information + * about the semihosting interface. + * + */ + +#define SEMIHOST_FILE_MODE_READ (0 << 2) +#define SEMIHOST_FILE_MODE_WRITE (1 << 2) +#define SEMIHOST_FILE_MODE_APPEND (2 << 2) +#define SEMIHOST_FILE_MODE_UPDATE (1 << 1) +#define SEMIHOST_FILE_MODE_BINARY (1 << 0) +#define SEMIHOST_FILE_MODE_ASCII (0 << 0) + +BOOLEAN +SemihostConnectionSupported ( + VOID + ); + +RETURN_STATUS +SemihostFileOpen ( + IN CHAR8 *FileName, + IN UINT32 Mode, + OUT UINTN *FileHandle + ); + +RETURN_STATUS +SemihostFileSeek ( + IN UINTN FileHandle, + IN UINTN Offset + ); + +RETURN_STATUS +SemihostFileRead ( + IN UINTN FileHandle, + IN OUT UINTN *Length, + OUT VOID *Buffer + ); + +RETURN_STATUS +SemihostFileWrite ( + IN UINTN FileHandle, + IN OUT UINTN *Length, + IN VOID *Buffer + ); + +RETURN_STATUS +SemihostFileClose ( + IN UINTN FileHandle + ); + +RETURN_STATUS +SemihostFileLength ( + IN UINTN FileHandle, + OUT UINTN *Length + ); + +/** + Get a temporary name for a file from the host running the debug agent. + + @param[out] Buffer Pointer to the buffer where the temporary name has to + be stored + @param[in] Identifier File name identifier (integer in the range 0 to 255) + @param[in] Length Length of the buffer to store the temporary name + + @retval RETURN_SUCCESS Temporary name returned + @retval RETURN_INVALID_PARAMETER Invalid buffer address + @retval RETURN_ABORTED Temporary name not returned + +**/ +RETURN_STATUS +SemihostFileTmpName( + OUT VOID *Buffer, + IN UINT8 Identifier, + IN UINTN Length + ); + +RETURN_STATUS +SemihostFileRemove ( + IN CHAR8 *FileName + ); + +/** + Rename a specified file. + + @param[in] FileName Name of the file to rename. + @param[in] NewFileName The new name of the file. + + @retval RETURN_SUCCESS File Renamed + @retval RETURN_INVALID_PARAMETER Either the current or the new name is not specified + @retval RETURN_ABORTED Rename failed + +**/ +RETURN_STATUS +SemihostFileRename( + IN CHAR8 *FileName, + IN CHAR8 *NewFileName + ); + +CHAR8 +SemihostReadCharacter ( + VOID + ); + +VOID +SemihostWriteCharacter ( + IN CHAR8 Character + ); + +VOID +SemihostWriteString ( + IN CHAR8 *String + ); + +UINT32 +SemihostSystem ( + IN CHAR8 *CommandLine + ); + +#endif // __SEMIHOSTING_H__ diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/UncachedMemoryAllocationLib.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/UncachedMemoryAllocationLib.h new file mode 100644 index 00000000..a49d8d3a --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Library/UncachedMemoryAllocationLib.h @@ -0,0 +1,665 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __UNCACHED_MEMORY_ALLOCATION_LIB_H__ +#define __UNCACHED_MEMORY_ALLOCATION_LIB_H__ + +/** + Converts a cached or uncached address to a physical address suitable for use in SoC registers. + + @param VirtualAddress The pointer to convert. + + @return The physical address of the supplied virtual pointer. + +**/ +EFI_PHYSICAL_ADDRESS +ConvertToPhysicalAddress ( + IN VOID *VirtualAddress + ); + +/** + Converts a cached or uncached address to a cached address. + + @param Address The pointer to convert. + + @return The address of the cached memory location corresponding to the input address. + +**/ +VOID * +ConvertToCachedAddress ( + IN VOID *Address + ); + +/** + Converts a cached or uncached address to an uncached address. + + @param Address The pointer to convert. + + @return The address of the uncached memory location corresponding to the input address. + +**/ +VOID * +ConvertToUncachedAddress ( + IN VOID *Address + ); + +/** + Allocates one or more 4KB pages of type EfiBootServicesData. + + Allocates the number of 4KB pages of type EfiBootServicesData and returns a pointer to the + allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL + is returned. If there is not enough memory remaining to satisfy the request, then NULL is + returned. + + @param Pages The number of 4 KB pages to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocatePages ( + IN UINTN Pages + ); + +/** + Allocates one or more 4KB pages of type EfiRuntimeServicesData. + + Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the + allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL + is returned. If there is not enough memory remaining to satisfy the request, then NULL is + returned. + + @param Pages The number of 4 KB pages to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateRuntimePages ( + IN UINTN Pages + ); + +/** + Allocates one or more 4KB pages of type EfiReservedMemoryType. + + Allocates the number of 4KB pages of type EfiReservedMemoryType and returns a pointer to the + allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL + is returned. If there is not enough memory remaining to satisfy the request, then NULL is + returned. + + @param Pages The number of 4 KB pages to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateReservedPages ( + IN UINTN Pages + ); + +/** + Frees one or more 4KB pages that were previously allocated with one of the page allocation + functions in the Memory Allocation Library. + + Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer. Buffer + must have been allocated on a previous call to the page allocation services of the Memory + Allocation Library. + If Buffer was not allocated with a page allocation function in the Memory Allocation Library, + then ASSERT(). + If Pages is zero, then ASSERT(). + + @param Buffer Pointer to the buffer of pages to free. + @param Pages The number of 4 KB pages to free. + +**/ +VOID +EFIAPI +UncachedFreePages ( + IN VOID *Buffer, + IN UINTN Pages + ); + +/** + Allocates one or more 4KB pages of type EfiBootServicesData at a specified alignment. + + Allocates the number of 4KB pages specified by Pages of type EfiBootServicesData with an + alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is + returned. If there is not enough memory at the specified alignment remaining to satisfy the + request, then NULL is returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param Pages The number of 4 KB pages to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedPages ( + IN UINTN Pages, + IN UINTN Alignment + ); + +/** + Allocates one or more 4KB pages of type EfiRuntimeServicesData at a specified alignment. + + Allocates the number of 4KB pages specified by Pages of type EfiRuntimeServicesData with an + alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is + returned. If there is not enough memory at the specified alignment remaining to satisfy the + request, then NULL is returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param Pages The number of 4 KB pages to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedRuntimePages ( + IN UINTN Pages, + IN UINTN Alignment + ); + +/** + Allocates one or more 4KB pages of type EfiReservedMemoryType at a specified alignment. + + Allocates the number of 4KB pages specified by Pages of type EfiReservedMemoryType with an + alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is + returned. If there is not enough memory at the specified alignment remaining to satisfy the + request, then NULL is returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param Pages The number of 4 KB pages to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedReservedPages ( + IN UINTN Pages, + IN UINTN Alignment + ); + +/** + Frees one or more 4KB pages that were previously allocated with one of the aligned page + allocation functions in the Memory Allocation Library. + + Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer. Buffer + must have been allocated on a previous call to the aligned page allocation services of the Memory + Allocation Library. + If Buffer was not allocated with an aligned page allocation function in the Memory Allocation + Library, then ASSERT(). + If Pages is zero, then ASSERT(). + + @param Buffer Pointer to the buffer of pages to free. + @param Pages The number of 4 KB pages to free. + +**/ +VOID +EFIAPI +UncachedFreeAlignedPages ( + IN VOID *Buffer, + IN UINTN Pages + ); + +/** + Allocates a buffer of type EfiBootServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiBootServicesData and returns a + pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is + returned. If there is not enough memory remaining to satisfy the request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocatePool ( + IN UINTN AllocationSize + ); + +/** + Allocates a buffer of type EfiRuntimeServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData and returns + a pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is + returned. If there is not enough memory remaining to satisfy the request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateRuntimePool ( + IN UINTN AllocationSize + ); + +/** + Allocates a buffer of type EfieservedMemoryType. + + Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType and returns + a pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is + returned. If there is not enough memory remaining to satisfy the request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateReservedPool ( + IN UINTN AllocationSize + ); + +/** + Allocates and zeros a buffer of type EfiBootServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, clears the + buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a + valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the + request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate and zero. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateZeroPool ( + IN UINTN AllocationSize + ); + +/** + Allocates and zeros a buffer of type EfiRuntimeServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, clears the + buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a + valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the + request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate and zero. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateRuntimeZeroPool ( + IN UINTN AllocationSize + ); + +/** + Allocates and zeros a buffer of type EfiReservedMemoryType. + + Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, clears the + buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a + valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the + request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate and zero. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateReservedZeroPool ( + IN UINTN AllocationSize + ); + +/** + Copies a buffer to an allocated buffer of type EfiBootServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, copies + AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the + allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there + is not enough memory remaining to satisfy the request, then NULL is returned. + If Buffer is NULL, then ASSERT(). + If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). + + @param AllocationSize The number of bytes to allocate and zero. + @param Buffer The buffer to copy to the allocated buffer. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateCopyPool ( + IN UINTN AllocationSize, + IN CONST VOID *Buffer + ); + +/** + Copies a buffer to an allocated buffer of type EfiRuntimeServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, copies + AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the + allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there + is not enough memory remaining to satisfy the request, then NULL is returned. + If Buffer is NULL, then ASSERT(). + If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). + + @param AllocationSize The number of bytes to allocate and zero. + @param Buffer The buffer to copy to the allocated buffer. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateRuntimeCopyPool ( + IN UINTN AllocationSize, + IN CONST VOID *Buffer + ); + +/** + Copies a buffer to an allocated buffer of type EfiReservedMemoryType. + + Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, copies + AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the + allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there + is not enough memory remaining to satisfy the request, then NULL is returned. + If Buffer is NULL, then ASSERT(). + If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). + + @param AllocationSize The number of bytes to allocate and zero. + @param Buffer The buffer to copy to the allocated buffer. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateReservedCopyPool ( + IN UINTN AllocationSize, + IN CONST VOID *Buffer + ); + +/** + Frees a buffer that was previously allocated with one of the pool allocation functions in the + Memory Allocation Library. + + Frees the buffer specified by Buffer. Buffer must have been allocated on a previous call to the + pool allocation services of the Memory Allocation Library. + If Buffer was not allocated with a pool allocation function in the Memory Allocation Library, + then ASSERT(). + + @param Buffer Pointer to the buffer to free. + +**/ +VOID +EFIAPI +UncachedFreePool ( + IN VOID *Buffer + ); + +/** + Allocates a buffer of type EfiBootServicesData at a specified alignment. + + Allocates the number bytes specified by AllocationSize of type EfiBootServicesData with an + alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0, + then a valid buffer of 0 size is returned. If there is not enough memory at the specified + alignment remaining to satisfy the request, then NULL is returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param AllocationSize The number of bytes to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedPool ( + IN UINTN AllocationSize, + IN UINTN Alignment + ); + +/** + Allocates a buffer of type EfiRuntimeServicesData at a specified alignment. + + Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData with an + alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0, + then a valid buffer of 0 size is returned. If there is not enough memory at the specified + alignment remaining to satisfy the request, then NULL is returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param AllocationSize The number of bytes to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedRuntimePool ( + IN UINTN AllocationSize, + IN UINTN Alignment + ); + +/** + Allocates a buffer of type EfieservedMemoryType at a specified alignment. + + Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType with an + alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0, + then a valid buffer of 0 size is returned. If there is not enough memory at the specified + alignment remaining to satisfy the request, then NULL is returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param AllocationSize The number of bytes to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedReservedPool ( + IN UINTN AllocationSize, + IN UINTN Alignment + ); + +/** + Allocates and zeros a buffer of type EfiBootServicesData at a specified alignment. + + Allocates the number bytes specified by AllocationSize of type EfiBootServicesData with an + alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the + allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there + is not enough memory at the specified alignment remaining to satisfy the request, then NULL is + returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param AllocationSize The number of bytes to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedZeroPool ( + IN UINTN AllocationSize, + IN UINTN Alignment + ); + +/** + Allocates and zeros a buffer of type EfiRuntimeServicesData at a specified alignment. + + Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData with an + alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the + allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there + is not enough memory at the specified alignment remaining to satisfy the request, then NULL is + returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param AllocationSize The number of bytes to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedRuntimeZeroPool ( + IN UINTN AllocationSize, + IN UINTN Alignment + ); + +/** + Allocates and zeros a buffer of type EfieservedMemoryType at a specified alignment. + + Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType with an + alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the + allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there + is not enough memory at the specified alignment remaining to satisfy the request, then NULL is + returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param AllocationSize The number of bytes to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedReservedZeroPool ( + IN UINTN AllocationSize, + IN UINTN Alignment + ); + +/** + Copies a buffer to an allocated buffer of type EfiBootServicesData at a specified alignment. + + Allocates the number bytes specified by AllocationSize of type EfiBootServicesData type with an + alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0, + then a valid buffer of 0 size is returned. If there is not enough memory at the specified + alignment remaining to satisfy the request, then NULL is returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param AllocationSize The number of bytes to allocate. + @param Buffer The buffer to copy to the allocated buffer. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedCopyPool ( + IN UINTN AllocationSize, + IN CONST VOID *Buffer, + IN UINTN Alignment + ); + +/** + Copies a buffer to an allocated buffer of type EfiRuntimeServicesData at a specified alignment. + + Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData type with an + alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0, + then a valid buffer of 0 size is returned. If there is not enough memory at the specified + alignment remaining to satisfy the request, then NULL is returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param AllocationSize The number of bytes to allocate. + @param Buffer The buffer to copy to the allocated buffer. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedRuntimeCopyPool ( + IN UINTN AllocationSize, + IN CONST VOID *Buffer, + IN UINTN Alignment + ); + +/** + Copies a buffer to an allocated buffer of type EfiReservedMemoryType at a specified alignment. + + Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType type with an + alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0, + then a valid buffer of 0 size is returned. If there is not enough memory at the specified + alignment remaining to satisfy the request, then NULL is returned. + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + + @param AllocationSize The number of bytes to allocate. + @param Buffer The buffer to copy to the allocated buffer. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +UncachedAllocateAlignedReservedCopyPool ( + IN UINTN AllocationSize, + IN CONST VOID *Buffer, + IN UINTN Alignment + ); + +/** + Frees a buffer that was previously allocated with one of the aligned pool allocation functions + in the Memory Allocation Library. + + Frees the buffer specified by Buffer. Buffer must have been allocated on a previous call to the + aligned pool allocation services of the Memory Allocation Library. + If Buffer was not allocated with an aligned pool allocation function in the Memory Allocation + Library, then ASSERT(). + + @param Buffer Pointer to the buffer to free. + +**/ +VOID +EFIAPI +UncachedFreeAlignedPool ( + IN VOID *Buffer + ); + +VOID +EFIAPI +UncachedSafeFreePool ( + IN VOID *Buffer + ); + +#endif // __UNCACHED_MEMORY_ALLOCATION_LIB_H__ diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Ppi/ArmMpCoreInfo.h b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Ppi/ArmMpCoreInfo.h new file mode 100644 index 00000000..fdacd811 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Include/Ppi/ArmMpCoreInfo.h @@ -0,0 +1,58 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARM_MP_CORE_INFO_PPI_H__ +#define __ARM_MP_CORE_INFO_PPI_H__ + +#include + +#define ARM_MP_CORE_INFO_PPI_GUID \ + { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} } + +/** + This service of the EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into + permanent memory. + + @param PeiServices Pointer to the PEI Services Table. + @param TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the + Temporary RAM contents. + @param PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the + Temporary RAM contents. + @param CopySize Amount of memory to migrate from temporary to permanent memory. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when + TemporaryMemoryBase > PermanentMemoryBase. + +**/ +typedef +EFI_STATUS +(EFIAPI * ARM_MP_CORE_INFO_GET) ( + OUT UINTN *ArmCoreCount, + OUT ARM_CORE_INFO **ArmCoreTable +); + +/// +/// This service abstracts the ability to migrate contents of the platform early memory store. +/// Note: The name EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI is different from the current PI 1.2 spec. +/// This PPI was optional. +/// +typedef struct { + ARM_MP_CORE_INFO_GET GetMpCoreInfo; +} ARM_MP_CORE_INFO_PPI; + +extern EFI_GUID gArmMpCoreInfoPpiGuid; +extern EFI_GUID gArmMpCoreInfoGuid; + +#endif diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c new file mode 100644 index 00000000..b81293c5 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c @@ -0,0 +1,292 @@ +/** @file + Generic ARM implementation of TimerLib.h + + Copyright (c) 2011-2016, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +#include +#include +#include +#include +#include +#include +#include + +#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U) + +// Select appropriate multiply function for platform architecture. +#ifdef MDE_CPU_ARM +#define MultU64xN MultU64x32 +#else +#define MultU64xN MultU64x64 +#endif + + +RETURN_STATUS +EFIAPI +TimerConstructor ( + VOID + ) +{ + // + // Check if the ARM Generic Timer Extension is implemented. + // + if (ArmIsArchTimerImplemented ()) { + + // + // Check if Architectural Timer frequency is pre-determined by the platform + // (ie. nonzero). + // + if (PcdGet32 (PcdArmArchTimerFreqInHz) != 0) { + // + // Check if ticks/uS is not 0. The Architectural timer runs at constant + // frequency, irrespective of CPU frequency. According to Generic Timer + // Ref manual, lower bound of the frequency is in the range of 1-10MHz. + // + ASSERT (TICKS_PER_MICRO_SEC); + +#ifdef MDE_CPU_ARM + // + // Only set the frequency for ARMv7. We expect the secure firmware to + // have already done it. + // If the security extension is not implemented, set Timer Frequency + // here. + // + if ((ArmReadIdPfr1 () & ARM_PFR1_SEC) == 0x0) { + ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz)); + } +#endif + } + + // + // Architectural Timer Frequency must be set in Secure privileged + // mode (if secure extension is supported). + // If the reset value (0) is returned, just ASSERT. + // + ASSERT (ArmGenericTimerGetTimerFreq () != 0); + + } else { + DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library cannot be used.\n")); + ASSERT (0); + } + + return RETURN_SUCCESS; +} + +/** + A local utility function that returns the PCD value, if specified. + Otherwise it defaults to ArmGenericTimerGetTimerFreq. + + @return The timer frequency. + +**/ +STATIC +UINTN +EFIAPI +GetPlatformTimerFreq ( + ) +{ + UINTN TimerFreq; + + TimerFreq = PcdGet32 (PcdArmArchTimerFreqInHz); + if (TimerFreq == 0) { + TimerFreq = ArmGenericTimerGetTimerFreq (); + } + return TimerFreq; +} + + +/** + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return The value of MicroSeconds input. + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + UINT64 TimerTicks64; + UINT64 SystemCounterVal; + + // Calculate counter ticks that represent requested delay: + // = MicroSeconds x TICKS_PER_MICRO_SEC + // = MicroSeconds x Frequency.10^-6 + TimerTicks64 = DivU64x32 ( + MultU64xN ( + MicroSeconds, + GetPlatformTimerFreq () + ), + 1000000U + ); + + // Read System Counter value + SystemCounterVal = ArmGenericTimerGetSystemCount (); + + TimerTicks64 += SystemCounterVal; + + // Wait until delay count expires. + while (SystemCounterVal < TimerTicks64) { + SystemCounterVal = ArmGenericTimerGetSystemCount (); + } + + return MicroSeconds; +} + + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + When the timer frequency is 1MHz, each tick corresponds to 1 microsecond. + Therefore, the nanosecond delay will be rounded up to the nearest 1 microsecond. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return The value of NanoSeconds inputed. + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + UINTN MicroSeconds; + + // Round up to 1us Tick Number + MicroSeconds = NanoSeconds / 1000; + MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1; + + MicroSecondDelay (MicroSeconds); + + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + The counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + // Just return the value of system count + return ArmGenericTimerGetSystemCount (); +} + +/** + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter starts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end with + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartValue + is less than EndValue, then the performance counter counts up. If StartValue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a StartValue + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with before + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue != NULL) { + // Timer starts at 0 + *StartValue = (UINT64)0ULL ; + } + + if (EndValue != NULL) { + // Timer counts up. + *EndValue = 0xFFFFFFFFFFFFFFFFUL; + } + + return (UINT64)ArmGenericTimerGetTimerFreq (); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance counter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + UINT32 TimerFreq; + + TimerFreq = GetPlatformTimerFreq (); + // + // Ticks + // Time = --------- x 1,000,000,000 + // Frequency + // + NanoSeconds = MultU64xN ( + DivU64x32Remainder ( + Ticks, + TimerFreq, + &Remainder), + 1000000000U + ); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds += DivU64x32 ( + MultU64xN ( + (UINT64) Remainder, + 1000000000U), + TimerFreq + ); + + return NanoSeconds; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf new file mode 100644 index 00000000..03a4b1ef --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf @@ -0,0 +1,38 @@ +#/** @file +# +# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmArchTimerLib + FILE_GUID = 82da1b44-d2d6-4a7d-bbf0-a0cb67964034 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = TimerLib + CONSTRUCTOR = TimerConstructor + +[Sources.common] + ArmArchTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + DebugLib + ArmLib + BaseLib + ArmGenericTimerCounterLib + +[Pcd] + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c new file mode 100644 index 00000000..0759e38c --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c @@ -0,0 +1,131 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include +#include +#include +#include + +STATIC +VOID +CacheRangeOperation ( + IN VOID *Start, + IN UINTN Length, + IN LINE_OPERATION LineOperation, + IN UINTN LineLength + ) +{ + UINTN ArmCacheLineAlignmentMask = LineLength - 1; + + // Align address (rounding down) + UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask); + UINTN EndAddress = (UINTN)Start + Length; + + // Perform the line operation on an address in each cache line + while (AlignedAddress < EndAddress) { + LineOperation(AlignedAddress); + AlignedAddress += LineLength; + } + ArmDataSynchronizationBarrier (); +} + +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ) +{ + ASSERT (FALSE); +} + +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ + ASSERT (FALSE); +} + +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA, + ArmDataCacheLineLength ()); + CacheRangeOperation (Address, Length, + ArmInvalidateInstructionCacheEntryToPoUByMVA, + ArmInstructionCacheLineLength ()); + + ArmInstructionSynchronizationBarrier (); + + return Address; +} + +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ) +{ + ASSERT (FALSE); +} + +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA, + ArmDataCacheLineLength ()); + return Address; +} + +VOID +EFIAPI +WriteBackDataCache ( + VOID + ) +{ + ASSERT (FALSE); +} + +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA, + ArmDataCacheLineLength ()); + return Address; +} + +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA, + ArmDataCacheLineLength ()); + return Address; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf new file mode 100644 index 00000000..d5199729 --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf @@ -0,0 +1,33 @@ +#/** @file +# Implement CacheMaintenanceLib for ARM architectures +# +# Copyright (c) 2008, Apple Inc. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmCacheMaintenanceLib + FILE_GUID = 1A20BE1F-33AD-450C-B49A-7123FCA8B7F9 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = CacheMaintenanceLib + +[Sources.common] + ArmCacheMaintenanceLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + BaseLib diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c new file mode 100644 index 00000000..3ecae77d --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c @@ -0,0 +1,48 @@ +/** @file + Default exception handler + + Copyright (c) 2014, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD + License which accompanies this distribution. The full text of the license may + be found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include + +/** + Place a disassembly of of **OpCodePtr into buffer, and update OpCodePtr to + point to next instruction. + + @param OpCodePtrPtr Pointer to pointer of instruction to disassemble. + @param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream + @param Extended TRUE dump hex for instruction too. + @param ItBlock Size of IT Block + @param Buf Buffer to sprintf disassembly into. + @param Size Size of Buf in bytes. + +**/ +VOID +DisassembleInstruction ( + IN UINT8 **OpCodePtr, + IN BOOLEAN Thumb, + IN BOOLEAN Extended, + IN OUT UINT32 *ItBlock, + OUT CHAR8 *Buf, + OUT UINTN Size + ) +{ + // Not yet supported for AArch64. + // Put error in the buffer as we have no return code and the buffer may be + // printed directly so needs a '\0'. + AsciiSPrint (Buf, Size, "AArch64 not supported"); + return; +} diff --git a/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c new file mode 100644 index 00000000..29d9414a --- /dev/null +++ b/FW/PlatformBuildLab/Max/edk2/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c @@ -0,0 +1,455 @@ +/** @file + Default exception handler + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include + +CHAR8 *gCondition[] = { + "EQ", + "NE", + "CS", + "CC", + "MI", + "PL", + "VS", + "VC", + "HI", + "LS", + "GE", + "LT", + "GT", + "LE", + "", + "2" +}; + +#define COND(_a) gCondition[((_a) >> 28)] + +CHAR8 *gReg[] = { + "r0", + "r1", + "r2", + "r3", + "r4", + "r5", + "r6", + "r7", + "r8", + "r9", + "r10", + "r11", + "r12", + "sp", + "lr", + "pc" +}; + +CHAR8 *gLdmAdr[] = { + "DA", + "IA", + "DB", + "IB" +}; + +CHAR8 *gLdmStack[] = { + "FA", + "FD", + "EA", + "ED" +}; + +#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)]) + + +#define SIGN(_U) ((_U) ? "" : "-") +#define WRITE(_W) ((_W) ? "!" : "") +#define BYTE(_B) ((_B) ? "B":"") +#define USER(_B) ((_B) ? "^" : "") + +CHAR8 mMregListStr[4*15 + 1]; + +CHAR8 * +MRegList ( + UINT32 OpCode + ) +{ + UINTN Index, Start, End; + BOOLEAN First; + + mMregListStr[0] = '\0'; + AsciiStrCatS (mMregListStr, sizeof mMregListStr, "{"); + for (Index = 0, First = TRUE; Index <= 15; Index++) { + if ((OpCode & (1 << Index)) != 0) { + Start = End = Index; + for (Index++; ((OpCode & (1 << Index)) != 0) && Index <= 15; Index++) { + End = Index; + } + + if (!First) { + AsciiStrCatS (mMregListStr, sizeof mMregListStr, ","); + } else { + First = FALSE; + } + + if (Start == End) { + AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[Start]); + AsciiStrCatS (mMregListStr, sizeof mMregListStr, ", "); + } else { + AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[Start]); + AsciiStrCatS (mMregListStr, sizeof mMregListStr, "-"); + AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[End]); + } + } + } + if (First) { + AsciiStrCatS (mMregListStr, sizeof mMregListStr, "ERROR"); + } + AsciiStrCatS (mMregListStr, sizeof mMregListStr, "}"); + + // BugBug: Make caller pass in buffer it is cleaner + return mMregListStr; +} + +CHAR8 * +FieldMask ( + IN UINT32 Mask + ) +{ + return ""; +} + +UINT32 +RotateRight ( + IN UINT32 Op, + IN UINT32 Shift + ) +{ + return (Op >> Shift) | (Op << (32 - Shift)); +} + + +/** + Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to + point to next instructin. + + We cheat and only decode instructions that access + memory. If the instruction is not found we dump the instruction in hex. + + @param OpCodePtr Pointer to pointer of ARM instruction to disassemble. + @param Buf Buffer to sprintf disassembly into. + @param Size Size of Buf in bytes. + @param Extended TRUE dump hex for instruction too. + +**/ +VOID +DisassembleArmInstruction ( + IN UINT32 **OpCodePtr, + OUT CHAR8 *Buf, + OUT UINTN Size, + IN BOOLEAN Extended + ) +{ + UINT32 OpCode = **OpCodePtr; + CHAR8 *Type, *Root; + BOOLEAN I, P, U, B, W, L, S, H; + UINT32 Rn, Rd, Rm; + UINT32 imode, offset_8, offset_12; + UINT32 Index; + UINT32 shift_imm, shift; + + I = (OpCode & BIT25) == BIT25; + P = (OpCode & BIT24) == BIT24; + U = (OpCode & BIT23) == BIT23; + B = (OpCode & BIT22) == BIT22; // Also called S + W = (OpCode & BIT21) == BIT21; + L = (OpCode & BIT20) == BIT20; + S = (OpCode & BIT6) == BIT6; + H = (OpCode & BIT5) == BIT5; + Rn = (OpCode >> 16) & 0xf; + Rd = (OpCode >> 12) & 0xf; + Rm = (OpCode & 0xf); + + + if (Extended) { + Index = AsciiSPrint (Buf, Size, "0x%08x ", OpCode); + Buf += Index; + Size -= Index; + } + + // LDREX, STREX + if ((OpCode & 0x0fe000f0) == 0x01800090) { + if (L) { + // A4.1.27 LDREX{} , [] + AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]); + } else { + // A4.1.103 STREX{} , , [] + AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]); + } + return; + } + + // LDM/STM + if ((OpCode & 0x0e000000) == 0x08000000) { + if (L) { + // A4.1.20 LDM{} {!}, + // A4.1.21 LDM{} , ^ + // A4.1.22 LDM{} {!}, ^ + AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B)); + } else { + // A4.1.97 STM{} {!}, + // A4.1.98 STM{} , ^ + AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B)); + } + return; + } + + // LDR/STR Address Mode 2 + if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) { + offset_12 = OpCode & 0xfff; + if ((OpCode & 0xfd70f000 ) == 0xf550f000) { + Index = AsciiSPrint (Buf, Size, "PLD"); + } else { + Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]); + } + if (P) { + if (!I) { + // A5.2.2 [, #+/-] + // A5.2.5 [, #+/-] + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (U), offset_12, WRITE (W)); + } else if ((OpCode & 0x03000ff0) == 0x03000000) { + // A5.2.3 [, +/-] + // A5.2.6 [, +/-]! + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (U), WRITE (W)); + } else { + // A5.2.4 [, +/-, LSL #] + // A5.2.7 [, +/-, LSL #]! + shift_imm = (OpCode >> 7) & 0x1f; + shift = (OpCode >> 5) & 0x3; + if (shift == 0x0) { + Type = "LSL"; + } else if (shift == 0x1) { + Type = "LSR"; + if (shift_imm == 0) { + shift_imm = 32; + } + } else if (shift == 0x12) { + Type = "ASR"; + } else if (shift_imm == 0) { + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W)); + return; + } else { + Type = "ROR"; + } + + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W)); + } + } else { // !P + if (!I) { + // A5.2.8 [], #+/- + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (U), offset_12); + } else if ((OpCode & 0x03000ff0) == 0x03000000) { + // A5.2.9 [], +/- + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]); + } else { + // A5.2.10 [], +/-, LSL # + shift_imm = (OpCode >> 7) & 0x1f; + shift = (OpCode >> 5) & 0x3; + + if (shift == 0x0) { + Type = "LSL"; + } else if (shift == 0x1) { + Type = "LSR"; + if (shift_imm == 0) { + shift_imm = 32; + } + } else if (shift == 0x12) { + Type = "ASR"; + } else if (shift_imm == 0) { + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (U), gReg[Rm]); + // FIx me + return; + } else { + Type = "ROR"; + } + + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm); + } + } + return; + } + + if ((OpCode & 0x0e000000) == 0x00000000) { + // LDR/STR address mode 3 + // LDR|STR{}H|SH|SB|D , + if (L) { + if (!S) { + Root = "LDR%aH %a, "; + } else if (!H) { + Root = "LDR%aSB %a, "; + } else { + Root = "LDR%aSH %a, "; + } + } else { + if (!S) { + Root = "STR%aH %a "; + } else if (!H) { + Root = "LDR%aD %a "; + } else { + Root = "STR%aD %a "; + } + } + + Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]); + + S = (OpCode & BIT6) == BIT6; + H = (OpCode & BIT5) == BIT5; + offset_8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff; + if (P & !W) { + // Immediate offset/index + if (B) { + // A5.3.2 [, #+/-] + // A5.3.4 [, #+/-]! + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (U), offset_8, WRITE (W)); + } else { + // A5.3.3 [, +/-] + // A5.3.5 [, +/-]! + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W)); + } + } else { + // Register offset/index + if (B) { + // A5.3.6 [], #+/- + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (U), offset_8); + } else { + // A5.3.7 [], +/- + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]); + } + } + return; + } + + if ((OpCode & 0x0fb000f0) == 0x01000050) { + // A4.1.108 SWP SWP{}B , , [] + // A4.1.109 SWPB SWP{}B , , [] + AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]); + return; + } + + if ((OpCode & 0xfe5f0f00) == 0xf84d0500) { + // A4.1.90 SRS SRS #{!} + AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W)); + return; + } + + if ((OpCode & 0xfe500f00) == 0xf8100500) { + // A4.1.59 RFE {!} + AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W)); + return; + } + + if ((OpCode & 0xfff000f0) == 0xe1200070) { + // A4.1.7 BKPT + AsciiSPrint (Buf, Size, "BKPT %x", ((OpCode >> 8) | (OpCode & 0xf)) & 0xffff); + return; + } + + if ((OpCode & 0xfff10020) == 0xf1000000) { + // A4.1.16 CPS {, #} + if (((OpCode >> 6) & 0x7) == 0) { + AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f)); + } else { + imode = (OpCode >> 18) & 0x3; + Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a", (imode == 3) ? "ID":"IE", (OpCode & BIT8) ? "A":"", (OpCode & BIT7) ? "I":"", (OpCode & BIT6) ? "F":""); + if ((OpCode & BIT17) != 0) { + AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f); + } + } + return; + } + + if ((OpCode & 0x0f000000) == 0x0f000000) { + // A4.1.107 SWI{} + AsciiSPrint (Buf, Size, "SWI%a %x", COND (OpCode), OpCode & 0x00ffffff); + return; + } + + if ((OpCode & 0x0fb00000) == 0x01000000) { + // A4.1.38 MRS{} , CPSR MRS{} , SPSR + AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR"); + return; + } + + + if ((OpCode & 0x0db00000) == 0x03200000) { + // A4.1.38 MSR{} CPSR_, # MSR{} CPSR_, + if (I) { + // MSR{} CPSR_, # + AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), B ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2)); + } else { + // MSR{} CPSR_, + AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]); + } + return; + } + + if ((OpCode & 0xff000010) == 0xfe000000) { + // A4.1.13 CDP{} , , , , , + AsciiSPrint (Buf, Size, "CDP%a 0x%x, 0x%x, CR%d, CR%d, CR%d, 0x%x", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, Rn, Rd, Rm, (OpCode >> 5) &0x7); + return; + } + + if ((OpCode & 0x0e000000) == 0x0c000000) { + // A4.1.19 LDC and A4.1.96 SDC + if ((OpCode & 0xf0000000) == 0xf0000000) { + Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", L ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd); + } else { + Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd); + } + + if (!P) { + if (!W) { + // A5.5.5.5 [],