mirror of
https://github.com/Dasharo/MySPITest.git
synced 2026-03-06 14:57:28 -08:00
25974ee9dd
The update introduces a few chages, notably we test SPI functionality by programming registers directly instead of using HAL which does some things not optimally.
108 lines
4.1 KiB
C
108 lines
4.1 KiB
C
#include "main.h"
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#include "spi.h"
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#include <stdio.h>
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#include <stdbool.h>
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#include <string.h>
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#define STATE_WAIT_HEADER 0
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#define STATE_WAIT_STATE 1
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#define STATE_WAIT_STATE_LAST 2
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#define STATE_PAYLOAD_TRANSFER 3
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static __attribute__((aligned(32))) uint8_t ff_buffer[64];
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static __attribute__((aligned(32))) uint8_t waitstate_insert[4] = {0xff, 0xff, 0xff, 0xfe};
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static __attribute__((aligned(32))) uint8_t waitstate_hold[1] = {0x00};
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static __attribute__((aligned(32))) uint8_t waitstate_cancel[1] = {0x01};
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static __attribute__((aligned(32))) uint8_t trash[4] = {0};
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static __attribute__((aligned(32))) uint8_t header[4] = {0};
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static uint8_t state = STATE_WAIT_HEADER;
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static __attribute__((aligned(32))) uint8_t scratch_buffer[64] = {0};
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static uint8_t transfer_is_read = 0;
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static uint32_t transfer_length = 0;
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static void txdma_complete(DMA_HandleTypeDef *hdma)
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{
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SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
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return;
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switch (state) {
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case STATE_WAIT_HEADER:
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// Wait state got inserted while reading header.
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HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)waitstate_cancel, (uint32_t)&hspi->Instance->DR, sizeof waitstate_cancel);
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// We don't care what host sends during wait state, but we start DMA anyway to avoid overrun errors.
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HAL_DMA_PollForTransfer(hspi->hdmarx, HAL_DMA_FULL_TRANSFER, HAL_MAX_DELAY);
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HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)trash, sizeof trash);
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transfer_is_read = !!(header[0] & (1 << 7));
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transfer_length = (header[0] & 0x3f) + 1;
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state = STATE_WAIT_STATE_LAST;
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break;
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case STATE_WAIT_STATE_LAST:
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if (transfer_is_read) {
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HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)scratch_buffer, (uint32_t)&hspi->Instance->DR, transfer_length);
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HAL_DMA_PollForTransfer(hspi->hdmarx, HAL_DMA_FULL_TRANSFER, HAL_MAX_DELAY);
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HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)ff_buffer, transfer_length);
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} else {
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HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)ff_buffer, (uint32_t)&hspi->Instance->DR, transfer_length);
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HAL_DMA_PollForTransfer(hspi->hdmarx, HAL_DMA_FULL_TRANSFER, HAL_MAX_DELAY);
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HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)scratch_buffer, transfer_length);
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}
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state = STATE_PAYLOAD_TRANSFER;
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break;
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case STATE_PAYLOAD_TRANSFER:
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HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)waitstate_insert, (uint32_t)&hspi->Instance->DR, sizeof waitstate_insert);
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HAL_DMA_PollForTransfer(hspi->hdmarx, HAL_DMA_FULL_TRANSFER, HAL_MAX_DELAY);
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HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)header, sizeof header);
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state = STATE_WAIT_HEADER;
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break;
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}
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}
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void app_main() {
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SPI_HandleTypeDef *hspi = &hspi2;
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assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
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assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
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assert(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE);
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assert(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE);
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memset(ff_buffer, 0xff, sizeof ff_buffer);
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//hspi->hdmarx->XferCpltCallback = rxdma_complete;
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hspi->hdmatx->XferCpltCallback = txdma_complete;
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SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
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CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX | SPI_CR2_LDMATX);
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hspi->hdmarx->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hspi->hdmarx->ChannelIndex & 0x1CU))
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| (DMA_ISR_GIF1 << (hspi->hdmatx->ChannelIndex & 0x1CU));
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hspi->hdmarx->Instance->CNDTR = sizeof header;
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hspi->hdmarx->Instance->CPAR = (uint32_t)&hspi->Instance->DR;
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hspi->hdmarx->Instance->CMAR = (uint32_t)header;
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__HAL_DMA_ENABLE_IT(hspi->hdmarx, DMA_IT_TC | DMA_IT_TE);
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__HAL_DMA_ENABLE(hspi->hdmarx);
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SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
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//HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)waitstate_insert, (uint32_t)&hspi->Instance->DR, sizeof waitstate_insert);
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hspi->hdmatx->Instance->CNDTR = sizeof waitstate_insert;
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hspi->hdmatx->Instance->CPAR = (uint32_t)&hspi->Instance->DR;
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hspi->hdmatx->Instance->CMAR = (uint32_t)header;
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__HAL_DMA_ENABLE_IT(hspi->hdmatx, DMA_IT_TC | DMA_IT_TE);
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__HAL_DMA_ENABLE(hspi->hdmatx);
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SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
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__HAL_SPI_ENABLE(hspi);
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}
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