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207 Commits

Author SHA1 Message Date
Tim Northover eae1d34029 Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions. 
Patch by Chris Lidbury.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 15:17:49 +00:00
Richard Smith 1144af3c9b Fix integer undefined behavior due to signed left shift overflow in LLVM. 
Reviewed offline by chandlerc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 23:29:28 +00:00
Craig Topper 960fb74370 Remove unnecessary include of ARMGenInstrInfo.inc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-17 06:21:09 +00:00
Jim Grosbach fc1a161d76 Switch the fixed-length disassembler to be table-driven. 
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.

As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:

Time to compile at -O2 (averaged w/ hot caches):
  Previous: 35.5s
  New:       8.9s

TEXT size:
  Previous: 447,251
  New:      297,661

Builds in 25% of the time previously required and generates code 66% of
the size.

Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-14 19:06:05 +00:00
Jiangning Liu fd652df8b3 Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 08:29:50 +00:00
Jiangning Liu c1b7ca5ba2 Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 08:21:27 +00:00
Sylvestre Ledru c8e41c5917 Fix a typo (the the => the) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-23 08:51:15 +00:00
Richard Barton fae96f17b4 Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-10 12:51:09 +00:00
Chad Rosier 270e3625b2 Revert r159938 (and r159945) to appease the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-09 20:43:34 +00:00
Richard Barton 83cfff6229 Oops - correct broken disassembly for VMOV 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-09 18:20:02 +00:00
Richard Barton 2e7e34ba54 Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-09 16:41:33 +00:00
Richard Barton c8f2fcc9a3 Correct decoder for T1 conditional B encoding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 09:12:53 +00:00
NAKAMURA Takumi dd051a0414 ARMDisassembler.cpp: Fix utf8 char in comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157292 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-22 21:47:02 +00:00
Kevin Enderby 3610a15c35 Tweak to the fix in r156212, as with the change in removing the shift the 
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156213 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 22:09:52 +00:00
Kevin Enderby ce734d5ffe Fix a bug in the ARM disassembler for wide branch conditional instructions 
where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156212 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 22:02:27 +00:00
Kevin Enderby 2d524b0765 Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits 
for the assembler and disassembler.  Which were not being set/read correctly
for offsets greater than 22 bits in some cases.

Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 22:41:56 +00:00
Silviu Baranga b422d0b65e Fixed disassembler for vstm/vldm ARM VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 16:38:40 +00:00
Jim Grosbach bb32f1d545 ARM: Tweak tADDrSP definition for consistent operand order. 
Make the operand order of the instruction match that of the asm syntax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155747 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-27 23:51:33 +00:00
Richard Barton 4d2f077df1 Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-27 08:42:59 +00:00
Richard Barton f4478f99dd Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155439 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-24 11:13:20 +00:00
Silviu Baranga 35ee7d28a6 Added support for disassembling unpredictable swp/swpb ARM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 14:18:57 +00:00
Silviu Baranga fa1ebc6abe Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 13:12:50 +00:00
Kevin Enderby c5a2a33938 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) 
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-17 00:49:27 +00:00
Kevin Enderby 2a7d3a9373 Fix a few more places in the ARM disassembler so that branches get 
symbolic operands added when using the C disassembler API.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154628 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 23:13:34 +00:00
Kevin Enderby b318cc16c9 Fixed a case of ARM disassembly getting an assert on a bad encoding 
of a VST instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:40:17 +00:00