Commit Graph

121 Commits

Author SHA1 Message Date
Evan Cheng 6bd9567a6a - Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code.
- Mark lots of X86 intrinsics as "Commutative" to allow load folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
Duncan Sands 83ec4b6711 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06 12:08:01 +00:00
Dan Gohman ee4fa1977d Move instruction flag inference out of InstrInfoEmitter and into
CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags. 

This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49123 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-03 00:02:49 +00:00
Christopher Lamb c929823525 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-16 03:12:01 +00:00
Evan Cheng da47e6e0d0 Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15 00:03:38 +00:00
Evan Cheng a844bdeab3 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02 04:07:54 +00:00
Christopher Lamb 8535624739 Allow ComplexExpressions in InstrInfo.td files to be slightly more... complex! ComplexExpressions can now have attributes which affect how TableGen interprets
the pattern when generating matchin code. 

The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46606 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-31 07:27:46 +00:00
Chris Lattner ba7e756c22 Start inferring side effect information more aggressively, and fix many bugs in the
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects.  It would be really nice if we could
write patterns for copy instructions.

I have audited all the x86 instructions down to MOVDQAmr.  The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10 07:59:24 +00:00
Chris Lattner 6cc654b27a Split the impl of CodeGenInstruction out to its own .cpp file, add a getName() accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45645 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-06 01:35:39 +00:00
Chris Lattner 6cefb77a70 change getQualifiedName to be a global function.
Split the pattern parsing code out from the dag isel emitter into it's own file.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45632 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-05 22:25:12 +00:00
Chris Lattner 3060910e29 remove attributions from utils.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45419 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:37:13 +00:00
Bill Wendling 6b1da9c39f Add flags to indicate that there are "never" side effects or that there "may be"
side effects for machine instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45022 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-14 01:48:59 +00:00
Evan Cheng 3dd298fb62 Oops. Forgot these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44969 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-13 00:42:35 +00:00
Owen Anderson 20ab29068d Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-12 07:39:39 +00:00
Dale Johannesen 317096ab37 Add sqrt and powi intrinsics for long double.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42423 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-28 01:08:20 +00:00
Evan Cheng a3ca3149f2 Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
between two registers in the specific class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42123 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-19 01:35:01 +00:00
Dan Gohman 0fee3ff93e Add MVT::fAny for overloading intrinsics on floating-point types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41128 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-16 21:57:19 +00:00
Chandler Carruth 6994040a95 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40807 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-04 01:51:18 +00:00
Christopher Lamb 08d52071ba Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26 07:48:21 +00:00
Christopher Lamb 8245510ae0 Teach TableGen about the new vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40513 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26 06:41:18 +00:00
Evan Cheng 102dc195b6 No need for noResults anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40075 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-20 00:21:23 +00:00
Evan Cheng 64d80e3387 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
Dan Gohman 3bf6e183d5 Eliminate an unused parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39828 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-13 20:16:50 +00:00
Evan Cheng 88cc092ca5 Try committing again. Add OptionalDefOperand. Remove clobbersPred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38498 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 18:05:01 +00:00
Evan Cheng c419bd3396 ImmutablePredicateOperand is no more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37963 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 23:23:38 +00:00