documentation that this module needs to be made independent of the
register file description of the current target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13125 91177308-0d34-0410-b5e6-96231b3b80d8
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8
instead of randomly groping about inside its outEdges array.
Make SchedGraph::addDummyEdges() use getNumOutEdges() instead of
outEdges.size().
Get rid of ifdefed-out code in SchedGraph::buildGraph().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11238 91177308-0d34-0410-b5e6-96231b3b80d8
a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().
This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10461 91177308-0d34-0410-b5e6-96231b3b80d8
not just an Instruction*, at least in one unfortunate case:
the first operand to the va_arg instruction.
Modify ValueToDefVecMap to map from Value*, not Instruction*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7052 91177308-0d34-0410-b5e6-96231b3b80d8
preallocated. While reg-to-reg dependences were already handled, this
change required new code for adding edges to/from call instructions.
This was part of the extensive changes to the way code generation occurs
for function call arguments and return values.
See log for CodeGen/PhyRegAlloc.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6467 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8
Chris Lattner
Brian Gaeke
Alkis Evlogimenos
Misha Brukman
John Criswell
Tanya Lattner
Vikram S. Adve