Commit Graph

195 Commits

Author SHA1 Message Date
Matthias Braun e67bd6c248 CodeGen: Use mop_iterator instead of MIOperands/ConstMIOperands
MIOperands/ConstMIOperands are classes iterating over the MachineOperand
of a MachineInstr, however MachineInstr::mop_iterator does the same
thing.

I assume these two iterators exist to have a uniform interface to
iterate over the operands of a machine instruction bundle and a single
machine instruction. However in practice I find it more confusing to have 2
different iterator classes, so this patch transforms (nearly all) the
code to use mop_iterators.

The only exception being MIOperands::anlayzePhysReg() and
MIOperands::analyzeVirtReg() still needing an equivalent, I leave that
as an exercise for the next patch.

Differential Revision: http://reviews.llvm.org/D9932

This version is slightly modified from the proposed revision in that it
introduces MachineInstr::getOperandNo to avoid the extra counting
variable in the few loops that previously used MIOperands::getOperandNo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238539 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-29 02:56:46 +00:00
Matthias Braun dfc41dbcda MachineInstr: Remove unused parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237726 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-19 21:22:20 +00:00
Daniel Jasper 6c456f0351 [MachineLICM] Use newer model of register pressure sets.
TargetRegisterInfo::getRegPressureLimit has a note that it is an old
model that relies on manually entered classes. Using the newer model of
register pressure sets seems more appropriate. We might eventually even
switch to lib/CodeGen/RegisterPressure.cpp, but we should probably do
incremental changes here.

Using the newer model also makes it easier to take regmasks into account
which is necessary to fix llvm.org/PR23143. I am currently also
preparing a patch for that, but would like to do this switch
independently.

Review: http://reviews.llvm.org/D8986

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234880 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-14 11:56:25 +00:00
Daniel Jasper 2c5bf601c3 [MachineLICM] Cleanup, remove unused parameters. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234392 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-08 07:10:30 +00:00
Daniel Jasper 6221f41a5e Cleanup register pressure calculation in MachineLICM.
There were four almost identical implementations of calculating/updating
the register pressure for a certain MachineInstr. Cleanup to have a
single implementation (well, controlled with two bool flags until this
is cleaned up more).

No functional changes intended.

Tested by verify that there are no binary changes in the entire llvm
test-suite. A new test was added separately in r234309 as it revealed a
pre-existing error in the register pressure calculation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234325 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 16:42:35 +00:00
Daniel Jasper 1fe7512627 [MachineLICM] Remove obsolete comment about not considering reg pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234310 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 11:43:32 +00:00
Daniel Jasper efa23ae2a9 [MachineLICM] Small cleanup: Constify and rangeify.
NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234018 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 16:19:48 +00:00
Daniel Jasper 439cc2c5de [MachineLICM] First steps of sinking GEPs near calls.
Specifically, if there are copy-like instructions in the loop header
they are moved into the loop close to their uses. This reduces the live
intervals of the values and can avoid register spills.

This is working towards a fix for http://llvm.org/PR22230.
Review: http://reviews.llvm.org/D7259

Next steps:
- Find a better cost model (which non-copy instructions should be sunk?)
- Make this dependent on register pressure

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232262 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-14 10:58:38 +00:00
Daniel Jasper c7c2518a65 Small cleanup of MachineLICM.cpp
Specifically:
- Calculate the loop pre-header once at the stat of HoistOutOfLoop, so:
  - We don't-DFS walk the MachineDomTree if we aren't going to do anything
  - Don't call getCurPreheader for each Scope
- Don't needlessly use a do-while loop
- Use early exit for Scopes.size() == 0

No functional changes intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228350 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 22:39:46 +00:00
Hal Finkel 9d1500e68f [MachineLICM] A command-line option to hoist even cheap instructions
Add a command-line option to enable hoisting even cheap instructions (in
low-register-pressure situations). This is turned off by default, but has
proved useful for testing purposes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225470 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 22:10:48 +00:00
David Blaikie 5401ba7099 Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool>
This is to be consistent with StringSet and ultimately with the standard
library's associative container insert function.

This lead to updating SmallSet::insert to return pair<iterator, bool>,
and then to update SmallPtrSet::insert to return pair<iterator, bool>,
and then to update all the existing users of those functions...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222334 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 07:49:26 +00:00
Eric Christopher b15974e996 Remove the use and member variable of the TargetMachine from
MachineLICM as we can get the same data off of the MachineFunction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219663 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-14 06:26:57 +00:00
Benjamin Kramer 63688e622c Eliminate some deep std::vector copies. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218999 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-03 18:33:16 +00:00
Eric Christopher 9f85dccfc6 Remove the TargetMachine forwards for TargetSubtargetInfo based
information and update all callers. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 21:25:23 +00:00
Jiangning Liu f3224d0617 Add TargetInstrInfo interface isAsCheapAsAMove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214158 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 01:55:19 +00:00
Chandler Carruth 8677f2ff9a [Modules] Remove potential ODR violations by sinking the DEBUG_TYPE
define below all header includes in the lib/CodeGen/... tree. While the
current modules implementation doesn't check for this kind of ODR
violation yet, it is likely to grow support for it in the future. It
also removes one layer of macro pollution across all the included
headers.

Other sub-trees will follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206837 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 02:02:50 +00:00
Nick Lewycky d63390cba1 Break PseudoSourceValue out of the Value hierarchy. It is now the root of its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206255 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 07:22:52 +00:00
Craig Topper 4ba844388c [C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206142 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 00:51:57 +00:00
Paul Robinson 5fa58a5b23 Disable each MachineFunctionPass for 'optnone' functions, unless that
pass normally runs at optimization level None, or is part of the
register allocation pipeline.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205228 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 17:43:35 +00:00
Owen Anderson 92fca73d52 Switch a number of loops in lib/CodeGen over to range-based for-loops, now that
the MachineRegisterInfo iterators are compatible with it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204075 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-17 19:36:09 +00:00
Owen Anderson bf63022492 Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing
operator* on the by-operand iterators to return a MachineOperand& rather than
a MachineInstr&.  At this point they almost behave like normal iterators!

Again, this requires making some existing loops more verbose, but should pave
the way for the big range-based for-loop cleanups in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 23:12:04 +00:00
Craig Topper 9f998de891 [C++11] Add 'override' keyword to virtual methods that override their base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203220 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 09:26:03 +00:00
Benjamin Kramer 94ee55d4b3 Replace some unnecessary vector copies with references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-15 22:04:42 +00:00
Richard Sandiford 9608ed1311 Fix overly pessimistic shortcut in post-RA MachineLICM
Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers
and TermRegs.  When it sees a definition of R it adds all aliases of R
to the corresponding set, so that when it needs to test for membership
it only needs to test a single register, rather than worrying about
aliases there too.  E.g. the final candidate loop just has:

    unsigned Def = Candidates[i].Def;
    if (!PhysRegClobbers.test(Def) && ...) {

to test whether register Def is multiply defined.

However, there was also a shortcut in ProcessMI to make sure we didn't
add candidates if we already knew that they would fail the final test.
This shortcut was more pessimistic than the final one because it
checked whether _any alias_ of the defined register was multiply defined.
This is too conservative for targets that define register pairs.
E.g. on z, R0 and R1 are sometimes used as a pair, so there is a
128-bit register that aliases both R0 and R1.  If a loop used
R0 and R1 independently, and the definition of R0 came first,
we would be able to hoist the R0 assignment (because that used
the final test quoted above) but not the R1 assignment (because
that meant we had two definitions of the paired R0/R1 register
and would fail the shortcut in ProcessMI).

This patch just uses the same check for the ProcessMI shortcut as
we use in the final candidate loop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:11:13 +00:00
Craig Topper 9e639e8fd9 Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186098 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-11 16:22:38 +00:00