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69 Commits

Author SHA1 Message Date
Marina Yatsina be4bc8908b [X86] Fix for bugzilla 31576 - add support for "data32" instruction prefix 
This patch fixes bugzilla 31576 (https://llvm.org/bugs/show_bug.cgi?id=31576).

"data32" instruction prefix was not defined in the llvm.
An exception had to be added to the X86 tablegen and AsmPrinter because both "data16" and "data32" are encoded to 0x66 (but in different modes).

Differential Revision: https://reviews.llvm.org/D28468



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292352 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-18 08:07:51 +00:00
Thomas Jablin 920d0ae595 test commit: remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273197 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-06-20 20:43:26 +00:00
Elena Demikhovsky a0a51734cd AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long types. 
In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch.
I temporary removed the old intrinsics test (just to split this patch).
Half types are not covered here.

Differential Revision: http://reviews.llvm.org/D11134



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242023 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-13 13:26:20 +00:00
Elena Demikhovsky 695922de3d AVX-512: Added VPTESTM and VPTESTNM instructions for SKX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235383 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-21 13:13:46 +00:00
Craig Topper b82d5479b9 Use SmallVector instead of std::vector for uniquing X86 disassembler operand sets. The number of operands is a small fixed size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234465 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-09 04:08:48 +00:00
Craig Topper 13154acf19 Simplify some printing code by combining new lines onto previous strings. Don't work so hard not to print a comma on the last entry of an array. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234464 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-09 04:08:46 +00:00
Craig Topper 684de8845e Don't convert enum to strings just to put them in the uniquing map. Use the enum directly. Only convert to a string for printing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234463 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-09 04:08:42 +00:00
Elena Demikhovsky 975e9b99aa AVX-512: Added mask and rounding mode for scalar arithmetics 
Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230891 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-01 07:44:04 +00:00
Craig Topper 01c99892ca [X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225099 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-03 00:00:20 +00:00
Craig Topper 71fc42dbf6 [X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates. 
This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used.

Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225075 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-02 07:02:25 +00:00
Craig Topper 51f423ff30 [X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit modes with all 4 combinations of OpSize and AdSize prefixes being present or not. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225036 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-31 07:07:31 +00:00
Craig Topper 3bc4397f1f [X86] Remove the single AdSize indicator and replace it with separate AdSize16/32/64 flags. 
This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224809 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-24 06:05:22 +00:00
Robert Khasanov 9371efbcdb [AVX512] Extended avx512_sqrt_packed (sqrt instructions) to VL subset. 
Refactored through AVX512_maskable



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220806 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-28 18:15:20 +00:00
Robert Khasanov 340b5b9ad7 [AVX512] Extended avx512_binop_rm for AVX512VL subsets. 
Added avx512_binop_rm_vl multiclass for VL subset
Added encoding tests



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219390 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-09 08:38:48 +00:00
Robert Khasanov cc4b123a47 [SKX] avx512_icmp_packed multiclass extension 
Extended avx512_icmp_packed multiclass by masking versions.
Added avx512_icmp_packed_rmb multiclass for embedded broadcast versions.
Added corresponding _vl multiclasses.
Added encoding tests for CPCMP{EQ|GT}* instructions.
Add more fields for X86VectorVTInfo.
Added AVX512VLVectorVTInfo that include X86VectorVTInfo for 512/256/128-bit versions

Differential Revision: http://reviews.llvm.org/D5024


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216383 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-25 14:49:34 +00:00
Robert Khasanov 7017934668 [SKX] Enabling load/store instructions: encoding 
Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS,

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214719 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-04 14:35:15 +00:00
Elena Demikhovsky b0a3627443 AVX-512: Added rrk, rrkz, rmk, rmkz, rmbk, rmbkz versions of AVX512 FP packed instructions, added encoding tests for them. 
By Robert Khazanov.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203098 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-06 08:45:30 +00:00
Craig Topper 82a644adf2 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-19 05:34:21 +00:00
Craig Topper 1ee7e39dd4 Remove filtering concept from X86 disassembler table generation. It's no longer necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201299 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-13 07:07:16 +00:00
Craig Topper a01427c15a Remove unnecessary include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201041 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-09 07:55:19 +00:00
David Woodhouse 9334b07527 [x86] Fix disassembly of MOV16ao16 et al. 
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199654 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-20 12:02:53 +00:00
Elena Demikhovsky 1f044d443d AVX-512: Embedded Rounding Control - encoding and printing 
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199102 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-13 12:55:03 +00:00
David Woodhouse aab59870a4 [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand 
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198759 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-08 12:58:24 +00:00
Craig Topper 5cfd40ccd4 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198284 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 21:52:57 +00:00
Elena Demikhovsky 3062a311ac AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 15:12:34 +00:00