Commit Graph

2900 Commits

Author SHA1 Message Date
Serge Rogatch 9a63b871bd [XRay][Arm] Repair XRay table emission on Arm32 and add tests to identify such problem earlier
Summary:
Emission of XRay table was occasionally disabled for Arm32, but this bug was not then detected because earlier (also by mistake) testing of XRay was occasionally disabled on 32-bit Arm targets. This patch should fix that problem and detect such problems in the future.
This patch is one of a series, see also
- https://reviews.llvm.org/D28623

Reviewers: rengolin, dberris

Reviewed By: dberris

Subscribers: llvm-commits, aemerson, rengolin, dberris, iid_iunknown

Differential Revision: https://reviews.llvm.org/D28624

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292516 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-19 20:24:23 +00:00
Renato Golin 6994e2312e Revert "[XRay][Arm] Repair XRay table emission on Arm32 and add tests to identify such problem earlier"
This reverts commit r292210, as it broke the Thumb buldbot with:

clang-5.0: error: the clang compiler does not support '-fxray-instrument
on thumbv7-unknown-linux-gnueabihf'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292357 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18 09:08:43 +00:00
Serge Rogatch fca725c192 [XRay][Arm] Repair XRay table emission on Arm32 and add tests to identify such problem earlier
Summary:
Emission of XRay table was occasionally disabled for Arm32, but this bug was not then detected because earlier (also by mistake) testing of XRay was occasionally disabled on 32-bit Arm targets. This patch should fix that problem and detect such problems in the future.
This patch is one of a series, see also
- https://reviews.llvm.org/D28623

Reviewers: rengolin, dberris

Reviewed By: dberris

Subscribers: llvm-commits, aemerson, rengolin, dberris, iid_iunknown

Differential Revision: https://reviews.llvm.org/D28624

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292210 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-17 11:52:10 +00:00
Simon Pilgrim b648fac5ca [SelectionDAG] Add support for BITREVERSE constant folding
We were relying on constant folding of the legalized instructions to do what constant folding we had previously

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292114 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16 13:39:00 +00:00
Kyle Butt 0aa7497cd7 Revert "CodeGen: Allow small copyable blocks to "break" the CFG."
This reverts commit ada6595a52.

This needs a simple probability check because there are some cases where it is
not profitable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291695 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-11 19:55:19 +00:00
Eli Friedman 1f1e5c29c3 [ARM] More aggressive matching for vpadd and vpaddl.
The new matchers work after legalization to make them simpler, and to avoid
blocking other optimizations.

Differential Revision: https://reviews.llvm.org/D27779



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291693 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-11 19:33:38 +00:00
Evgeny Astigeevich de8188fb92 [ARM] Fix test CodeGen/ARM/fpcmp_ueq.ll broken by rL290616
Commit rL290616 (https://reviews.llvm.org/rL290616) changed a checking command
for the triple arm-apple-darwin in LLVM::CodeGen/ARM/fpcmp_ueq.ll. As a result
of the changes the test could fail for the valid generated code.

These changes fixes the test to check only instructions we would expect.

Differential Revision: https://reviews.llvm.org/D28159



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291678 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-11 16:23:28 +00:00
Kyle Butt ada6595a52 CodeGen: Allow small copyable blocks to "break" the CFG.
When choosing the best successor for a block, ordinarily we would have preferred
a block that preserves the CFG unless there is a strong probability the other
direction. For small blocks that can be duplicated we now skip that requirement
as well.

Differential revision: https://reviews.llvm.org/D27742

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291609 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-10 23:04:30 +00:00
Matt Arsenault fa5aafaac2 DAG: Avoid OOB when legalizing vector indexing
If a vector index is out of bounds, the result is supposed to be
undefined but is not undefined behavior. Change the legalization
for indexing the vector on the stack so that an out of bounds
index does not create an out of bounds memory access.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291604 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-10 22:02:30 +00:00
Joerg Sonnenberger 9af2e4eb39 Emit .cfi_sections before the first .cfi_startproc
GNU as rejects input where .cfi_sections is used after .cfi_startproc,
if the new section differs from the old. Adjust our output to always
emit .cfi_sections before the first .cfi_startproc to minimize necessary
code.

Differential Revision: https://reviews.llvm.org/D28011


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290817 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-02 18:05:27 +00:00
Saleem Abdulrasool f40c74a0fe test: modernise ARM CodeGen tests
Replace the use of grep with FileCheck.  Tidy up some of the tests.  A
few of the tests have been left as weak as previously, though some have
been made more stringent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290616 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-27 18:35:19 +00:00
Zijiao Ma e365f8338a Make the canonicalisation on shifts benifit to more case.
1.Fix pessimized case in FIXME.
2.Add tests for it.
3.The canonicalisation on shifts results in different sequence for
  tests of machine-licm.Correct some check lines.

Differential Revision: https://reviews.llvm.org/D27916

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290410 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-23 02:56:07 +00:00
Adrian Prantl c271bc0481 Renumber testcase metadata nodes after r290153.
This patch renumbers the metadata nodes in debug info testcases after
https://reviews.llvm.org/D26769. This is a separate patch because it
causes so much churn. This was implemented with a python script that
pipes the testcases through llvm-as - | llvm-dis - and then goes
through the original and new output side-by side to insert all
comments at a close-enough location.

Differential Revision: https://reviews.llvm.org/D27765

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290292 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 00:45:21 +00:00
Adrian Prantl 6b556068df Legalize metadata in legacy testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290285 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-21 23:28:49 +00:00
Eli Friedman 1e77c707b7 [ARM] Implement isExtractSubvectorCheap.
See https://reviews.llvm.org/D6678 for the history of
isExtractSubvectorCheap. Essentially the same considerations apply
to ARM.

This temporarily breaks the formation of vpadd/vpaddl in certain cases;
AddCombineToVPADDL essentially assumes that we won't form VUZP shuffles.
See https://reviews.llvm.org/D27779 for followup fix.

Differential Revision: https://reviews.llvm.org/D27774



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290198 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 20:05:07 +00:00
Eli Friedman 967c9cbd8f [ARM] Generate checks for shuffle tests using update_llc_test_checks.py.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290196 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 19:33:24 +00:00
Adrian Prantl 7b500b4bdf [IR] Remove the DIExpression field from DIGlobalVariable.
This patch implements PR31013 by introducing a
DIGlobalVariableExpression that holds a pair of DIGlobalVariable and
DIExpression.

Currently, DIGlobalVariables holds a DIExpression. This is not the
best way to model this:

(1) The DIGlobalVariable should describe the source level variable,
    not how to get to its location.

(2) It makes it unsafe/hard to update the expressions when we call
    replaceExpression on the DIGLobalVariable.

(3) It makes it impossible to represent a global variable that is in
    more than one location (e.g., a variable with multiple
    DW_OP_LLVM_fragment-s).  We also moved away from attaching the
    DIExpression to DILocalVariable for the same reasons.

This reapplies r289902 with additional testcase upgrades and a change
to the Bitcode record for DIGlobalVariable, that makes upgrading the
old format unambiguous also for variables without DIExpressions.

<rdar://problem/29250149>
https://llvm.org/bugs/show_bug.cgi?id=31013
Differential Revision: https://reviews.llvm.org/D26769

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290153 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 02:09:43 +00:00
Eli Friedman 97cbb36487 Add ARM support to update_llc_test_checks.py
Just the minimal support to get it working at the moment.

Includes checks for test/CodeGen/ARM/vzip.ll as an example.

Differential Revision: https://reviews.llvm.org/D27829



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290144 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 23:09:51 +00:00
Diana Picus 7678e12d91 [ARM] GlobalISel: Add more checks to test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290108 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 14:08:11 +00:00
Diana Picus af01848eb7 [ARM] GlobalISel: Minor style fixup in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290107 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 14:08:06 +00:00
Diana Picus ce4dc1f41b [ARM] GlobalISel: Lower i8 and i16 register args
This allows lowering i8 and i16 arguments if they can fit in the registers. Note
that the lowering is incomplete - ABI extensions are handled in a subsequent
patch.

(Last part of)
Differential Revision: https://reviews.llvm.org/D27704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290106 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 14:08:02 +00:00
Diana Picus 07b3834b44 [ARM] GlobalISel: Allow i8 and i16 adds
Teach the instruction selector and legalizer that it's ok to have adds with 8 or
16-bit integers.

This is the second part of https://reviews.llvm.org/D27704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290105 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 14:07:56 +00:00
Diana Picus f2838d8814 [ARM] GlobalISel: Select i8 and i16 copies
Teach the instruction selector that it's ok to copy small values from physical
registers.

First part of https://reviews.llvm.org/D27704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290104 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 14:07:50 +00:00
Diana Picus 9950c0fd74 [ARM] GlobalISel: Lower more than 4 arguments
This adds support for lowering more than 4 arguments (although still i32 only).
It uses the handleAssignments / ValueHandler infrastructure extracted from
the AArch64 backend in r288658.

Differential Revision: https://reviews.llvm.org/D27195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290098 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 11:55:41 +00:00
Diana Picus abc24acb9f [ARM] GlobalISel: Support loading from the stack
Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit
scalars only). This will be useful for functions that need to pass arguments on
the stack.

First part of https://reviews.llvm.org/D27195.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290096 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 11:26:31 +00:00