Commit Graph

58 Commits

Author SHA1 Message Date
Javed Absar a297939a6a [ARM]: Add Cortex-R52 target to LLVM
This patch adds Cortex-R52, the new ARM real-time processor, to LLVM. 
Cortex-R52 implements the ARMv8-R architecture.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283542 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-07 12:06:40 +00:00
Mehdi Amini a47cbd993e Use StringReg in TargetParser APIs (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283527 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-07 08:37:29 +00:00
Zijiao Ma b87ab2ee22 Add unittests to {ARM | AArch64}TargetParser.
Add unittest to {ARM | AArch64}TargetParser,and by the way correct problems as below:
1.Correct a incorrect indexing problem in AArch64TargetParser. The architecture enumeration
 is shared across ARM and AArch64 in original implementation.But In the code,I just used the
 index which was offset by the ARM, and this would index into the array incorrectly. To make
 AArch64 has its own arch enum,or we will do a lot of slowly iterating.
2.Correct a spelling error. The parameter of llvm::AArch64::getArchExtName.
3.Correct a writing mistake, in llvm::ARM::parseArchISA.

Differential Revision: https://reviews.llvm.org/D21785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276957 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-28 06:11:18 +00:00
Zijiao Ma 28712da449 [AArch64] Add RAS extensions support in AArch64TargetParser.
RAS extensions are part of ARMv8.2,now supported in Clang.
Add RAS extensions support in AArch64TargetParser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272533 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-13 05:27:58 +00:00
Saleem Abdulrasool e169351252 Support: correct AArch64 TargetParser implementation
The architecture enumeration is shared across ARM and AArch64.  However, the
data is not.  The code incorrectly would index into the array using the
architecture index which was offset by the ARMv7 architecture enumeration.  We
do not have a marker for indicating the architectural family to which the
enumeration belongs so we cannot be clever about offsetting the index (at least
it is not immediately apparent to me).  Instead, fall back to the tried-and-true
method of slowly iterating the array (its not a large array, so the impact of
this is not too high).

Because of the incorrect indexing, if we were lucky, we would crash, but usually
we would return an invalid StringRef.  We did not have any tests for the AArch64
target parser previously;.  Extend the previous tests I had added for ARM to
cover AArch64 for ensuring that we return expected StringRefs.

Take the opportunity to change some iterator types to references.

This work is needed to support parsing `.arch name` directives in the AArch64
target asm parser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272145 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-08 14:30:00 +00:00
Renato Golin 0e4502240a [AArch64] Adding a TargetParser for AArch64
There's already a ARMTargetParser,now adding a similar one for aarch64.
so we can use it to do ARCH/CPU/FPU parsing in clang and llvm, instead of
string comparison.

Patch by Jojo Ma.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270687 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-25 12:02:33 +00:00
Saleem Abdulrasool 2954f99f46 Support: catch invalid accesses
It is possible to invoke these methods on an invalid input resulting in an
invalid substring construction.  It seems that we do not have unit tests for
these methods.  Tests to ensure that the invalid call is caught to follow in
clang.

Resolves PR26839.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262778 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-05 20:00:44 +00:00
Bradley Smith 0283decdee [ARM] Add ARMv8-M Baseline/Mainline LLVM targeting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257878 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-15 10:24:39 +00:00
Ben Craig 49f241bc5a Reordering fields to reduce padding in LLVM. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255554 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-14 21:57:05 +00:00
Oliver Stannard 27fff2c5ff [ARM] Add ARMv8.2-A to TargetParser
Add ARMv8.2-A to TargetParser, so that it can be used by the clang
command-line options and the .arch directive.

Most testing of this will be done in clang, checking that the
command-line options that this enables work.

Differential Revision: http://reviews.llvm.org/D15037



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254400 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-01 10:33:56 +00:00
Artyom Skrobov 7cbf72b489 Handle ARMv6-J as an alias, instead of fake architecture
Summary:
This follows D14577 to treat ARMv6-J as an alias for ARMv6,
instead of an architecture in its own right.

The functional change is that the default CPU when targeting ARMv6-J
changes from arm1136j-s to arm1136jf-s, which is currently used as
the default CPU for ARMv6; both are, in fact, ARMv6-J CPUs.

The J-bit (Jazelle support) is irrelevant to LLVM, and it doesn't
affect code generation, attributes, optimizations, or anything else,
apart from selecting the default CPU.

Reviewers: rengolin, logan, compnerd

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D14755

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253675 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-20 16:46:09 +00:00
NAKAMURA Takumi d19cbfed93 TargetParser.cpp: Fixup -- StringRef::startswith() is better here. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253570 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-19 15:42:52 +00:00
NAKAMURA Takumi 073829825d llvm/lib/Support/TargetParser.cpp: Rework llvm::ARM::getArchExtFeature() to avoid abuse of Twine in r253470.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253566 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-19 15:03:11 +00:00
Bradley Smith fbbc259e37 [ARM] Add +feature names to TargetParser extensions table
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253470 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-18 16:32:12 +00:00
Artyom Skrobov 4c351fd4e8 Handle ARMv6KZ naming
Summary:
* ARMv6KZ is the "canonical" name, given in the ARMARM
* ARMv6Z is an "official abbreviation" for it, mentioned in the ARMARM
* ARMv6ZK is a popular misspelling, which we should support as an alias.

The patch corrects the handling of the names.

Functional changes:
* ARMv6Z no longer treated as an architecture in its own right
* ARMv6ZK renamed to ARMv6KZ, accepting ARMv6ZK as an alias
* arm1176jz-s and arm1176jzf-s recognized as ARMv6ZK, instead of ARMv6K
* default ARMv6K CPU changed to arm1176j-s

Reviewers: rengolin, logan, compnerd

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D14568

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253206 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 14:05:32 +00:00
Artyom Skrobov 05400e9493 NFC refactorings in lib/Support/TargetParser.cpp
Summary:
* declare FPUNames, ARCHNames, ARCHExtNames, HWDivNames, CPUNames
  as static const
* implement getDefaultExtensions with a StringSwitch, in the same
  way getDefaultFPU is implemented

Reviewers: rengolin

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14648

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253201 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 12:08:05 +00:00
Bradley Smith 870fdb54c3 [ARM] Allow TargetParser to accurately target architectures
Instead of defaulting to an empty string, we want to default to
the CPU 'generic' in the case of no valid default CPU being found,
(as long as the architecture is actually valid).

In order to do this we add a default FPU for each architecture, as
well as falling back to architecture defaults for extensions and FPU
in the case of a generic CPU is specified.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253198 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 11:15:22 +00:00
Artyom Skrobov 957ee69c41 Cull non-standard variants of ARM architectures (NFC)
Summary:
This patch changes ARMV5, ARMV5E, ARMV6SM, ARMV6HL, ARMV7, ARMV7L,
ARMV7HL, ARMV7EM to be treated as aliases for the corresponding
standard architectures, instead of as actual architectures.

Reviewers: rengolin

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D14577

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252903 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-12 15:51:41 +00:00
Tim Northover 856a038026 ARM: support .watchos_version_min and .tvos_version_min.
These MachO file directives are used by linkers and other tools to provide
compatibility information, much like the existing .ios_version_min and
.macosx_version_min.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251569 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-28 22:36:05 +00:00
Artyom Skrobov 3685b697a2 [ARM] Renaming +t2dsp feature into +dsp, as discussed on llvm-dev
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251125 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-23 17:19:19 +00:00
Artyom Skrobov c848236c93 [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a
hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with
a FIXME: attached.

This patch changes the handling of +t2dsp to be in line with other
architecture extensions.

Following a revert of r248152 and new review comments, this patch also includes
renaming FeatureDSPThumb2 -> FeatureDSP, hasThumb2DSP() -> hasDSP(), etc.
The spelling of "t2dsp" is preserved, pending a further investigation of its
possible external usage.

Differential Revision: http://reviews.llvm.org/D12937



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248519 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 17:31:16 +00:00
James Molloy 7d3733cd0d Revert "[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def"
This was committed without the code review (http://reviews.llvm.org/D12937) being approved.

This reverts commit r248152.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248174 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 16:35:08 +00:00
Artyom Skrobov 7dfb31c329 [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a
hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with
a FIXME: attached.

This patch changes the handling of +t2dsp to be in line with other
architecture extensions.

Following review comments, also updating the description of FeatureDSPThumb2
in ARM.td.

Differential Revision: http://reviews.llvm.org/D12937



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248152 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 12:43:10 +00:00
Alexandros Lamprineas 1955b207be Added arch extensions and default target features in TargetParser.
Differential: http://reviews.llvm.org/D11590

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246930 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-05 17:05:33 +00:00
Chandler Carruth 2ff230d5c9 Remove a linear walk to find the default FPU for a given CPU by directly
expanding the .def file within a StringSwitch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246377 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-30 09:01:38 +00:00