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Author SHA1 Message Date
Craig Topper f031545412 [X86] Merge the disassemblers handling of the different TYPE_RELs by getting the size information from the ENCODING field. NFCI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292096 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-16 06:49:09 +00:00
Craig Topper 14d16cc514 [X86] Reduce the number of operand 'types' the disassembler needs to deal with. NFCI 
We were frequently checking for a list of types and the different types
conveyed no real information. So lump them together explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292095 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-16 06:49:03 +00:00
Craig Topper 75deb64c6f [AVX-512] Begin giving the disassembler a way to recognize that VSIB is a different encoding than regular addressing modes. 
This part first teaches it not to check error if EVEX.V2 is used by a VSIB instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292093 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-16 05:44:25 +00:00
Craig Topper 00915333a9 [AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQD 
with ZMM index. Similar for SCATTER and the prefetch gather and scatter
instructions.

Fixes PR31618.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292088 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-16 00:55:58 +00:00
Craig Topper 08f89d57a0 [X86] Create a new instruction format to handle 4VOp3 encoding. This saves one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279424 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-08-22 07:38:50 +00:00
Craig Topper 91e5e5818d [X86] Create a new instruction format to handle MemOp4 encoding. This saves one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279423 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-08-22 07:38:45 +00:00
Craig Topper b663f7015c [X86] Space out the encodings of X86 instruction formats. I plan to add some new encodings in future commits and this will reduce the size of those commits. NFC 
This tries to keep all the ModRM memory and register forms in their own regions of the encodings. Hoping to make it simple on some of the switch statements that operate on these encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279422 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-08-22 07:38:41 +00:00
Craig Topper 6e07b06d38 [X86] Merge small helper function into the switch that calls it since they both operate on the same variable. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279421 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-08-22 07:38:36 +00:00
Craig Topper d30b1a1614 [X86] Explicitly list all X86 instruction forms in switch statement so its easier to detect when one is missing. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279420 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-08-22 07:38:30 +00:00
Igor Breger 7f2251533a AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling. 
Differential Revision: http://reviews.llvm.org/D17564

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261862 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-02-25 13:30:17 +00:00
Craig Topper f150810c18 [X86] Remove some unused encoding checks from the disassembler table building. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261418 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-02-20 06:20:21 +00:00
Craig Topper 2082d39556 [TableGen,X86] Add NDEBUG check to a variable initialization that's only used by asserts. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261188 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-02-18 04:54:32 +00:00
Craig Topper a5754d7efa [TableGen,X86] Remove extra optional operand from RawFrm. RawFrm with 2 immediates is handled by RawFrmImm8/RawFrmImm16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261187 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-02-18 04:54:29 +00:00
Craig Topper 35e38d845b [TableGen] Fix inconsistent spacing. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260935 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-02-16 04:24:58 +00:00
Craig Topper 69dced0d4c [TableGen] Stop passing by reference an integer that doesn't get modified. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260934 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-02-16 04:24:56 +00:00
Craig Topper 6ff0feee63 [TableGen] Remove unused member variable. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260933 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-02-16 04:24:54 +00:00
Asaf Badouh 5c7343b3a6 [X86][PKU] Add {RD,WR}PKRU encoding 
Differential Revision: http://reviews.llvm.org/D15711

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256366 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-12-24 08:25:00 +00:00
Chih-Hung Hsieh 3a1999a311 [X86] Part 2 to fix x86-64 fp128 calling convention. 
Part 1 was submitted in http://reviews.llvm.org/D15134.
Changes in this part:
* X86RegisterInfo.td, X86RecognizableInstr.cpp: Add FR128 register class.
* X86CallingConv.td: Pass f128 values in XMM registers or on stack.
* X86InstrCompiler.td, X86InstrInfo.td, X86InstrSSE.td:
  Add instruction selection patterns for f128.
* X86ISelLowering.cpp:
  When target has MMX registers, configure MVT::f128 in FR128RegClass,
  with TypeSoftenFloat action, and custom actions for some opcodes.
  Add missed cases of MVT::f128 in places that handle f32, f64, or vector types.
  Add TODO comment to support f128 type in inline assembly code.
* SelectionDAGBuilder.cpp:
  Fix infinite loop when f128 type can have
  VT == TLI.getTypeToTransformTo(Ctx, VT).
* Add unit tests for x86-64 fp128 type.

Differential Revision: http://reviews.llvm.org/D11438



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255558 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-12-14 22:08:36 +00:00
Elena Demikhovsky b23b2fbd3a AVX-512: Added all SKX forms of GATHER instructions. 
Added intrinsics.
Added encoding and tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240905 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-28 10:53:29 +00:00
Elena Demikhovsky 22debdcab6 X86-MPX: Implemented encoding for MPX instructions. 
Added encoding tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239403 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-09 13:02:10 +00:00
Elena Demikhovsky bf704ed348 AVX-512: Added VPMOVx2M instructions for SKX, 
fixed encoding of VPMOVM2x.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235385 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-21 14:38:31 +00:00
Craig Topper e2f7231e45 [X86] Add the remaining 11 possible exact ModRM formats. This makes their encodings linear which can then be used to simplify some other code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229279 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-15 04:16:44 +00:00
Craig Topper f3455f13a2 [X86] Add support for parsing and printing the mnemonic aliases for the XOP VPCOM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229078 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-13 07:42:25 +00:00
Craig Topper aef361807e [X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227302 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 10:09:56 +00:00
Craig Topper 896c1e9b70 [X86] Replace i32i8imm on SSE/AVX instructions with i32u8imm which will make the assembler bounds check them. It will also make them print as unsigned. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227032 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 02:21:16 +00:00