mirror of
https://github.com/ARMSX2/ARMSX2.git
synced 2026-08-24 16:50:16 -07:00
refractionpcsx2
fd1305e4da
Need to adjust GameDB entries for to remove ones no longer required, added EE Timing fix for SOCOM as that seems to fix it up like its sequel. Some misc changes too which are inconsequential (mostly formatting)
498 lines
13 KiB
C++
498 lines
13 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "Hardware.h"
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#include "Gif_Unit.h"
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#include "IopCommon.h"
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#include "ps2/HwInternal.h"
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#include "ps2/eeHwTraceLog.inl"
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#include "ps2/pgif.h"
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#include "SPU2/spu2.h"
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#include "R3000A.h"
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using namespace R5900;
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// Shift the middle 8 bits (bits 4-12) into the lower 8 bits.
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// This helps the compiler optimize the switch statement into a lookup table. :)
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#define HELPSWITCH(m) (((m)>>4) & 0xff)
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#define mcase(src) case HELPSWITCH(src)
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template< uint page > void __fastcall _hwWrite8(u32 mem, u8 value);
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template< uint page > void __fastcall _hwWrite16(u32 mem, u8 value);
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template< uint page > void __fastcall _hwWrite128(u32 mem, u8 value);
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template<uint page>
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void __fastcall _hwWrite32( u32 mem, u32 value )
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{
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pxAssume( (mem & 0x03) == 0 );
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// Notes:
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// All unknown registers on the EE are "reserved" as discarded writes and indeterminate
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// reads. Bus error is only generated for registers outside the first 16k of mapped
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// register space (which is handled by the VTLB mapping, so no need for checks here).
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#if PSX_EXTRALOGS
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if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("32bit Write to SIF Register %x value %x", mem, value);
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//if ((mem & 0x1000ff00) == 0x1000f200) DevCon.Warning("Write to SIF Register %x value %x", mem, value);
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#endif
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switch (page)
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{
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case 0x00: if (!rcntWrite32<0x00>(mem, value)) return; break;
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case 0x01: if (!rcntWrite32<0x01>(mem, value)) return; break;
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case 0x02:
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if (!ipuWrite32(mem, value)) return;
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break;
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case 0x04:
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case 0x05:
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case 0x06:
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case 0x07:
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{
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// [Ps2Confirm] Direct FIFO read/write behavior. We need to create a test that writes
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// data to one of the FIFOs and determine the result. I'm not quite sure offhand a good
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// way to do that --air
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// Current assumption is that 32-bit and 64-bit writes likely do 128-bit zero-filled
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// writes (upper 96 bits are 0, lower 32 bits are effective).
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u128 zerofill = u128::From32(0);
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zerofill._u32[(mem >> 2) & 0x03] = value;
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DevCon.WriteLn( Color_Cyan, "Writing 32-bit FIFO data (zero-extended to 128 bits)" );
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_hwWrite128<page>(mem & ~0x0f, &zerofill);
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}
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return;
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case 0x03:
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if (mem >= EEMemoryMap::VIF0_Start)
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{
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if(mem >= EEMemoryMap::VIF1_Start)
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{
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if (!vifWrite32<1>(mem, value)) return;
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}
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else
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{
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if (!vifWrite32<0>(mem, value)) return;
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}
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}
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else iswitch(mem)
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{
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icase(GIF_CTRL)
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{
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// Not exactly sure what RST needs to do
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gifRegs.ctrl.write(value & 9);
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if (gifRegs.ctrl.RST) {
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GUNIT_LOG("GIF CTRL - Reset");
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gifUnit.Reset(true); // Should it reset gsSIGNAL?
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//gifUnit.ResetRegs();
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}
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gifRegs.stat.PSE = gifRegs.ctrl.PSE;
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return;
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}
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icase(GIF_MODE)
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{
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gifRegs.mode.write(value);
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//Need to kickstart the GIF if the M3R mask comes off
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if (gifRegs.stat.M3R == 1 && gifRegs.mode.M3R == 0 && (gifch.chcr.STR || gif_fifo.fifoSize))
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{
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DevCon.Warning("GIF Mode cancelling P3 Disable");
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CPU_INT(DMAC_GIF, 8);
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}
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gifRegs.stat.M3R = gifRegs.mode.M3R;
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gifRegs.stat.IMT = gifRegs.mode.IMT;
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return;
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}
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}
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break;
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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case 0x0c:
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case 0x0d:
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case 0x0e:
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if (!dmacWrite32<page>(mem, value)) return;
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break;
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case 0x0f:
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{
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switch( HELPSWITCH(mem) )
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{
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mcase(INTC_STAT):
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psHu32(INTC_STAT) &= ~value;
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//cpuTestINTCInts();
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return;
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mcase(INTC_MASK):
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psHu32(INTC_MASK) ^= (u16)value;
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cpuTestINTCInts();
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return;
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mcase(SIO_TXFIFO):
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{
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u8* woot = (u8*)&value;
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// [Ps2Confirm] What happens when we write 32 bit values to SIO_TXFIFO?
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// If it works like the IOP, then all 32 bits are written to the FIFO in
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// order. PCSX2 up to this point simply ignored non-8bit writes to this port.
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_hwWrite8<0x0f>(SIO_TXFIFO, woot[0]);
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_hwWrite8<0x0f>(SIO_TXFIFO, woot[1]);
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_hwWrite8<0x0f>(SIO_TXFIFO, woot[2]);
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_hwWrite8<0x0f>(SIO_TXFIFO, woot[3]);
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}
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return;
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mcase(SBUS_F200):
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// Performs a standard psHu32 assignment (which is the default action anyway).
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//psHu32(mem) = value;
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break;
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mcase(SBUS_F220):
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psHu32(mem) |= value;
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return;
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mcase(SBUS_F230):
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psHu32(mem) &= ~value;
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return;
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mcase(SBUS_F240) :
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if (value & (1 << 19))
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{
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u32 cycle = psxRegs.cycle;
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//pgifInit();
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psxReset();
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PSXCLK = 33868800;
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SPU2ps1reset();
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setPs1CDVDSpeed(cdvd.Speed);
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psxHu32(0x1f801450) = 0x8;
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psxHu32(0x1f801078) = 1;
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psxRegs.cycle = cycle;
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}
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if(!(value & 0x100))
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psHu32(mem) &= ~0x100;
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else
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psHu32(mem) |= 0x100;
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return;
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mcase(SBUS_F260):
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#if PSX_EXTRALOGS
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DevCon.Warning("Write SBUS_F260 %x ", psHu32(SBUS_F260));
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#endif
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psHu32(mem) = value;
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return;
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// TODO: psx handling is done in the default case. Keep the code until we decide if we decide which interface to use (sif2/Pgif dma)
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#if 0
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mcase(SBUS_F300) :
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psxHu32(0x1f801814) = value;
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/*
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if (sif2.fifo.size == 0) psxHu32(0x1f801814) |= 0x4000000;
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switch ((psxHu32(HW_PS1_GPU_STATUS) >> 29) & 0x3)
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{
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case 0x0:
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//DevCon.Warning("Set DMA Mode OFF");
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psxHu32(HW_PS1_GPU_STATUS) &= ~0x2000000;
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break;
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case 0x1:
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//DevCon.Warning("Set DMA Mode FIFO");
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psxHu32(HW_PS1_GPU_STATUS) |= 0x2000000;
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break;
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case 0x2:
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//DevCon.Warning("Set DMA Mode CPU->GPU");
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psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x10000000) >> 3);
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break;
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case 0x3:
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//DevCon.Warning("Set DMA Mode GPUREAD->CPU");
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psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x8000000) >> 2);
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break;
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}*/
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//psHu32(mem) = 0;
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return;
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mcase(SBUS_F380) :
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psHu32(mem) = value;
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return;
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#endif
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mcase(MCH_RICM)://MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5
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if ((((value >> 16) & 0xFFF) == 0x21) && (((value >> 6) & 0xF) == 1) && (((psHu32(0xf440) >> 7) & 1) == 0))//INIT & SRP=0
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rdram_sdevid = 0; // if SIO repeater is cleared, reset sdevid
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psHu32(mem) = value & ~0x80000000; //kill the busy bit
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return;
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mcase(MCH_DRD):
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// Performs a standard psHu32 assignment (which is the default action anyway).
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//psHu32(mem) = value;
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break;
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mcase(DMAC_ENABLEW):
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if (!dmacWrite32<0x0f>(DMAC_ENABLEW, value)) return;
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break;
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default:
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// TODO: psx add the real address in a sbus mcase
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if (((mem & 0x1FFFFFFF) >= EEMemoryMap::SBUS_PS1_Start) && ((mem & 0x1FFFFFFF) < EEMemoryMap::SBUS_PS1_End)) {
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PGIFw((mem & 0x1FFFFFFF), value);
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return;
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}
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//mcase(SIO_ISR):
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//mcase(0x1000f410):
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// Mystery Regs! No one knows!?
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// (unhandled so fall through to default)
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}
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}
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break;
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}
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psHu32(mem) = value;
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}
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template<uint page>
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void __fastcall hwWrite32( u32 mem, u32 value )
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{
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eeHwTraceLog( mem, value, false );
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_hwWrite32<page>( mem, value );
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}
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// --------------------------------------------------------------------------------------
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// hwWrite8 / hwWrite16 / hwWrite64 / hwWrite128
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// --------------------------------------------------------------------------------------
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template< uint page >
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void __fastcall _hwWrite8(u32 mem, u8 value)
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{
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#if PSX_EXTRALOGS
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if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("8bit Write to SIF Register %x value %x wibble", mem, value);
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#endif
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iswitch (mem)
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icase(SIO_TXFIFO)
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{
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static bool iggy_newline = false;
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static char sio_buffer[1024];
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static int sio_count;
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if (value == '\r')
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{
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iggy_newline = true;
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sio_buffer[sio_count++] = '\n';
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}
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else if (!iggy_newline || (value != '\n'))
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{
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iggy_newline = false;
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sio_buffer[sio_count++] = value;
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}
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if ((sio_count == ArraySize(sio_buffer)-1) || (sio_count != 0 && sio_buffer[sio_count-1] == '\n'))
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{
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sio_buffer[sio_count] = 0;
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eeConLog( ShiftJIS_ConvertString(sio_buffer) );
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sio_count = 0;
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}
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return;
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}
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switch(mem & ~3)
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{
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case DMAC_STAT:
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case INTC_STAT:
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case INTC_MASK:
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case DMAC_FAKESTAT:
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DevCon.Warning ( "8bit write mem = %x value %x", mem, value );
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_hwWrite32<page>(mem & ~3, (u32)value << (mem & 3) * 8);
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return;
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}
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u32 merged = _hwRead32<page,false>(mem & ~0x03);
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((u8*)&merged)[mem & 0x3] = value;
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_hwWrite32<page>(mem & ~0x03, merged);
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}
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template< uint page >
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void __fastcall hwWrite8(u32 mem, u8 value)
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{
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eeHwTraceLog( mem, value, false );
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_hwWrite8<page>(mem, value);
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}
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template< uint page >
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void __fastcall _hwWrite16(u32 mem, u16 value)
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{
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pxAssume( (mem & 0x01) == 0 );
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#if PSX_EXTRALOGS
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if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("16bit Write to SIF Register %x wibble", mem);
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#endif
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switch(mem & ~3)
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{
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case DMAC_STAT:
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case INTC_STAT:
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case INTC_MASK:
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case DMAC_FAKESTAT:
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DevCon.Warning ( "16bit write mem = %x value %x", mem, value );
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_hwWrite32<page>(mem & ~3, (u32)value << (mem & 3) * 8);
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return;
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}
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u32 merged = _hwRead32<page,false>(mem & ~0x03);
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((u16*)&merged)[(mem>>1) & 0x1] = value;
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hwWrite32<page>(mem & ~0x03, merged);
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}
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template< uint page >
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void __fastcall hwWrite16(u32 mem, u16 value)
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{
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eeHwTraceLog( mem, value, false );
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_hwWrite16<page>(mem, value);
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}
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template<uint page>
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void __fastcall _hwWrite64( u32 mem, const mem64_t* srcval )
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{
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pxAssume( (mem & 0x07) == 0 );
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// * Only the IPU has true 64 bit registers.
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// * FIFOs have 128 bit registers that are probably zero-fill.
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// * All other registers likely disregard the upper 32-bits and simply act as normal
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// 32-bit writes.
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#if PSX_EXTRALOGS
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if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("64bit Write to SIF Register %x wibble", mem);
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#endif
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switch (page)
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{
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case 0x02:
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if (!ipuWrite64(mem, *srcval)) return;
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break;
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case 0x04:
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case 0x05:
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case 0x06:
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case 0x07:
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{
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DevCon.WriteLn( Color_Cyan, "Writing 64-bit FIFO data (zero-extended to 128 bits)" );
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u128 zerofill = u128::From32(0);
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zerofill._u64[(mem >> 3) & 0x01] = *srcval;
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hwWrite128<page>(mem & ~0x0f, &zerofill);
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}
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return;
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default:
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// disregard everything except the lower 32 bits.
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// ... and skip the 64 bit writeback since the 32-bit one will suffice.
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hwWrite32<page>( mem, ((u32*)srcval)[0] );
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return;
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}
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psHu64(mem) = *srcval;
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}
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template<uint page>
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void __fastcall hwWrite64( u32 mem, const mem64_t* srcval )
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{
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eeHwTraceLog( mem, *srcval, false );
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_hwWrite64<page>(mem, srcval);
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}
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template< uint page >
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void __fastcall _hwWrite128(u32 mem, const mem128_t* srcval)
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{
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pxAssume( (mem & 0x0f) == 0 );
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// FIFOs are the only "legal" 128 bit registers. Handle them first.
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// all other registers fall back on the 64-bit handler (and from there
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// most of them fall back to the 32-bit handler).
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#if PSX_EXTRALOGS
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if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("128bit Write to SIF Register %x wibble", mem);
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#endif
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switch (page)
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{
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case 0x04:
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WriteFIFO_VIF0(srcval);
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return;
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case 0x05:
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WriteFIFO_VIF1(srcval);
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return;
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case 0x06:
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WriteFIFO_GIF(srcval);
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return;
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case 0x07:
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if (mem & 0x10)
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{
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WriteFIFO_IPUin(srcval);
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}
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else
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{
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// [Ps2Confirm] Most likely writes to IPUout will be silently discarded. A test
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// to confirm such would be easy -- just dump some data to FIFO_IPUout and see
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// if the program causes BUSERR or something on the PS2.
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//WriteFIFO_IPUout(srcval);
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}
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return;
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case 0x0F:
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// todo: psx mode: this is new
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if (((mem & 0x1FFFFFFF) >= EEMemoryMap::SBUS_PS1_Start) && ((mem & 0x1FFFFFFF) < EEMemoryMap::SBUS_PS1_End)) {
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PGIFwQword((mem & 0x1FFFFFFF), (void*)srcval);
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return;
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}
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default: break;
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}
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// All upper bits of all non-FIFO 128-bit HW writes are almost certainly disregarded. --air
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hwWrite64<page>(mem, (mem64_t*)srcval);
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//CopyQWC(&psHu128(mem), srcval);
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}
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template< uint page >
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void __fastcall hwWrite128(u32 mem, const mem128_t* srcval)
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{
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eeHwTraceLog( mem, *srcval, false );
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_hwWrite128<page>(mem, srcval);
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}
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#define InstantizeHwWrite(pageidx) \
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template void __fastcall hwWrite8<pageidx>(u32 mem, mem8_t value); \
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template void __fastcall hwWrite16<pageidx>(u32 mem, mem16_t value); \
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template void __fastcall hwWrite32<pageidx>(u32 mem, mem32_t value); \
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template void __fastcall hwWrite64<pageidx>(u32 mem, const mem64_t* srcval); \
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template void __fastcall hwWrite128<pageidx>(u32 mem, const mem128_t* srcval);
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InstantizeHwWrite(0x00); InstantizeHwWrite(0x08);
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InstantizeHwWrite(0x01); InstantizeHwWrite(0x09);
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InstantizeHwWrite(0x02); InstantizeHwWrite(0x0a);
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InstantizeHwWrite(0x03); InstantizeHwWrite(0x0b);
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InstantizeHwWrite(0x04); InstantizeHwWrite(0x0c);
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InstantizeHwWrite(0x05); InstantizeHwWrite(0x0d);
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InstantizeHwWrite(0x06); InstantizeHwWrite(0x0e);
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InstantizeHwWrite(0x07); InstantizeHwWrite(0x0f);
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