pstef 8542a9c38a EE/FPU: compute mode 3 in the relocated domain ...

iFPUd widened every operand with ToDoubleFrom: eleven instructions
branching on exponent field 0xff, since a PS2 single with that exponent
is an ordinary large number IEEE reads as Inf or NaN. Against a
relocated slot the widening is one Fmul, and a compare goes from 34.75
host instructions to 8.75. CVT.W loses its NaN fix-up the same way,
leaving Fcvtzs.

Which format the file is in follows the clamp mode, so modes 0-2 keep
the architectural word in the low half. FPRreg's accessors read the
format and the emitters read the mode; the two engines meet at the
boundaries the word is still observable at -- MFC1, MTC1, MOV.S, the two
conversions, LWC1, SWC1 and the allocator's fill and spill.

The unscale factor takes q11 and d10's mask moves to the relocated
layout, so the allocator's callee-saved range is q12-q15.

2026-08-15 23:57:24 +02:00

..

ctest

EE/FPU: compute mode 3 in the relocated domain

2026-08-15 23:57:24 +02:00

run_test.pl

misc: A couple of more leftovers from SPU2 merge.

2021-01-04 02:07:30 +01:00