mirror of
https://github.com/ARMSX2/ARMSX2.git
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b884f93dd7
CMake/preset wiring for the ARM64 target, the vixl C++20 enum-conversion warning suppression, PmuCounters (cycle/instret PMU reads), and the Perf jitdump dir/enable controls (EmuConfig.Profiler.EnablePerfDump, redirected out of /tmp into the cache dir). Plus small platform/build fixes (ALSA thread naming, SmallString, X11 guards, ARM MIDR CPU-name fallback, gcc lambda decay). The ARCH_ARM64 status banner now reflects that EE/IOP/VU recompilers are all implemented. Co-Authored-By: Ryan Walklin <ryan@testtoast.com> Co-Authored-By: Brian Degenhardt <bmd@bmdhacks.com> Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
103 lines
3.2 KiB
C++
103 lines
3.2 KiB
C++
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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// Smoke tests for PmuCounters. The tests SUCCEED-and-skip-assertions when
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// perf_event_open is restricted (perf_event_paranoid >= 2 without
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// CAP_PERFMON), to avoid CI failures on locked-down hosts.
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#include "common/PmuCounters.h"
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#include <gtest/gtest.h>
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#include <chrono>
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#include <thread>
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TEST(PmuCounters, OpenSucceedsOrSkipsCleanly)
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{
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PmuCounters::Group g;
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const bool opened = g.Open();
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if (!opened)
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{
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GTEST_SKIP() << "perf_event_open denied — set kernel.perf_event_paranoid=1 "
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"to enable this test on a development box.";
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}
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EXPECT_TRUE(g.IsOpen());
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// Leader is always installed if Open() returned true.
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EXPECT_TRUE(g.IsAvailable(PmuCounters::CpuCycles));
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}
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TEST(PmuCounters, MeasureRecordsNonZeroCyclesAndInstructions)
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{
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PmuCounters::Group g;
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if (!g.Open())
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GTEST_SKIP() << "perf_event_open denied";
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// Busy work the optimizer can't prove dead — accumulator escapes via the
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// gtest assertion below.
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volatile u64 sink = 0;
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const auto values = g.Measure([&]() {
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for (u64 i = 0; i < 1'000'000; ++i)
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sink += i * 7u;
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});
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EXPECT_GT(values[PmuCounters::CpuCycles], 0u);
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EXPECT_GT(values[PmuCounters::InstructionsRetired], 0u);
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// Instructions ≈ same order as cycles for this loop. Loose bound so the
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// test does not need to reason about IPC on whichever host is running.
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EXPECT_GT(values[PmuCounters::InstructionsRetired],
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values[PmuCounters::CpuCycles] / 100u);
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(void)sink; // placate the optimizer; the volatile load is what matters
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}
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TEST(PmuCounters, ResetClearsCounts)
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{
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PmuCounters::Group g;
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if (!g.Open())
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GTEST_SKIP() << "perf_event_open denied";
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volatile u64 sink = 0;
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g.Enable();
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for (u64 i = 0; i < 10'000; ++i)
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sink += i;
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g.Disable();
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const auto first = g.Read();
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EXPECT_GT(first[PmuCounters::CpuCycles], 0u);
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// Reset() reads back exactly zero only because the group is Disabled here:
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// PERF_EVENT_IOC_RESET on a still-enabled leader can race in-flight counting
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// and return a small non-zero value. Don't copy this == 0 assertion into a
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// context where the counters are still running (Read() itself is allowed
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// while running, but a reset-then-read-zero is not).
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g.Reset();
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const auto after_reset = g.Read();
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EXPECT_EQ(after_reset[PmuCounters::CpuCycles], 0u);
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EXPECT_EQ(after_reset[PmuCounters::InstructionsRetired], 0u);
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(void)sink;
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}
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TEST(PmuCounters, NameReturnsStableLabels)
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{
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EXPECT_STREQ("cycles", PmuCounters::Name(PmuCounters::CpuCycles));
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EXPECT_STREQ("instructions", PmuCounters::Name(PmuCounters::InstructionsRetired));
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EXPECT_STREQ("branch-misses", PmuCounters::Name(PmuCounters::BranchMisses));
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EXPECT_STREQ("branches", PmuCounters::Name(PmuCounters::BranchInstructions));
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EXPECT_STREQ("L1-dcache-load-misses", PmuCounters::Name(PmuCounters::L1dCacheRefills));
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}
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TEST(PmuCounters, ReadReturnsZeroForUnavailableCounter)
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{
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PmuCounters::Group g;
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if (!g.Open())
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GTEST_SKIP() << "perf_event_open denied";
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const auto values = g.Read();
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for (int i = 0; i < PmuCounters::Count; ++i)
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{
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const auto c = static_cast<PmuCounters::Counter>(i);
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if (!g.IsAvailable(c))
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EXPECT_EQ(values[i], 0u) << PmuCounters::Name(c);
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}
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}
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