mirror of
https://github.com/ARMSX2/ARMSX2.git
synced 2026-08-24 16:50:16 -07:00
369 lines
9.5 KiB
C++
369 lines
9.5 KiB
C++
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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// Important Note to Future Developers:
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// None of the COP0 instructions are really critical performance items,
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// so don't waste time converting any more them into recompiled code
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// unless it can make them nicely compact. Calling the C versions will
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// suffice.
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#include "Common.h"
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#include "R5900OpcodeTables.h"
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#include "iR5900.h"
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#include "iCOP0.h"
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namespace Interp = R5900::Interpreter::OpcodeImpl::COP0;
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using namespace x86Emitter;
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namespace R5900 {
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namespace Dynarec {
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namespace OpcodeImpl {
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namespace COP0 {
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/*********************************************************
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* COP0 opcodes *
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* *
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*********************************************************/
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// emits "setup" code for a COP0 branch test. The instruction immediately following
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// this should be a conditional Jump -- JZ or JNZ normally.
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static void _setupBranchTest()
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{
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_eeFlushAllDirty();
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// COP0 branch conditionals are based on the following equation:
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// (((psHu16(DMAC_STAT) | ~psHu16(DMAC_PCR)) & 0x3ff) == 0x3ff)
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// BC0F checks if the statement is false, BC0T checks if the statement is true.
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// note: We only want to compare the 16 bit values of DMAC_STAT and PCR.
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// But using 32-bit loads here is ok (and faster), because we mask off
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// everything except the lower 10 bits away.
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xMOV(eax, ptr[(&psHu32(DMAC_PCR))]);
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xMOV(ecx, 0x3ff); // ECX is our 10-bit mask var
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xNOT(eax);
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xOR(eax, ptr[(&psHu32(DMAC_STAT))]);
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xAND(eax, ecx);
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xCMP(eax, ecx);
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}
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void recBC0F()
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{
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const u32 branchTo = ((s32)_Imm_ * 4) + pc;
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const bool swap = TrySwapDelaySlot(0, 0, 0, false);
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_setupBranchTest();
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recDoBranchImm(branchTo, JE32(0), false, swap);
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}
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void recBC0T()
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{
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const u32 branchTo = ((s32)_Imm_ * 4) + pc;
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const bool swap = TrySwapDelaySlot(0, 0, 0, false);
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_setupBranchTest();
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recDoBranchImm(branchTo, JNE32(0), false, swap);
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}
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void recBC0FL()
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{
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const u32 branchTo = ((s32)_Imm_ * 4) + pc;
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_setupBranchTest();
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recDoBranchImm(branchTo, JE32(0), true, false);
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}
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void recBC0TL()
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{
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const u32 branchTo = ((s32)_Imm_ * 4) + pc;
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_setupBranchTest();
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recDoBranchImm(branchTo, JNE32(0), true, false);
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}
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void recTLBR() { recCall(Interp::TLBR); }
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void recTLBP() { recCall(Interp::TLBP); }
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void recTLBWI() { recCall(Interp::TLBWI); }
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void recTLBWR() { recCall(Interp::TLBWR); }
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void recERET()
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{
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recBranchCall(Interp::ERET);
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}
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void recEI()
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{
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// must branch after enabling interrupts, so that anything
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// pending gets triggered properly.
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recBranchCall(Interp::EI);
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}
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void recDI()
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{
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//// No need to branch after disabling interrupts...
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//iFlushCall(0);
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//xMOV(eax, ptr[&cpuRegs.cycle ]);
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//xMOV(ptr[&g_nextBranchCycle], eax);
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//xFastCall((void*)(uptr)Interp::DI );
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// Fixes booting issues in the following games:
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// Jak X, Namco 50th anniversary, Spongebob the Movie, Spongebob Battle for Bikini Bottom,
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// The Incredibles, The Incredibles rize of the underminer, Soukou kihei armodyne, Garfield Saving Arlene, Tales of Fandom Vol. 2.
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if (!g_recompilingDelaySlot)
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recompileNextInstruction(false, false); // DI execution is delayed by one instruction
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xMOV(eax, ptr[&cpuRegs.CP0.n.Status]);
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xTEST(eax, 0x20006); // EXL | ERL | EDI
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xForwardJNZ8 iHaveNoIdea;
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xTEST(eax, 0x18); // KSU
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xForwardJNZ8 inUserMode;
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iHaveNoIdea.SetTarget();
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xAND(eax, ~(u32)0x10000); // EIE
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xMOV(ptr[&cpuRegs.CP0.n.Status], eax);
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inUserMode.SetTarget();
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}
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#ifndef CP0_RECOMPILE
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REC_SYS(MFC0);
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REC_SYS(MTC0);
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#else
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void recMFC0()
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{
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if (_Rd_ == 9)
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{
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// This case needs to be handled even if the write-back is ignored (_Rt_ == 0 )
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xMOV(rcx, ptr64[&cpuRegs.cycle]);
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xADD(rcx, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rcx); // update cycles
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xMOV(rax, rcx);
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xSUB(rax, ptr[&cpuRegs.lastCOP0Cycle]);
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xADD(ptr[&cpuRegs.CP0.n.Count], rax);
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xMOV(ptr[&cpuRegs.lastCOP0Cycle], rcx);
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if (!_Rt_)
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return;
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const int regt = _Rt_ ? _allocX86reg(X86TYPE_GPR, _Rt_, MODE_WRITE) : -1;
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xMOVSX(xRegister64(regt), ptr32[&cpuRegs.CP0.r[_Rd_]]);
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return;
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}
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if (!_Rt_)
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return;
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if (_Rd_ == 25)
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{
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if (0 == (_Imm_ & 1)) // MFPS, register value ignored
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{
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const int regt = _allocX86reg(X86TYPE_GPR, _Rt_, MODE_WRITE);
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xMOVSX(xRegister64(regt), ptr32[&cpuRegs.PERF.n.pccr]);
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}
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else if (0 == (_Imm_ & 2)) // MFPC 0, only LSB of register matters
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{
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iFlushCall(FLUSH_INTERPRETER);
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xMOV(rax, ptr64[&cpuRegs.cycle]);
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xADD(rax, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rax); // update cycles
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xFastCall((void*)COP0_UpdatePCCR);
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const int regt = _allocX86reg(X86TYPE_GPR, _Rt_, MODE_WRITE);
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xMOVSX(xRegister64(regt), ptr32[&cpuRegs.PERF.n.pcr0]);
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}
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else // MFPC 1
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{
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iFlushCall(FLUSH_INTERPRETER);
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xMOV(rax, ptr64[&cpuRegs.cycle]);
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xADD(rax, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rax); // update cycles
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xFastCall((void*)COP0_UpdatePCCR);
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const int regt = _allocX86reg(X86TYPE_GPR, _Rt_, MODE_WRITE);
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xMOVSX(xRegister64(regt), ptr32[&cpuRegs.PERF.n.pcr1]);
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}
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return;
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}
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else if (_Rd_ == 24)
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{
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COP0_LOG("MFC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
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return;
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}
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const int regt = _allocX86reg(X86TYPE_GPR, _Rt_, MODE_WRITE);
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xMOVSX(xRegister64(regt), ptr32[&cpuRegs.CP0.r[_Rd_]]);
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}
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void recMTC0()
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{
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if (GPR_IS_CONST1(_Rt_))
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{
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switch (_Rd_)
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{
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case 12:
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iFlushCall(FLUSH_INTERPRETER);
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xMOV(rax, ptr64[&cpuRegs.cycle]);
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xADD(rax, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rax); // update cycles
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xFastCall((void*)WriteCP0Status, g_cpuConstRegs[_Rt_].UL[0]);
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break;
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case 16:
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iFlushCall(FLUSH_INTERPRETER);
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xFastCall((void*)WriteCP0Config, g_cpuConstRegs[_Rt_].UL[0]);
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break;
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case 9:
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xMOV(rcx, ptr64[&cpuRegs.cycle]);
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xADD(rcx, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rcx); // update cycles
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xMOV(ptr64[&cpuRegs.lastCOP0Cycle], rcx);
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xMOV(ptr32[&cpuRegs.CP0.r[9]], g_cpuConstRegs[_Rt_].UL[0]);
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break;
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case 25:
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if (0 == (_Imm_ & 1)) // MTPS
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{
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if (0 != (_Imm_ & 0x3E)) // only effective when the register is 0
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break;
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// Updates PCRs and sets the PCCR.
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iFlushCall(FLUSH_INTERPRETER);
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xMOV(rax, ptr64[&cpuRegs.cycle]);
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xADD(rax, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rax); // update cycles
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xFastCall((void*)COP0_UpdatePCCR);
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xMOV(ptr32[&cpuRegs.PERF.n.pccr], g_cpuConstRegs[_Rt_].UL[0]);
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xFastCall((void*)COP0_DiagnosticPCCR);
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}
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else if (0 == (_Imm_ & 2)) // MTPC 0, only LSB of register matters
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{
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xMOV(rax, ptr64[&cpuRegs.cycle]);
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xADD(rax, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rax); // update cycles
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xMOV(ptr32[&cpuRegs.PERF.n.pcr0], g_cpuConstRegs[_Rt_].UL[0]);
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xMOV(ptr64[&cpuRegs.lastPERFCycle[0]], rax);
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}
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else // MTPC 1
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{
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xMOV(rax, ptr64[&cpuRegs.cycle]);
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xADD(rax, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rax); // update cycles
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xMOV(ptr32[&cpuRegs.PERF.n.pcr1], g_cpuConstRegs[_Rt_].UL[0]);
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xMOV(ptr64[&cpuRegs.lastPERFCycle[1]], rax);
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}
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break;
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case 24:
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COP0_LOG("MTC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
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break;
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default:
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xMOV(ptr32[&cpuRegs.CP0.r[_Rd_]], g_cpuConstRegs[_Rt_].UL[0]);
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break;
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}
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}
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else
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{
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switch (_Rd_)
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{
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case 12:
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_eeMoveGPRtoR(arg1reg, _Rt_);
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iFlushCall(FLUSH_INTERPRETER);
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xMOV(rax, ptr64[&cpuRegs.cycle]);
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xADD(rax, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rax); // update cycles
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xFastCall((void*)WriteCP0Status);
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break;
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case 16:
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_eeMoveGPRtoR(arg1reg, _Rt_);
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iFlushCall(FLUSH_INTERPRETER);
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xFastCall((void*)WriteCP0Config);
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break;
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case 9:
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xMOV(rcx, ptr64[&cpuRegs.cycle]);
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xADD(rcx, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rcx); // update cycles
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_eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[9], _Rt_);
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xMOV(ptr64[&cpuRegs.lastCOP0Cycle], rcx);
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break;
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case 25:
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if (0 == (_Imm_ & 1)) // MTPS
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{
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if (0 != (_Imm_ & 0x3E)) // only effective when the register is 0
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break;
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iFlushCall(FLUSH_INTERPRETER);
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xMOV(rax, ptr64[&cpuRegs.cycle]);
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xADD(rax, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rax); // update cycles
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xFastCall((void*)COP0_UpdatePCCR);
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_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pccr, _Rt_);
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xFastCall((void*)COP0_DiagnosticPCCR);
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}
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else if (0 == (_Imm_ & 2)) // MTPC 0, only LSB of register matters
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{
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xMOV(rcx, ptr64[&cpuRegs.cycle]);
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xADD(rcx, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rcx); // update cycles
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_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr0, _Rt_);
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xMOV(ptr64[&cpuRegs.lastPERFCycle[0]], rcx);
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}
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else // MTPC 1
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{
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xMOV(rcx, ptr64[&cpuRegs.cycle]);
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xADD(rcx, scaleblockcycles_clear());
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xMOV(ptr64[&cpuRegs.cycle], rcx); // update cycles
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_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr1, _Rt_);
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xMOV(ptr64[&cpuRegs.lastPERFCycle[1]], rcx);
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}
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break;
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case 24:
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COP0_LOG("MTC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
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break;
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default:
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_eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[_Rd_], _Rt_);
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break;
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}
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}
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}
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#endif
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/*void rec(COP0) {
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}
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void rec(BC0F) {
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}
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void rec(BC0T) {
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}
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void rec(BC0FL) {
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}
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void rec(BC0TL) {
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}
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void rec(TLBR) {
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}
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void rec(TLBWI) {
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}
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void rec(TLBWR) {
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}
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void rec(TLBP) {
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}*/
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} // namespace COP0
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} // namespace OpcodeImpl
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} // namespace Dynarec
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} // namespace R5900
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