mirror of
https://github.com/ARMSX2/ARMSX2.git
synced 2026-08-24 16:50:16 -07:00
Brian Degenhardt
2ce8c27e13
Eleven commented-out defines in iR5900-arm64.h, each selecting the interpreter for one opcode category (branch, jump, move, shift, ALU, arith-imm, mult/div, memory, COP0, FPU, COP2), consumed by twelve #ifdef/#else/#endif pairs across eleven files. Using one meant editing the header and rebuilding. pcsx2-eerunner --rec-fallback <groups> does the same bisect at runtime with no rebuild and no source edit, over a full VM boot, so it stays game-faithful. The transform keeps every #else body byte for byte - the diff is deletions only, no added or reindented lines. Also drops two comments that referenced the defines. recompiler_tests: 1513 passed, 2 skipped, 0 failed.
606 lines
16 KiB
C++
606 lines
16 KiB
C++
// SPDX-FileCopyrightText: 2026 yaps2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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// ARM64 EE Multiply/Divide Instruction Codegen — memory-based
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// MULT/DIV write to HI:LO registers, optionally Rd.
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// ARM64 has native SMULL/UMULL and SDIV/UDIV.
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// All operands via cpuRegs memory.
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#include "arm64/iR5900-arm64.h"
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namespace a64 = vixl::aarch64;
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namespace R5900 {
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namespace Dynarec {
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namespace OpcodeImpl {
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namespace Interp = R5900::Interpreter::OpcodeImpl;
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// Fetch Rs/Rt lower 32 bits for the mul/div ops. Substitution-aware
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// (EE-SRA 2 WS-C6): returns the pin / MODE_READ allocator reg directly (zero
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// insns) or materializes into w1/w9. Every caller sits right after
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// _eeFlushAllDirty (the post-flush coherence contract), and every consumer
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// below is read-only on the sources — EXCEPT the DIVU remainder Msub, which
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// therefore targets w10 rather than writing a source in place.
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//
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// ⚠️ Scratch choice: w9/w10 (non-allocatable), NOT w2/w3. A resident FCR31
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// (ARM64TYPE_FPRC, GE-12) lives in the {x2-x7, x14, x15} pool ACROSS ops —
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// _eeFlushAllDirty writes it back but keeps residency, so a raw w2/w3
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// clobber here poisons the flag a later BC1x/CFC1/DIV-flag-RMW reads (same
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// class as the fpuEmitGuardedAddSub SotC bug; pinned by
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// EeRecFpu.CompareSurvivesInterposed{Mult,Div}).
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static a64::Register loadRs32()
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{
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if (GPR_IS_CONST1(_Rs_))
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{
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armAsm->Mov(a64::w1, g_cpuConstRegs[_Rs_].UL[0]);
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return a64::w1;
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}
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return _eeGetGPRSourceReg(a64::w1, _Rs_);
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}
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static a64::Register loadRt32()
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{
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if (GPR_IS_CONST1(_Rt_))
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{
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armAsm->Mov(a64::w9, g_cpuConstRegs[_Rt_].UL[0]);
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return a64::w9;
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}
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return _eeGetGPRSourceReg(a64::w9, _Rt_);
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}
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// Write LO and HI from 64-bit result in x0 (clobbers x0)
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// lo = lower 32, hi = upper 32, both sign-extended to 64 bits
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static void recWritebackHILO(bool upper)
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{
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armAsm->Sxtw(RXSCRATCH, a64::w0);
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armAsm->Str(RXSCRATCH, armCpuRegMem(upper ? &cpuRegs.LO.UD[1] : &cpuRegs.LO.UD[0]));
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// Asr(x0, #32) already yields the sign-extended upper half — store it directly (GE-01).
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armAsm->Asr(a64::x0, a64::x0, 32);
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armAsm->Str(a64::x0, armCpuRegMem(upper ? &cpuRegs.HI.UD[1] : &cpuRegs.HI.UD[0]));
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}
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// Write Rd from the sign-extended LO value recWritebackHILO leaves in
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// RXSCRATCH (GE-09). Contract: every caller invokes this IMMEDIATELY after
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// recWritebackHILO — the old Ldr from LO.UD[half] was a store→load
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// round-trip on the value computed one instruction earlier. Same helper
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// serves both pipelines (the RXSCRATCH value is the rd value either way).
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// _deleteEEreg's NEON writeback emits only Str q/pin Movs — x8 untouched.
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static void recWritebackRd()
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{
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if (!_Rd_) return;
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_deleteEEreg(_Rd_, 0);
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GPR_DEL_CONST(_Rd_);
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_eeStoreGPRDestReg(_Rd_, RXSCRATCH);
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}
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//// MULT — signed 32-bit multiply, result in HI:LO, optionally Rd
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void recMULT()
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{
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if (GPR_IS_CONST2(_Rs_, _Rt_))
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{
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s64 result = (s64)(s32)g_cpuConstRegs[_Rs_].UL[0] * (s64)(s32)g_cpuConstRegs[_Rt_].UL[0];
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armAsm->Mov(RXSCRATCH, (s64)(s32)(u32)result);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[0]));
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armAsm->Mov(RXSCRATCH, (s64)(s32)(u32)(result >> 32));
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[0]));
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if (_Rd_)
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{
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_deleteEEreg(_Rd_, 0);
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g_cpuConstRegs[_Rd_].SD[0] = (s32)(u32)result;
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GPR_SET_CONST(_Rd_);
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}
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return;
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}
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_eeFlushAllDirty();
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const a64::Register rs32 = loadRs32();
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const a64::Register rt32 = loadRt32();
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armAsm->Smull(a64::x0, rs32, rt32);
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recWritebackHILO(false);
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recWritebackRd();
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}
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//// MULTU — unsigned 32-bit multiply
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void recMULTU()
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{
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if (GPR_IS_CONST2(_Rs_, _Rt_))
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{
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u64 result = (u64)g_cpuConstRegs[_Rs_].UL[0] * (u64)g_cpuConstRegs[_Rt_].UL[0];
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armAsm->Mov(RXSCRATCH, (s64)(s32)(u32)result);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[0]));
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armAsm->Mov(RXSCRATCH, (s64)(s32)(u32)(result >> 32));
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[0]));
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if (_Rd_)
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{
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_deleteEEreg(_Rd_, 0);
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g_cpuConstRegs[_Rd_].SD[0] = (s32)(u32)result;
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GPR_SET_CONST(_Rd_);
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}
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return;
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}
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_eeFlushAllDirty();
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const a64::Register rs32 = loadRs32();
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const a64::Register rt32 = loadRt32();
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armAsm->Umull(a64::x0, rs32, rt32);
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recWritebackHILO(false);
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recWritebackRd();
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}
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//// DIV — signed 32-bit divide. LO = quotient, HI = remainder.
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// PS2 div-by-zero: LO = (rs >= 0 ? -1 : 1), HI = rs (sign-extended into 64-bit
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// HI/LO). Matches the interpreter and the PS2 hardware spec.
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void recDIV()
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{
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if (GPR_IS_CONST2(_Rs_, _Rt_))
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{
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s32 rs = g_cpuConstRegs[_Rs_].SL[0];
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s32 rt = g_cpuConstRegs[_Rt_].SL[0];
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s32 lo, hi;
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if (rt == 0)
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{
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lo = (rs >= 0) ? -1 : 1;
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hi = rs;
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}
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else if (rs == (s32)0x80000000 && rt == -1)
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{
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lo = (s32)0x80000000;
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hi = 0;
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}
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else
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{
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lo = rs / rt;
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hi = rs % rt;
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}
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armAsm->Mov(RXSCRATCH, (s64)lo);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[0]));
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armAsm->Mov(RXSCRATCH, (s64)hi);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[0]));
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return;
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}
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_eeFlushAllDirty();
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const a64::Register rs32 = loadRs32();
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const a64::Register rt32 = loadRt32();
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// Branch on rt == 0 → div-by-zero handler.
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a64::Label divByZero;
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a64::Label done;
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armAsm->Cbz(rt32, &divByZero);
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// Normal path: SDIV w0 = rs/rt; MSUB w10 = rs - w0*rt (remainder).
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armAsm->Sdiv(a64::w0, rs32, rt32);
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armAsm->Msub(a64::w10, a64::w0, rt32, rs32);
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armAsm->B(&done);
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// Div-by-zero: w0 = (rs >= 0 ? -1 : 1), w10 = rs.
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// Cneg w0, w0, lt: if rs < 0, w0 = -(-1) = 1; else w0 = -1.
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armAsm->Bind(&divByZero);
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armAsm->Mov(a64::w0, -1);
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armAsm->Cmp(rs32, 0);
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armAsm->Cneg(a64::w0, a64::w0, a64::lt);
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armAsm->Mov(a64::w10, rs32); // HI = rs
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armAsm->Bind(&done);
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// Store LO = sign_extend(quotient or -1/1)
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armAsm->Sxtw(RXSCRATCH, a64::w0);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[0]));
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// Store HI = sign_extend(remainder or rs)
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armAsm->Sxtw(RXSCRATCH, a64::w10);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[0]));
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}
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//// DIVU — unsigned 32-bit divide. PS2 div-by-zero: LO = -1 (0xffffffff
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//// sign-extended), HI = rs.
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void recDIVU()
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{
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if (GPR_IS_CONST2(_Rs_, _Rt_))
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{
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u32 rs = g_cpuConstRegs[_Rs_].UL[0];
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u32 rt = g_cpuConstRegs[_Rt_].UL[0];
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s32 lo, hi;
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if (rt == 0)
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{
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lo = -1;
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hi = (s32)rs;
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}
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else
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{
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lo = (s32)(rs / rt);
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hi = (s32)(rs % rt);
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}
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armAsm->Mov(RXSCRATCH, (s64)lo);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[0]));
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armAsm->Mov(RXSCRATCH, (s64)hi);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[0]));
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return;
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}
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_eeFlushAllDirty();
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const a64::Register rs32 = loadRs32();
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const a64::Register rt32 = loadRt32();
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a64::Label divByZero;
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a64::Label done;
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armAsm->Cbz(rt32, &divByZero);
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// Normal path: UDIV w0; MSUB remainder into w10 — NOT in place over the Rs
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// source, which may be a pin (WS-C6 pin-safety; the old in-place form
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// predates operand substitution).
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armAsm->Udiv(a64::w0, rs32, rt32);
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armAsm->Msub(a64::w10, a64::w0, rt32, rs32);
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armAsm->B(&done);
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// Div-by-zero: w0 = -1; HI = rs.
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armAsm->Bind(&divByZero);
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armAsm->Mov(a64::w0, -1);
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armAsm->Mov(a64::w10, rs32);
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armAsm->Bind(&done);
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// Store LO = sign_extend(quotient or -1)
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armAsm->Sxtw(RXSCRATCH, a64::w0);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[0]));
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// Store HI = sign_extend(remainder or rs)
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armAsm->Sxtw(RXSCRATCH, a64::w10);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[0]));
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}
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// Pipeline-1 Rd writeback — identical to recWritebackRd since GE-09 (the
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// rd value rides RXSCRATCH out of recWritebackHILO for either pipeline).
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static void recWritebackRd1()
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{
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recWritebackRd();
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}
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//// MULT1 — signed 32-bit multiply, pipeline 1 (HI1:LO1)
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void recMULT1()
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{
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if (GPR_IS_CONST2(_Rs_, _Rt_))
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{
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s64 result = (s64)(s32)g_cpuConstRegs[_Rs_].UL[0] * (s64)(s32)g_cpuConstRegs[_Rt_].UL[0];
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armAsm->Mov(RXSCRATCH, (s64)(s32)(u32)result);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[1]));
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armAsm->Mov(RXSCRATCH, (s64)(s32)(u32)(result >> 32));
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[1]));
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if (_Rd_)
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{
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_deleteEEreg(_Rd_, 0);
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g_cpuConstRegs[_Rd_].SD[0] = (s32)(u32)result;
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GPR_SET_CONST(_Rd_);
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}
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return;
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}
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_eeFlushAllDirty();
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const a64::Register rs32 = loadRs32();
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const a64::Register rt32 = loadRt32();
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armAsm->Smull(a64::x0, rs32, rt32);
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recWritebackHILO(true);
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recWritebackRd1();
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}
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//// MULTU1 — unsigned 32-bit multiply, pipeline 1
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void recMULTU1()
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{
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if (GPR_IS_CONST2(_Rs_, _Rt_))
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{
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u64 result = (u64)g_cpuConstRegs[_Rs_].UL[0] * (u64)g_cpuConstRegs[_Rt_].UL[0];
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armAsm->Mov(RXSCRATCH, (s64)(s32)(u32)result);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[1]));
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armAsm->Mov(RXSCRATCH, (s64)(s32)(u32)(result >> 32));
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[1]));
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if (_Rd_)
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{
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_deleteEEreg(_Rd_, 0);
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g_cpuConstRegs[_Rd_].SD[0] = (s32)(u32)result;
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GPR_SET_CONST(_Rd_);
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}
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return;
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}
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_eeFlushAllDirty();
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const a64::Register rs32 = loadRs32();
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const a64::Register rt32 = loadRt32();
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armAsm->Umull(a64::x0, rs32, rt32);
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recWritebackHILO(true);
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recWritebackRd1();
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}
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//// DIV1 — signed 32-bit divide, pipeline 1. Same div-by-zero spec as DIV.
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void recDIV1()
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{
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if (GPR_IS_CONST2(_Rs_, _Rt_))
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{
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s32 rs = g_cpuConstRegs[_Rs_].SL[0];
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s32 rt = g_cpuConstRegs[_Rt_].SL[0];
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s32 lo, hi;
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if (rt == 0)
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{
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lo = (rs >= 0) ? -1 : 1;
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hi = rs;
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}
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else if (rs == (s32)0x80000000 && rt == -1)
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{
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lo = (s32)0x80000000;
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hi = 0;
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}
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else
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{
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lo = rs / rt;
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hi = rs % rt;
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}
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armAsm->Mov(RXSCRATCH, (s64)lo);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[1]));
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armAsm->Mov(RXSCRATCH, (s64)hi);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[1]));
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return;
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}
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_eeFlushAllDirty();
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const a64::Register rs32 = loadRs32();
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const a64::Register rt32 = loadRt32();
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a64::Label divByZero;
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a64::Label done;
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armAsm->Cbz(rt32, &divByZero);
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armAsm->Sdiv(a64::w0, rs32, rt32);
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armAsm->Msub(a64::w10, a64::w0, rt32, rs32);
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armAsm->B(&done);
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// Div-by-zero: w0 = (rs >= 0 ? -1 : 1), w10 = rs. See recDIV for Cneg rationale.
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armAsm->Bind(&divByZero);
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armAsm->Mov(a64::w0, -1);
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armAsm->Cmp(rs32, 0);
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armAsm->Cneg(a64::w0, a64::w0, a64::lt);
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armAsm->Mov(a64::w10, rs32); // HI = rs
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armAsm->Bind(&done);
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armAsm->Sxtw(RXSCRATCH, a64::w0);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[1]));
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armAsm->Sxtw(RXSCRATCH, a64::w10);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[1]));
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}
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//// DIVU1 — unsigned 32-bit divide, pipeline 1. Same div-by-zero spec as DIVU.
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void recDIVU1()
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{
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if (GPR_IS_CONST2(_Rs_, _Rt_))
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{
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u32 rs = g_cpuConstRegs[_Rs_].UL[0];
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u32 rt = g_cpuConstRegs[_Rt_].UL[0];
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s32 lo, hi;
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if (rt == 0)
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{
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lo = -1;
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hi = (s32)rs;
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}
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else
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{
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lo = (s32)(rs / rt);
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hi = (s32)(rs % rt);
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}
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armAsm->Mov(RXSCRATCH, (s64)lo);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[1]));
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armAsm->Mov(RXSCRATCH, (s64)hi);
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armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[1]));
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return;
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}
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_eeFlushAllDirty();
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const a64::Register rs32 = loadRs32();
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const a64::Register rt32 = loadRt32();
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a64::Label divByZero;
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a64::Label done;
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armAsm->Cbz(rt32, &divByZero);
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// Remainder into w10, not in place — see recDIVU (WS-C6 pin-safety).
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armAsm->Udiv(a64::w0, rs32, rt32);
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armAsm->Msub(a64::w10, a64::w0, rt32, rs32);
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armAsm->B(&done);
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armAsm->Bind(&divByZero);
|
|
armAsm->Mov(a64::w0, -1);
|
|
armAsm->Mov(a64::w10, rs32);
|
|
|
|
armAsm->Bind(&done);
|
|
|
|
armAsm->Sxtw(RXSCRATCH, a64::w0);
|
|
armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.LO.UD[1]));
|
|
|
|
armAsm->Sxtw(RXSCRATCH, a64::w10);
|
|
armAsm->Str(RXSCRATCH, armCpuRegMem(&cpuRegs.HI.UD[1]));
|
|
}
|
|
|
|
//// MADD — signed multiply-add: HI:LO += Rs * Rt, Rd = LO
|
|
void recMADD()
|
|
{
|
|
if (GPR_IS_CONST2(_Rs_, _Rt_))
|
|
{
|
|
s64 result = (s64)(s32)g_cpuConstRegs[_Rs_].UL[0] * (s64)(s32)g_cpuConstRegs[_Rt_].UL[0];
|
|
|
|
// Add to existing HI:LO — load, add, store
|
|
_eeFlushAllDirty();
|
|
armLoadEERegPtr(a64::w1, &cpuRegs.LO.UL[0]);
|
|
armLoadEERegPtr(a64::w9, &cpuRegs.HI.UL[0]);
|
|
armAsm->Orr(a64::x1, a64::x1, a64::Operand(a64::x9, a64::LSL, 32));
|
|
armAsm->Mov(RXSCRATCH, result);
|
|
armAsm->Add(a64::x0, a64::x1, RXSCRATCH);
|
|
|
|
recWritebackHILO(false);
|
|
recWritebackRd();
|
|
return;
|
|
}
|
|
|
|
_eeFlushAllDirty();
|
|
const a64::Register rs32 = loadRs32();
|
|
const a64::Register rt32 = loadRt32();
|
|
|
|
// x0 = Rs * Rt (signed 32x32→64)
|
|
armAsm->Smull(a64::x0, rs32, rt32);
|
|
|
|
// Load existing HI:LO into x1
|
|
armLoadEERegPtr(a64::w10, &cpuRegs.LO.UL[0]);
|
|
armLoadEERegPtr(RWSCRATCH, &cpuRegs.HI.UL[0]); // w8: reserved scratch (w4 is allocatable)
|
|
armAsm->Orr(a64::x10, a64::x10, a64::Operand(RXSCRATCH, a64::LSL, 32));
|
|
|
|
// Add
|
|
armAsm->Add(a64::x0, a64::x0, a64::x10);
|
|
|
|
recWritebackHILO(false);
|
|
recWritebackRd();
|
|
}
|
|
|
|
//// MADDU — unsigned multiply-add: HI:LO += Rs * Rt, Rd = LO
|
|
void recMADDU()
|
|
{
|
|
if (GPR_IS_CONST2(_Rs_, _Rt_))
|
|
{
|
|
u64 result = (u64)g_cpuConstRegs[_Rs_].UL[0] * (u64)g_cpuConstRegs[_Rt_].UL[0];
|
|
|
|
_eeFlushAllDirty();
|
|
armLoadEERegPtr(a64::w1, &cpuRegs.LO.UL[0]);
|
|
armLoadEERegPtr(a64::w9, &cpuRegs.HI.UL[0]);
|
|
armAsm->Orr(a64::x1, a64::x1, a64::Operand(a64::x9, a64::LSL, 32));
|
|
armAsm->Mov(RXSCRATCH, result);
|
|
armAsm->Add(a64::x0, a64::x1, RXSCRATCH);
|
|
|
|
recWritebackHILO(false);
|
|
recWritebackRd();
|
|
return;
|
|
}
|
|
|
|
_eeFlushAllDirty();
|
|
const a64::Register rs32 = loadRs32();
|
|
const a64::Register rt32 = loadRt32();
|
|
|
|
armAsm->Umull(a64::x0, rs32, rt32);
|
|
|
|
armLoadEERegPtr(a64::w10, &cpuRegs.LO.UL[0]);
|
|
armLoadEERegPtr(RWSCRATCH, &cpuRegs.HI.UL[0]); // w8: reserved scratch (w4 is allocatable)
|
|
armAsm->Orr(a64::x10, a64::x10, a64::Operand(RXSCRATCH, a64::LSL, 32));
|
|
|
|
armAsm->Add(a64::x0, a64::x0, a64::x10);
|
|
|
|
recWritebackHILO(false);
|
|
recWritebackRd();
|
|
}
|
|
|
|
//// MADD1 — signed multiply-add, pipeline 1: HI1:LO1 += Rs * Rt, Rd = LO1
|
|
void recMADD1()
|
|
{
|
|
if (GPR_IS_CONST2(_Rs_, _Rt_))
|
|
{
|
|
s64 result = (s64)(s32)g_cpuConstRegs[_Rs_].UL[0] * (s64)(s32)g_cpuConstRegs[_Rt_].UL[0];
|
|
|
|
_eeFlushAllDirty();
|
|
armLoadEERegPtr(a64::w1, &cpuRegs.LO.UL[2]);
|
|
armLoadEERegPtr(a64::w9, &cpuRegs.HI.UL[2]);
|
|
armAsm->Orr(a64::x1, a64::x1, a64::Operand(a64::x9, a64::LSL, 32));
|
|
armAsm->Mov(RXSCRATCH, result);
|
|
armAsm->Add(a64::x0, a64::x1, RXSCRATCH);
|
|
|
|
recWritebackHILO(true);
|
|
recWritebackRd1();
|
|
return;
|
|
}
|
|
|
|
_eeFlushAllDirty();
|
|
const a64::Register rs32 = loadRs32();
|
|
const a64::Register rt32 = loadRt32();
|
|
|
|
armAsm->Smull(a64::x0, rs32, rt32);
|
|
|
|
armLoadEERegPtr(a64::w10, &cpuRegs.LO.UL[2]); // LO1 = LO.UL[2] (upper 64 bits)
|
|
armLoadEERegPtr(RWSCRATCH, &cpuRegs.HI.UL[2]); // HI1 = HI.UL[2] (w8: reserved scratch — w4 is allocatable)
|
|
armAsm->Orr(a64::x10, a64::x10, a64::Operand(RXSCRATCH, a64::LSL, 32));
|
|
|
|
armAsm->Add(a64::x0, a64::x0, a64::x10);
|
|
|
|
recWritebackHILO(true);
|
|
recWritebackRd1();
|
|
}
|
|
|
|
//// MADDU1 — unsigned multiply-add, pipeline 1
|
|
void recMADDU1()
|
|
{
|
|
if (GPR_IS_CONST2(_Rs_, _Rt_))
|
|
{
|
|
u64 result = (u64)g_cpuConstRegs[_Rs_].UL[0] * (u64)g_cpuConstRegs[_Rt_].UL[0];
|
|
|
|
_eeFlushAllDirty();
|
|
armLoadEERegPtr(a64::w1, &cpuRegs.LO.UL[2]);
|
|
armLoadEERegPtr(a64::w9, &cpuRegs.HI.UL[2]);
|
|
armAsm->Orr(a64::x1, a64::x1, a64::Operand(a64::x9, a64::LSL, 32));
|
|
armAsm->Mov(RXSCRATCH, result);
|
|
armAsm->Add(a64::x0, a64::x1, RXSCRATCH);
|
|
|
|
recWritebackHILO(true);
|
|
recWritebackRd1();
|
|
return;
|
|
}
|
|
|
|
_eeFlushAllDirty();
|
|
const a64::Register rs32 = loadRs32();
|
|
const a64::Register rt32 = loadRt32();
|
|
|
|
armAsm->Umull(a64::x0, rs32, rt32);
|
|
|
|
armLoadEERegPtr(a64::w10, &cpuRegs.LO.UL[2]);
|
|
armLoadEERegPtr(RWSCRATCH, &cpuRegs.HI.UL[2]); // w8: reserved scratch (w4 is allocatable)
|
|
armAsm->Orr(a64::x10, a64::x10, a64::Operand(RXSCRATCH, a64::LSL, 32));
|
|
|
|
armAsm->Add(a64::x0, a64::x0, a64::x10);
|
|
|
|
recWritebackHILO(true);
|
|
recWritebackRd1();
|
|
}
|
|
|
|
} // namespace OpcodeImpl
|
|
} // namespace Dynarec
|
|
} // namespace R5900
|