mirror of
https://github.com/ARMSX2/ARMSX2.git
synced 2026-08-24 16:50:16 -07:00
Brian Degenhardt
06445dd641
Once a hunt reaches `cop2vu` it stops: that group is one dispatch bit covering the whole VU macro-mode instruction set, and there was no next axis. Finding which of them miscompiles meant hand-editing the classifier and rebuilding per hypothesis. Two additions close that gap. `--rec-fallback cop2vu:<mnemonic>` selects individual macro ops by name, over a flat 256-entry id space covering all three dispatch tables (BC2 by rt, SPECIAL1 by funct, SPECIAL2 by its packed index). And a compile-time census, printed after --mkstate, lists the macro ops the run actually emitted — an op that never compiles cannot be the bug, so it turns a 100-way search into a bisect over the handful a given game really uses. On NASCAR Thunder 2002 the census reported 58 distinct ops and the bisect reached one of them in eleven runs, no rebuilds.
554 lines
22 KiB
C++
554 lines
22 KiB
C++
// SPDX-FileCopyrightText: 2026 yaps2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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#include "arm64/iR5900-arm64.h"
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#include "common/Assertions.h"
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#include "common/Console.h"
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namespace a64 = vixl::aarch64;
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namespace R5900 {
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namespace Dynarec {
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// Forward declarations for native COP2 codegen (defined in iCOP2-arm64.cpp)
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namespace OpcodeImpl {
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// Transfer ops
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void recCOP2_QMFC2();
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void recCOP2_QMTC2();
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void recCOP2_CFC2();
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// SIMPLE
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void recCOP2_VMOVE();
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void recCOP2_VMR32();
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void recCOP2_VNOP();
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void recCOP2_VWAITQ();
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void recCOP2_VABS();
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// VEC_ARITH
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void recCOP2_VADD();
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void recCOP2_VSUB();
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void recCOP2_VMUL();
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void recCOP2_VMAX();
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void recCOP2_VMINI();
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// BC variants
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void recCOP2_VADDx(); void recCOP2_VADDy(); void recCOP2_VADDz(); void recCOP2_VADDw();
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void recCOP2_VSUBx(); void recCOP2_VSUBy(); void recCOP2_VSUBz(); void recCOP2_VSUBw();
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void recCOP2_VMULx(); void recCOP2_VMULy(); void recCOP2_VMULz(); void recCOP2_VMULw();
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void recCOP2_VMAXx(); void recCOP2_VMAXy(); void recCOP2_VMAXz(); void recCOP2_VMAXw();
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void recCOP2_VMINIx(); void recCOP2_VMINIy(); void recCOP2_VMINIz(); void recCOP2_VMINIw();
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void recCOP2_VMAXi(); void recCOP2_VMINIi();
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// Q/I variants
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void recCOP2_VADDq(); void recCOP2_VSUBq(); void recCOP2_VMULq();
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void recCOP2_VADDi(); void recCOP2_VSUBi(); void recCOP2_VMULi();
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// MADD/MSUB
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void recCOP2_VMADD(); void recCOP2_VMSUB();
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void recCOP2_VMADDx(); void recCOP2_VMADDy(); void recCOP2_VMADDz(); void recCOP2_VMADDw();
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void recCOP2_VMSUBx(); void recCOP2_VMSUBy(); void recCOP2_VMSUBz(); void recCOP2_VMSUBw();
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void recCOP2_VMADDq(); void recCOP2_VMSUBq();
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void recCOP2_VMADDi(); void recCOP2_VMSUBi();
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void recCOP2_VOPMSUB();
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// Accumulator
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void recCOP2_VADDA(); void recCOP2_VSUBA(); void recCOP2_VMULA();
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void recCOP2_VADDAx(); void recCOP2_VADDAy(); void recCOP2_VADDAz(); void recCOP2_VADDAw();
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void recCOP2_VSUBAx(); void recCOP2_VSUBAy(); void recCOP2_VSUBAz(); void recCOP2_VSUBAw();
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void recCOP2_VMULAx(); void recCOP2_VMULAy(); void recCOP2_VMULAz(); void recCOP2_VMULAw();
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void recCOP2_VMULAq(); void recCOP2_VMULAi();
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void recCOP2_VADDAq(); void recCOP2_VSUBAq();
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void recCOP2_VADDAi(); void recCOP2_VSUBAi();
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void recCOP2_VMADDA(); void recCOP2_VMSUBA();
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void recCOP2_VMADDAx(); void recCOP2_VMADDAy(); void recCOP2_VMADDAz(); void recCOP2_VMADDAw();
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void recCOP2_VMSUBAx(); void recCOP2_VMSUBAy(); void recCOP2_VMSUBAz(); void recCOP2_VMSUBAw();
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void recCOP2_VMADDAq(); void recCOP2_VMSUBAq();
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void recCOP2_VMADDAi(); void recCOP2_VMSUBAi();
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void recCOP2_VOPMULA();
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// Conversion
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void recCOP2_VITOF0(); void recCOP2_VITOF4(); void recCOP2_VITOF12(); void recCOP2_VITOF15();
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void recCOP2_VFTOI0(); void recCOP2_VFTOI4(); void recCOP2_VFTOI12(); void recCOP2_VFTOI15();
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// Integer ops
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void recCOP2_VIADD(); void recCOP2_VISUB(); void recCOP2_VIADDI();
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void recCOP2_VIAND(); void recCOP2_VIOR();
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// CTC2
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void recCOP2_CTC2();
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// Division ops
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void recCOP2_VDIV();
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void recCOP2_VSQRT();
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void recCOP2_VRSQRT();
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// Clip
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void recCOP2_VCLIP();
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} // namespace OpcodeImpl
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// Branch helper — not implemented on ARM64. Callers (iCOP0/iFPU/COP2 macro
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// paths) drive SaveBranchState/SetBranchImm directly instead. Fail loudly
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// rather than silently no-op if a future port wires this in by mistake.
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void recDoBranchImm(u32 branchTo, u32* jmpSkip, bool isLikely, bool swappedDelaySlot)
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{
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pxFailRel("recDoBranchImm is not implemented on ARM64");
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}
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namespace OpcodeImpl {
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namespace Interp = R5900::Interpreter::OpcodeImpl;
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void recPREF() {}
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// SYSCALL and BREAK — flush state and call interpreter
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void recSYSCALL()
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{
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if (GPR_IS_CONST1(3))
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{
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// FlushCache (0x64) / iFlushCache (0x68): the EE cache is not modelled,
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// so account for the kernel handler cycles inline and skip the call.
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// Cycle count from github.com/F0bes/flushcache-cycles. Mirrors x86 recSYSCALL.
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//
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// This skip leaves v0/v1/at/t0/t1 and EPC at their pre-syscall values,
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// whereas the interpreter actually raises cpuException(0x20) and runs the
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// BIOS 0x80000180 trampoline, which clobbers them. That JIT-vs-interp
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// divergence is REAL but ABI-benign: FlushCache is a syscall, so under
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// the MIPS calling convention those are all caller-saved/temporary regs
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// (plus EPC, which user code never reads) — correct code never depends on
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// them surviving. Upstream PCSX2-x86 ships this skip as a correct, faster
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// optimization.
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const u8 syscallNum = g_cpuConstRegs[3].UC[0];
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if (syscallNum == 0x64 || syscallNum == 0x68)
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{
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s_nBlockCycles += 5650;
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return;
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}
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}
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recBranchCall(Interp::SYSCALL);
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}
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void recBREAK()
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{
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recBranchCall(Interp::BREAK);
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}
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// =====================================================================================================
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// COP2 (VU0 macro mode) — dispatch table with per-sub-opcode interpreter fallback
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// Mirrors the x86 dispatch structure: recCOP2 → recCOP2t[_Rs_] → SPEC1/SPEC2
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// =====================================================================================================
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// COP2 macro-mode mVU-reuse wrapper. Drives the existing microVU emitter
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// (mVU_<op> in microVU_Lower-arm64.inl) via the mVUmacroEmit_<op> adapter
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// declared in iR5900-arm64.h. Mirrors x86 REC_COP2_mVU0 (microVU_Macro.inl:122).
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// Mode bits per x86 microVU_Macro.inl:158-165:
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// 0x01 reads Q reg / 0x02 writes Q reg / 0x04 requires analysis pass
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// 0x08 writes CLIP / 0x10 writes status/mac / 0x100 requires x86 regs.
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#define REC_COP2_mVU0_ARM64(name, mode) \
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static void recV##name() \
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{ \
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setupMacroOp_arm64(mode); \
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mVUmacroEmit_##name(mode); \
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endMacroOp_arm64(mode); \
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}
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// Transfer ops — native codegen for QMFC2/QMTC2/CFC2, CTC2 stays interpreter
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static void recVQMFC2() { recCOP2_QMFC2(); }
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static void recVQMTC2() { recCOP2_QMTC2(); }
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static void recVCFC2() { recCOP2_CFC2(); }
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static void recVCTC2() { recCOP2_CTC2(); }
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// Branch ops — native COP2 condition branch. CP2COND = bit 8 of
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// VU0.VI[REG_VPU_STAT] (COP2.cpp:11). Mirrors x86 _setupBranchTest
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// (microVU_Macro.inl) and the recBC1F FPU-branch shape: a lightweight
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// _eeFlushAllDirty + a single Tbz/Tbnz on the flag bit, then the standard EE
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// branch-imm machinery — avoiding FLUSH_INTERPRETER + C-call + dispatcher
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// round-trip overhead.
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static a64::Label* s_pBC2Label = nullptr;
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static void recSetBranchCOP2(bool branchOnTrue)
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{
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_eeFlushAllDirty();
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armAsm->Ldr(RWSCRATCH, armVU0Mem(&VU0.VI[REG_VPU_STAT]));
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// The forward branch skips the taken path: BC2T (branchOnTrue) is taken when
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// CP2COND is set → skip when clear → Tbz; BC2F is taken when clear → skip
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// when set → Tbnz. Matches x86 JZ32/JNZ32 in recBC2T/recBC2F.
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s_pBC2Label = new a64::Label();
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if (branchOnTrue)
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armAsm->Tbz(RWSCRATCH, 8, s_pBC2Label);
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else
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armAsm->Tbnz(RWSCRATCH, 8, s_pBC2Label);
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}
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static void recBindBC2Label()
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{
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armAsm->Bind(s_pBC2Label);
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delete s_pBC2Label;
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s_pBC2Label = nullptr;
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}
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// Non-likely (BC2F/BC2T): attempt a delay-slot swap (allow_loadstore=false,
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// matching x86 _setupBranchTest's TrySwapDelaySlot(0,0,0,false)).
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static void recVBC2F()
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{
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u32 branchTo = ((s32)_Imm_ * 4) + pc;
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const bool swap = TrySwapDelaySlot(0, 0, 0, false);
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recSetBranchCOP2(false);
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if (!swap)
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{
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SaveBranchState();
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recompileNextInstruction(true, false);
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}
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SetBranchImm(branchTo);
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recBindBC2Label();
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if (!swap)
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{
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pc -= 4;
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LoadBranchState();
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recompileNextInstruction(true, false);
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}
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SetBranchImm(pc);
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}
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static void recVBC2T()
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{
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u32 branchTo = ((s32)_Imm_ * 4) + pc;
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const bool swap = TrySwapDelaySlot(0, 0, 0, false);
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recSetBranchCOP2(true);
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if (!swap)
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{
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SaveBranchState();
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recompileNextInstruction(true, false);
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}
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SetBranchImm(branchTo);
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recBindBC2Label();
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if (!swap)
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{
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pc -= 4;
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LoadBranchState();
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recompileNextInstruction(true, false);
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}
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SetBranchImm(pc);
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}
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// Likely (BC2FL/BC2TL): delay slot squashed when not taken; no swap, matching
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// the x86 isLikely path (and the interp's `else { cpuRegs.pc += 4; }`).
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static void recVBC2FL()
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{
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u32 branchTo = ((s32)_Imm_ * 4) + pc;
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recSetBranchCOP2(false);
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SaveBranchState();
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recompileNextInstruction(true, false);
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SetBranchImm(branchTo);
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recBindBC2Label();
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LoadBranchState();
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SetBranchImm(pc);
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}
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static void recVBC2TL()
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{
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u32 branchTo = ((s32)_Imm_ * 4) + pc;
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recSetBranchCOP2(true);
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SaveBranchState();
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recompileNextInstruction(true, false);
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SetBranchImm(branchTo);
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recBindBC2Label();
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LoadBranchState();
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SetBranchImm(pc);
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}
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// Upper instructions (SPEC1) — native NEON codegen
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// BC variants: VF[fd] = VF[fs] OP VF[ft].bc
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static void recVADDx() { recCOP2_VADDx(); } static void recVADDy() { recCOP2_VADDy(); }
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static void recVADDz() { recCOP2_VADDz(); } static void recVADDw() { recCOP2_VADDw(); }
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static void recVSUBx() { recCOP2_VSUBx(); } static void recVSUBy() { recCOP2_VSUBy(); }
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static void recVSUBz() { recCOP2_VSUBz(); } static void recVSUBw() { recCOP2_VSUBw(); }
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static void recVMADDx() { recCOP2_VMADDx(); } static void recVMADDy() { recCOP2_VMADDy(); }
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static void recVMADDz() { recCOP2_VMADDz(); } static void recVMADDw() { recCOP2_VMADDw(); }
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static void recVMSUBx() { recCOP2_VMSUBx(); } static void recVMSUBy() { recCOP2_VMSUBy(); }
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static void recVMSUBz() { recCOP2_VMSUBz(); } static void recVMSUBw() { recCOP2_VMSUBw(); }
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static void recVMAXx() { recCOP2_VMAXx(); } static void recVMAXy() { recCOP2_VMAXy(); }
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static void recVMAXz() { recCOP2_VMAXz(); } static void recVMAXw() { recCOP2_VMAXw(); }
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static void recVMINIx() { recCOP2_VMINIx(); } static void recVMINIy() { recCOP2_VMINIy(); }
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static void recVMINIz() { recCOP2_VMINIz(); } static void recVMINIw() { recCOP2_VMINIw(); }
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static void recVMULx() { recCOP2_VMULx(); } static void recVMULy() { recCOP2_VMULy(); }
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static void recVMULz() { recCOP2_VMULz(); } static void recVMULw() { recCOP2_VMULw(); }
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static void recVMULq() { recCOP2_VMULq(); } static void recVMAXi() { recCOP2_VMAXi(); }
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static void recVMULi() { recCOP2_VMULi(); } static void recVMINIi() { recCOP2_VMINIi(); }
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static void recVADDq() { recCOP2_VADDq(); } static void recVMADDq() { recCOP2_VMADDq(); }
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static void recVADDi() { recCOP2_VADDi(); } static void recVMADDi() { recCOP2_VMADDi(); }
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static void recVSUBq() { recCOP2_VSUBq(); } static void recVMSUBq() { recCOP2_VMSUBq(); }
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static void recVSUBi() { recCOP2_VSUBi(); } static void recVMSUBi() { recCOP2_VMSUBi(); }
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static void recVADD() { recCOP2_VADD(); } static void recVMADD() { recCOP2_VMADD(); }
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static void recVMUL() { recCOP2_VMUL(); } static void recVMAX() { recCOP2_VMAX(); }
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static void recVSUB() { recCOP2_VSUB(); } static void recVMSUB() { recCOP2_VMSUB(); }
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static void recVOPMSUB(){ recCOP2_VOPMSUB(); } static void recVMINI() { recCOP2_VMINI(); }
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// Integer ops — native
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static void recVIADD() { recCOP2_VIADD(); } static void recVISUB() { recCOP2_VISUB(); }
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static void recVIADDI() { recCOP2_VIADDI(); }
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static void recVIAND() { recCOP2_VIAND(); } static void recVIOR() { recCOP2_VIOR(); }
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// CALLMS/CALLMSR kick off a VU0 microprogram via the interpreter — they are
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// NOT EE branches (x86 iR5900Analysis case 56/57 just `break;`) so they
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// must NOT exit the recompiled block the way recBranchCall does. Mirror
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// x86's INTERPRETATE_COP2_FUNC(CALLMS) (microVU_Macro.inl:142): full
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// FLUSH_INTERPRETER flush (so cpuRegs.code is current — VCALLMS reads
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// the start PC from `(cpuRegs.code >> 6) & 0x7FFF`), apply pending block
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// cycles, call the interpreter (which itself runs _vu0FinishMicro +
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// vu0ExecMicro), then reload RECCYCLE in case the interp advanced
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// cpuRegs.cycle. Block execution continues at the next opcode.
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// Using iFlushCall(FLUSH_INTERPRETER) inline avoids the g_branch=2 block
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// exit that recBranchCall would trigger on every CALLMS; the flush cost
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// is the same, with no dispatcher round-trip.
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static void recVCallmsImpl(void (*func)())
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{
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iFlushCall(FLUSH_INTERPRETER);
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u32 cycles = scaleblockcycles_clear();
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if (cycles != 0)
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armAsm->Add(RECCYCLE, RECCYCLE, cycles);
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armFlushCycleDelta();
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armFlushEEClobberedPins(); // lazy-dirty seam: pairs with the reload below
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armEmitCall((void*)func);
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armReloadCycleDelta();
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// VCALLMS/VCALLMSR run VU0 micro (writes VU state, not EE GPRs); restore
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// the caller-saved pins the C call clobbered — the block continues.
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armReloadEEClobberedPins();
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}
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static void recVCALLMS() { recVCallmsImpl(VCALLMS); }
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static void recVCALLMSR() { recVCallmsImpl(VCALLMSR); }
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// Lower instructions (SPEC2) — native NEON codegen for accumulator/conversion/simple ops
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// Accumulator BC variants
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static void recVADDAx() { recCOP2_VADDAx(); } static void recVADDAy() { recCOP2_VADDAy(); }
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static void recVADDAz() { recCOP2_VADDAz(); } static void recVADDAw() { recCOP2_VADDAw(); }
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static void recVSUBAx() { recCOP2_VSUBAx(); } static void recVSUBAy() { recCOP2_VSUBAy(); }
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static void recVSUBAz() { recCOP2_VSUBAz(); } static void recVSUBAw() { recCOP2_VSUBAw(); }
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static void recVMADDAx(){ recCOP2_VMADDAx(); } static void recVMADDAy(){ recCOP2_VMADDAy(); }
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static void recVMADDAz(){ recCOP2_VMADDAz(); } static void recVMADDAw(){ recCOP2_VMADDAw(); }
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static void recVMSUBAx(){ recCOP2_VMSUBAx(); } static void recVMSUBAy(){ recCOP2_VMSUBAy(); }
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static void recVMSUBAz(){ recCOP2_VMSUBAz(); } static void recVMSUBAw(){ recCOP2_VMSUBAw(); }
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// Conversions — native NEON
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static void recVITOF0() { recCOP2_VITOF0(); } static void recVITOF4() { recCOP2_VITOF4(); }
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static void recVITOF12() { recCOP2_VITOF12(); } static void recVITOF15() { recCOP2_VITOF15(); }
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static void recVFTOI0() { recCOP2_VFTOI0(); } static void recVFTOI4() { recCOP2_VFTOI4(); }
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static void recVFTOI12() { recCOP2_VFTOI12(); } static void recVFTOI15() { recCOP2_VFTOI15(); }
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// Accumulator MULAx/y/z/w
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static void recVMULAx() { recCOP2_VMULAx(); } static void recVMULAy() { recCOP2_VMULAy(); }
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static void recVMULAz() { recCOP2_VMULAz(); } static void recVMULAw() { recCOP2_VMULAw(); }
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static void recVMULAq() { recCOP2_VMULAq(); } static void recVABS() { recCOP2_VABS(); }
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static void recVMULAi() { recCOP2_VMULAi(); }
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// CLIP: native (recCOP2_VCLIP, iCOP2-arm64.cpp) - NEON vectorized 6-plane clip test
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static void recVCLIP() { recCOP2_VCLIP(); }
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// Accumulator Q/I variants
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static void recVADDAq() { recCOP2_VADDAq(); } static void recVMADDAq(){ recCOP2_VMADDAq(); }
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static void recVADDAi() { recCOP2_VADDAi(); } static void recVMADDAi(){ recCOP2_VMADDAi(); }
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static void recVSUBAq() { recCOP2_VSUBAq(); } static void recVMSUBAq(){ recCOP2_VMSUBAq(); }
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static void recVSUBAi() { recCOP2_VSUBAi(); } static void recVMSUBAi(){ recCOP2_VMSUBAi(); }
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// Accumulator full-vector variants
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static void recVADDA() { recCOP2_VADDA(); } static void recVMADDA() { recCOP2_VMADDA(); }
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static void recVMULA() { recCOP2_VMULA(); }
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static void recVSUBA() { recCOP2_VSUBA(); } static void recVMSUBA() { recCOP2_VMSUBA(); }
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static void recVOPMULA(){ recCOP2_VOPMULA(); } static void recVNOP() { recCOP2_VNOP(); }
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// Simple data movement — native
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static void recVMOVE() { recCOP2_VMOVE(); } static void recVMR32() { recCOP2_VMR32(); }
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// Load/store — full group native via mVU emit (mode bits from x86 microVU_Macro.inl:276-279).
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REC_COP2_mVU0_ARM64(LQI, 0x104); REC_COP2_mVU0_ARM64(SQI, 0x100);
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REC_COP2_mVU0_ARM64(LQD, 0x104); REC_COP2_mVU0_ARM64(SQD, 0x100);
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// Division ops — native
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static void recVDIV() { recCOP2_VDIV(); }
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static void recVSQRT() { recCOP2_VSQRT(); }
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static void recVRSQRT(){ recCOP2_VRSQRT(); }
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static void recVWAITQ() { recCOP2_VWAITQ(); }
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REC_COP2_mVU0_ARM64(MTIR, 0x104); REC_COP2_mVU0_ARM64(MFIR, 0x104);
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REC_COP2_mVU0_ARM64(ILWR, 0x104); REC_COP2_mVU0_ARM64(ISWR, 0x100);
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REC_COP2_mVU0_ARM64(RNEXT, 0x104); REC_COP2_mVU0_ARM64(RGET, 0x104);
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REC_COP2_mVU0_ARM64(RINIT, 0x100); REC_COP2_mVU0_ARM64(RXOR, 0x100);
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static void rec_C2UNK() { Console.Error("EE: Unrecognized COP2 opcode %08X", cpuRegs.code); }
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// Dispatch tables — mirror x86 structure
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static void recCOP2_BC2();
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static void recCOP2_SPEC1();
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static void recCOP2_SPEC2();
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static void (*recCOP2t[32])() = {
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rec_C2UNK, recVQMFC2, recVCFC2, rec_C2UNK, rec_C2UNK, recVQMTC2, recVCTC2, rec_C2UNK,
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recCOP2_BC2, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
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recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1,
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recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1,
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};
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static void (*recCOP2_BC2t[32])() = {
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recVBC2F, recVBC2T, recVBC2FL, recVBC2TL, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
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rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
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rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
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rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
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};
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static void (*recCOP2SPECIAL1t[64])() = {
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recVADDx, recVADDy, recVADDz, recVADDw, recVSUBx, recVSUBy, recVSUBz, recVSUBw,
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recVMADDx, recVMADDy, recVMADDz, recVMADDw, recVMSUBx, recVMSUBy, recVMSUBz, recVMSUBw,
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recVMAXx, recVMAXy, recVMAXz, recVMAXw, recVMINIx, recVMINIy, recVMINIz, recVMINIw,
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recVMULx, recVMULy, recVMULz, recVMULw, recVMULq, recVMAXi, recVMULi, recVMINIi,
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recVADDq, recVMADDq, recVADDi, recVMADDi, recVSUBq, recVMSUBq, recVSUBi, recVMSUBi,
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recVADD, recVMADD, recVMUL, recVMAX, recVSUB, recVMSUB, recVOPMSUB, recVMINI,
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recVIADD, recVISUB, recVIADDI, rec_C2UNK, recVIAND, recVIOR, rec_C2UNK, rec_C2UNK,
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recVCALLMS, recVCALLMSR,rec_C2UNK, rec_C2UNK, recCOP2_SPEC2, recCOP2_SPEC2, recCOP2_SPEC2, recCOP2_SPEC2,
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};
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static void (*recCOP2SPECIAL2t[128])() = {
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recVADDAx, recVADDAy, recVADDAz, recVADDAw, recVSUBAx, recVSUBAy, recVSUBAz, recVSUBAw,
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recVMADDAx,recVMADDAy, recVMADDAz, recVMADDAw, recVMSUBAx, recVMSUBAy, recVMSUBAz, recVMSUBAw,
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recVITOF0, recVITOF4, recVITOF12, recVITOF15, recVFTOI0, recVFTOI4, recVFTOI12, recVFTOI15,
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recVMULAx, recVMULAy, recVMULAz, recVMULAw, recVMULAq, recVABS, recVMULAi, recVCLIP,
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recVADDAq, recVMADDAq,recVADDAi, recVMADDAi, recVSUBAq, recVMSUBAq, recVSUBAi, recVMSUBAi,
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recVADDA, recVMADDA, recVMULA, rec_C2UNK, recVSUBA, recVMSUBA, recVOPMULA, recVNOP,
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recVMOVE, recVMR32, rec_C2UNK, rec_C2UNK, recVLQI, recVSQI, recVLQD, recVSQD,
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|
recVDIV, recVSQRT, recVRSQRT, recVWAITQ, recVMTIR, recVMFIR, recVILWR, recVISWR,
|
|
recVRNEXT, recVRGET, recVRINIT, recVRXOR, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
|
rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
|
rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
|
rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
|
rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
|
rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
|
rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
|
rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
|
};
|
|
|
|
static void recCOP2_BC2() { recCOP2_BC2t[_Rt_](); }
|
|
static void recCOP2_SPEC1() { recCOP2SPECIAL1t[cpuRegs.code & 0x3f](); }
|
|
static void recCOP2_SPEC2() { recCOP2SPECIAL2t[(cpuRegs.code & 0x3) | ((cpuRegs.code >> 4) & 0x7c)](); }
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|
|
|
void recCOP2()
|
|
{
|
|
#ifdef PCSX2_RECOMPILER_TESTS
|
|
EERecFallback::NoteCop2VuCompiled(cpuRegs.code);
|
|
#endif
|
|
recCOP2t[_Rs_]();
|
|
}
|
|
|
|
void recSYNC() {}
|
|
|
|
// MFSA — rd = sa (shift amount register)
|
|
void recMFSA()
|
|
{
|
|
if (!_Rd_) return;
|
|
_deleteEEreg(_Rd_, 0);
|
|
const a64::Register dst = _eeGetGPRDestReg(_Rd_, RXSCRATCH, /*alloc_if_used=*/true);
|
|
// Ldr of the 32-bit sa zero-extends into the 64-bit dest (GE-04).
|
|
armLoadEERegPtr(dst.W(), &cpuRegs.sa);
|
|
_eeStoreGPRDestReg(_Rd_, dst);
|
|
}
|
|
|
|
// MTSA — sa = rs[3:0]. SA is four bits wide on hardware (console capture:
|
|
// `mtsa 0x10` -> 0, `mtsa 0xFFFFFFFF` -> 0xF), and MFSA reads the masked
|
|
// value back, so the mask belongs at the write rather than at QFSRV's
|
|
// consumption.
|
|
void recMTSA()
|
|
{
|
|
if (GPR_IS_CONST1(_Rs_))
|
|
{
|
|
armAsm->Mov(RWSCRATCH, g_cpuConstRegs[_Rs_].UL[0] & 0xF);
|
|
armAsm->Str(RWSCRATCH, armCpuRegMem(&cpuRegs.sa));
|
|
}
|
|
else
|
|
{
|
|
_deleteEEreg(_Rs_, 1);
|
|
const a64::Register rs = _eeGetGPRSourceReg(RWSCRATCH, _Rs_);
|
|
armAsm->And(RWSCRATCH, rs, 0xF); // read rs, write scratch (rs may be a pin)
|
|
armAsm->Str(RWSCRATCH, armCpuRegMem(&cpuRegs.sa));
|
|
}
|
|
}
|
|
|
|
// MTSAB — sa = (rs[3:0] ^ imm[3:0])
|
|
void recMTSAB()
|
|
{
|
|
if (GPR_IS_CONST1(_Rs_))
|
|
{
|
|
u32 val = (g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF);
|
|
armAsm->Mov(RWSCRATCH, val);
|
|
armAsm->Str(RWSCRATCH, armCpuRegMem(&cpuRegs.sa));
|
|
}
|
|
else
|
|
{
|
|
_deleteEEreg(_Rs_, 1);
|
|
const a64::Register rs = _eeGetGPRSourceReg(RWSCRATCH, _Rs_);
|
|
armAsm->And(RWSCRATCH, rs, 0xF); // read rs, write scratch (rs may be a pin)
|
|
armAsm->Eor(RWSCRATCH, RWSCRATCH, _Imm_ & 0xF);
|
|
armAsm->Str(RWSCRATCH, armCpuRegMem(&cpuRegs.sa));
|
|
}
|
|
}
|
|
|
|
// MTSAH — sa = ((rs[2:0] ^ imm[2:0]) << 1)
|
|
void recMTSAH()
|
|
{
|
|
if (GPR_IS_CONST1(_Rs_))
|
|
{
|
|
u32 val = ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1;
|
|
armAsm->Mov(RWSCRATCH, val);
|
|
armAsm->Str(RWSCRATCH, armCpuRegMem(&cpuRegs.sa));
|
|
}
|
|
else
|
|
{
|
|
_deleteEEreg(_Rs_, 1);
|
|
const a64::Register rs = _eeGetGPRSourceReg(RWSCRATCH, _Rs_);
|
|
armAsm->Eor(RWSCRATCH, rs, _Imm_ & 0x7); // read rs, write scratch (rs may be a pin)
|
|
// ubfiz w, w, #1, #3 extracts bits[2:0] and places them at bit 1
|
|
armAsm->Ubfiz(RWSCRATCH, RWSCRATCH, 1, 3);
|
|
armAsm->Str(RWSCRATCH, armCpuRegMem(&cpuRegs.sa));
|
|
}
|
|
}
|
|
|
|
void recNULL()
|
|
{
|
|
Console.Error("EE: Unimplemented op %x", cpuRegs.code);
|
|
}
|
|
|
|
void recUnknown()
|
|
{
|
|
Console.Error("EE: Unrecognized op %x", cpuRegs.code);
|
|
}
|
|
|
|
void recMMI_Unknown()
|
|
{
|
|
Console.Error("EE: Unrecognized MMI op %x", cpuRegs.code);
|
|
}
|
|
|
|
void recCOP0_Unknown()
|
|
{
|
|
Console.Error("EE: Unrecognized COP0 op %x", cpuRegs.code);
|
|
}
|
|
|
|
void recCOP1_Unknown()
|
|
{
|
|
Console.Error("EE: Unrecognized FPU/COP1 op %x", cpuRegs.code);
|
|
}
|
|
|
|
void recCACHE() {}
|
|
|
|
REC_SYS(TGE);
|
|
REC_SYS(TGEU);
|
|
REC_SYS(TLT);
|
|
REC_SYS(TLTU);
|
|
REC_SYS(TEQ);
|
|
REC_SYS(TNE);
|
|
REC_SYS(TGEI);
|
|
REC_SYS(TGEIU);
|
|
REC_SYS(TLTI);
|
|
REC_SYS(TLTIU);
|
|
REC_SYS(TEQI);
|
|
REC_SYS(TNEI);
|
|
|
|
} // namespace OpcodeImpl
|
|
} // namespace Dynarec
|
|
} // namespace R5900
|
|
|
|
// recBackpropBSC is provided by the shared x86/iR5900Analysis.cpp
|
|
// (compiled for ARM64 via ARCH_ARM64 conditional include).
|
|
|