mirror of
https://github.com/ARMSX2/ARMSX2.git
synced 2026-08-24 16:50:16 -07:00
Brian Degenhardt
3e077eff9b
Merges yaps2/main (github.com/yaps2/yaps2,c16b88cb7) into ARMSX2, replacing the arm64 recompiler family with the yaps2 JITs and importing the yaps2 testing, perf, and libretro infrastructure. Common ancestor is upstream PCSX2342db5152(2026-06-19); git auto-merged all but 38 files. Replaced (deleted in this merge, recoverable from history): - arm64/aR5900*, aR3000A*, aVU* -> arm64/iR5900*/iR3000A*/microVU*-arm64: EE static-pin register file with lazy dirty tracking, dual-residence allocator, IOP block linking, native COP2 macro ops, inline unaligned fastmem, persisted VU program cache, call-ret shadow ring, VU0 spin fast-forward. - MVU_DIFF shadow-run hooks in shared VU interpreter TUs (superseded by the offline vurunner JIT-vs-interp oracle). Imported from yaps2: - tests/ctest/core/recompilers: ~80 gtest suites (EE/IOP/VU differential harnesses, fuzzers, ABI digest tripwire, capture format pins) plus the gs_vertex_tests kernel oracle. - pcsx2-vurunner / pcsx2-eerunner headless capture-replay runners. - tools/perf counter-based A/B rigs, perf jitdump productionization, PmuCounters, clang-perf/clang-handheld presets. - pcsx2-libretro core (ENABLE_LIBRETRO, default OFF; rename pending). - GS vertex-kick fast path (GV series): TBL-based packed parse, register-resident kick, scalar-outcode cull, fused draw-rect/FindMinMax. - Null renderer, VK_KHR_display direct WSI, swapchain PresentStats. - SPU2 NEON mixer vectorization, EE timer read clamp (NFL 2K5 hang), IOP ioman signed-compare fix, assorted UB fixes. Kept from ARMSX2 in the both-touched files: - iOS dual-map W^X and fastmem-unavailable resilience (Memory, HostSys, vtlb). The split data/code area model is retained; both areas now take fixed VA hints so cached VU JIT code stays deterministic on Linux. - Android thread-affinity model, VMState shutdown early-outs, all platform frontends, branding, CI, RetroAchievements identity/policy. - GSDeviceVK: ARMSX2's push-descriptor decision logic (Mali crash gate, proprietary-vs-turnip Adreno split) merged with yaps2's descriptor-pool exhaustion recovery (flush + render-pass restart instead of dropped binds). Vendor feature policy is the union: Mali fbfetch policy with MediaTek/G57/Xclipse gates from ARMSX2; Adreno stencil/ROV/ test-and-sample-depth hang avoidance and no_ps2_z_quantization from yaps2. Build-system notes: - The Qt debugger is now gated behind ENABLE_QT_DEBUGGER (default off on arm64) so handheld builds drop the KDDockWidgets dependency. - GSDeviceNone and remaining yaps2 GS code were ported to the newer upstream GSTexture Usage-flags API. The replaced backend's interpreter-fallback glue (intExecuteOneInst, AndroidEEOpHist) and the EEDiffVerify runtime differ are retained for now; dead pieces will be removed in a follow-up commit.
433 lines
9.7 KiB
C++
433 lines
9.7 KiB
C++
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
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// SPDX-FileCopyrightText: 2026 isztld <https://isztld.com/>
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// SPDX-License-Identifier: GPL-3.0
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#include "Vif_UnpackNEON.h"
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#include "common/Perf.h"
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namespace a64 = vixl::aarch64;
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// =====================================================================================================
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// VifUnpackSSE_Base Section
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// =====================================================================================================
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VifUnpackNEON_Base::VifUnpackNEON_Base()
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: usn(false)
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, doMask(false)
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, UnpkLoopIteration(0)
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, UnpkNoOfIterations(0)
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, IsAligned(0)
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, dstIndirect(a64::MemOperand(RXARG1))
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, srcIndirect(a64::MemOperand(RXARG2))
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, workReg(a64::q1)
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, destReg(a64::q0)
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, workGprW(a64::w4)
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{
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}
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void VifUnpackNEON_Base::xMovDest() const
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{
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if (!IsWriteProtectedOp())
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{
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if (IsUnmaskedOp())
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armAsm->Str(destReg, dstIndirect);
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else
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doMaskWrite(destReg);
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}
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}
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void VifUnpackNEON_Base::xShiftR(const vixl::aarch64::VRegister& regX, int n) const
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{
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if (usn)
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armAsm->Ushr(regX.V4S(), regX.V4S(), n);
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else
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armAsm->Sshr(regX.V4S(), regX.V4S(), n);
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}
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void VifUnpackNEON_Base::xPMOVXX8(const vixl::aarch64::VRegister& regX) const
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{
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// TODO(Stenzek): Check this
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armAsm->Ldr(regX.S(), srcIndirect);
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if (usn)
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{
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armAsm->Ushll(regX.V8H(), regX.V8B(), 0);
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armAsm->Ushll(regX.V4S(), regX.V4H(), 0);
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}
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else
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{
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armAsm->Sshll(regX.V8H(), regX.V8B(), 0);
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armAsm->Sshll(regX.V4S(), regX.V4H(), 0);
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}
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}
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void VifUnpackNEON_Base::xPMOVXX16(const vixl::aarch64::VRegister& regX) const
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{
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armAsm->Ldr(regX.D(), srcIndirect);
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if (usn)
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armAsm->Ushll(regX.V4S(), regX.V4H(), 0);
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else
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armAsm->Sshll(regX.V4S(), regX.V4H(), 0);
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}
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void VifUnpackNEON_Base::xUPK_S_32() const
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{
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if (UnpkLoopIteration == 0)
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armAsm->Ldr(workReg, srcIndirect);
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if (IsInputMasked())
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return;
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switch (UnpkLoopIteration)
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{
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case 0:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 0);
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break;
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case 1:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 1);
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break;
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case 2:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 2);
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break;
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case 3:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 3);
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break;
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}
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}
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void VifUnpackNEON_Base::xUPK_S_16() const
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{
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if (UnpkLoopIteration == 0)
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xPMOVXX16(workReg);
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if (IsInputMasked())
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return;
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switch (UnpkLoopIteration)
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{
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case 0:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 0);
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break;
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case 1:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 1);
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break;
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case 2:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 2);
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break;
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case 3:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 3);
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break;
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}
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}
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void VifUnpackNEON_Base::xUPK_S_8() const
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{
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if (UnpkLoopIteration == 0)
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xPMOVXX8(workReg);
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if (IsInputMasked())
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return;
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switch (UnpkLoopIteration)
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{
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case 0:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 0);
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break;
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case 1:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 1);
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break;
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case 2:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 2);
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break;
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case 3:
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armAsm->Dup(destReg.V4S(), workReg.V4S(), 3);
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break;
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}
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}
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// The V2 + V3 unpacks have freaky behaviour, the manual claims "indeterminate".
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// After testing on the PS2, it's very much determinate in 99% of cases
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// and games like Lemmings, And1 Streetball rely on this data to be like this!
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// I have commented after each shuffle to show what data is going where - Ref
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void VifUnpackNEON_Base::xUPK_V2_32() const
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{
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if (UnpkLoopIteration == 0)
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{
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armAsm->Ldr(workReg, srcIndirect);
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if (IsInputMasked())
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return;
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armAsm->Dup(destReg.V2D(), workReg.V2D(), 0); //v1v0v1v0
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if (IsAligned)
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armAsm->Ins(destReg.V4S(), 3, a64::wzr); //zero last word - tested on ps2
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}
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else
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{
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if (IsInputMasked())
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return;
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armAsm->Dup(destReg.V2D(), workReg.V2D(), 1); //v3v2v3v2
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if (IsAligned)
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armAsm->Ins(destReg.V4S(), 3, a64::wzr); //zero last word - tested on ps2
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}
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}
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void VifUnpackNEON_Base::xUPK_V2_16() const
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{
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if (UnpkLoopIteration == 0)
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{
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xPMOVXX16(workReg);
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if (IsInputMasked())
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return;
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armAsm->Dup(destReg.V2D(), workReg.V2D(), 0); //v1v0v1v0
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}
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else
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{
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if (IsInputMasked())
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return;
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armAsm->Dup(destReg.V2D(), workReg.V2D(), 1); //v3v2v3v2
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}
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}
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void VifUnpackNEON_Base::xUPK_V2_8() const
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{
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if (UnpkLoopIteration == 0)
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{
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xPMOVXX8(workReg);
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if (IsInputMasked())
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return;
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armAsm->Dup(destReg.V2D(), workReg.V2D(), 0); //v1v0v1v0
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}
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else
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{
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if (IsInputMasked())
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return;
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armAsm->Dup(destReg.V2D(), workReg.V2D(), 1); //v3v2v3v2
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}
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}
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void VifUnpackNEON_Base::xUPK_V3_32() const
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{
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if (IsInputMasked())
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return;
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armAsm->Ldr(destReg, srcIndirect);
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if (UnpkLoopIteration != IsAligned)
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armAsm->Ins(destReg.V4S(), 3, a64::wzr);
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}
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void VifUnpackNEON_Base::xUPK_V3_16() const
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{
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if (IsInputMasked())
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return;
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xPMOVXX16(destReg);
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//With V3-16, it takes the first vector from the next position as the W vector
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//However - IF the end of this iteration of the unpack falls on a quadword boundary, W becomes 0
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//IsAligned is the position through the current QW in the vif packet
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//Iteration counts where we are in the packet.
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int result = (((UnpkLoopIteration / 4) + 1 + (4 - IsAligned)) & 0x3);
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if ((UnpkLoopIteration & 0x1) == 0 && result == 0)
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armAsm->Ins(destReg.V4S(), 3, a64::wzr); //zero last word on QW boundary if whole 32bit word is used - tested on ps2
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}
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void VifUnpackNEON_Base::xUPK_V3_8() const
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{
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if (IsInputMasked())
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return;
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xPMOVXX8(destReg);
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if (UnpkLoopIteration != IsAligned)
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armAsm->Ins(destReg.V4S(), 3, a64::wzr);
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}
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void VifUnpackNEON_Base::xUPK_V4_32() const
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{
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if (IsInputMasked())
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return;
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armAsm->Ldr(destReg.Q(), a64::MemOperand(srcIndirect));
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}
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void VifUnpackNEON_Base::xUPK_V4_16() const
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{
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if (IsInputMasked())
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return;
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xPMOVXX16(destReg);
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}
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void VifUnpackNEON_Base::xUPK_V4_8() const
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{
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if (IsInputMasked())
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return;
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xPMOVXX8(destReg);
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}
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void VifUnpackNEON_Base::xUPK_V4_5() const
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{
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if (IsInputMasked())
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return;
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armAsm->Ldrh(workGprW, srcIndirect);
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armAsm->Lsl(workGprW, workGprW, 3); // ABG|R5.000
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armAsm->Dup(destReg.V4S(), workGprW); // x|x|x|R
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armAsm->Lsr(workGprW, workGprW, 8); // ABG
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armAsm->Lsl(workGprW, workGprW, 3); // AB|G5.000
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armAsm->Ins(destReg.V4S(), 1, workGprW); // x|x|G|R
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armAsm->Lsr(workGprW, workGprW, 8); // AB
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armAsm->Lsl(workGprW, workGprW, 3); // A|B5.000
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armAsm->Ins(destReg.V4S(), 2, workGprW); // x|B|G|R
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armAsm->Lsr(workGprW, workGprW, 8); // A
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armAsm->Lsl(workGprW, workGprW, 7); // A.0000000
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armAsm->Ins(destReg.V4S(), 3, workGprW); // A|B|G|R
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// Zero the upper 24 bits of each lane (lanes carry per-channel
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// Lsr/Lsl residue from the unpack chain above). Shl+Ushr is 2
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// NEON insns; an AND with a pre-built mask is the same count
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// (Movi #0xFF + And) so no win — keep the shift form.
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armAsm->Shl(destReg.V4S(), destReg.V4S(), 24);
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armAsm->Ushr(destReg.V4S(), destReg.V4S(), 24);
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}
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void VifUnpackNEON_Base::xUnpack(int upknum) const
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{
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switch (upknum)
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{
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case 0:
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xUPK_S_32();
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break;
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case 1:
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xUPK_S_16();
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break;
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case 2:
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xUPK_S_8();
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break;
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case 4:
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xUPK_V2_32();
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break;
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case 5:
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xUPK_V2_16();
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break;
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case 6:
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xUPK_V2_8();
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break;
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case 8:
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xUPK_V3_32();
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break;
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case 9:
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xUPK_V3_16();
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break;
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case 10:
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xUPK_V3_8();
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break;
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case 12:
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xUPK_V4_32();
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break;
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case 13:
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xUPK_V4_16();
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break;
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case 14:
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xUPK_V4_8();
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break;
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case 15:
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xUPK_V4_5();
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break;
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case 3:
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case 7:
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case 11:
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// TODO: Needs hardware testing.
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// Dynasty Warriors 5: Empire - Player 2 chose a character menu.
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Console.Warning("Vpu/Vif: Invalid Unpack %d", upknum);
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break;
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}
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}
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// =====================================================================================================
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// VifUnpackSSE_Simple
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// =====================================================================================================
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VifUnpackNEON_Simple::VifUnpackNEON_Simple(bool usn_, bool domask_, int curCycle_)
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{
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curCycle = curCycle_;
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usn = usn_;
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doMask = domask_;
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IsAligned = true;
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}
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void VifUnpackNEON_Simple::doMaskWrite(const vixl::aarch64::VRegister& regX) const
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{
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armAsm->Ldr(a64::q7, dstIndirect);
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int offX = std::min(curCycle, 3);
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armMoveAddressToReg(RXVIXLSCRATCH, nVifMask);
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armAsm->Ldr(a64::q29, a64::MemOperand(RXVIXLSCRATCH, reinterpret_cast<const u8*>(nVifMask[0][offX]) - reinterpret_cast<const u8*>(nVifMask)));
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armAsm->Ldr(a64::q30, a64::MemOperand(RXVIXLSCRATCH, reinterpret_cast<const u8*>(nVifMask[1][offX]) - reinterpret_cast<const u8*>(nVifMask)));
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armAsm->Ldr(a64::q31, a64::MemOperand(RXVIXLSCRATCH, reinterpret_cast<const u8*>(nVifMask[2][offX]) - reinterpret_cast<const u8*>(nVifMask)));
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armAsm->And(regX.V16B(), regX.V16B(), a64::q29.V16B());
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armAsm->And(a64::q7.V16B(), a64::q7.V16B(), a64::q30.V16B());
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armAsm->Orr(regX.V16B(), regX.V16B(), a64::q31.V16B());
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armAsm->Orr(regX.V16B(), regX.V16B(), a64::q7.V16B());
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armAsm->Str(regX, dstIndirect);
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}
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// ecx = dest, edx = src
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static void nVifGen(int usn, int mask, int curCycle)
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{
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int usnpart = usn * 2 * 16;
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int maskpart = mask * 16;
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VifUnpackNEON_Simple vpugen(!!usn, !!mask, curCycle);
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for (int i = 0; i < 16; ++i)
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{
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nVifCall& ucall(nVifUpk[((usnpart + maskpart + i) * 4) + curCycle]);
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ucall = NULL;
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if (nVifT[i] == 0)
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continue;
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ucall = (nVifCall)armStartBlock();
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vpugen.xUnpack(i);
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vpugen.xMovDest();
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armAsm->Ret();
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armEndBlock();
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}
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}
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void VifUnpackSSE_Init()
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{
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DevCon.WriteLn("Generating NEON-optimized unpacking functions for VIF interpreters...");
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HostSys::BeginCodeWrite();
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armSetAsmPtr(SysMemory::GetVIFUnpackRec(), SysMemory::GetVIFUnpackRecEnd() - SysMemory::GetVIFUnpackRec(), nullptr);
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for (int a = 0; a < 2; a++)
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{
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for (int b = 0; b < 2; b++)
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{
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for (int c = 0; c < 4; c++)
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{
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nVifGen(a, b, c);
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}
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}
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}
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Perf::any.Register(SysMemory::GetVIFUnpackRec(), armGetAsmPtr() - SysMemory::GetVIFUnpackRec(), "VIF Unpack");
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HostSys::EndCodeWrite();
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}
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