mirror of
https://github.com/ARMSX2/ARMSX2.git
synced 2026-08-24 16:50:16 -07:00
Brian Degenhardt
fc55cd86f1
AndroidPerfBuckets.h wrapped hot EE/VU/GS/VIF paths in steady_clock reads and relaxed atomic adds, gated on ARMSX2_ANDROID_PERF_BUCKETS. It served its purpose: the 2026-06-17 run used it to pin the dominant EE cost on ee_interp_step. Its call sites are all gone now, so the header's claim that "the atomic counters and every call site stay compiled in either way" no longer holds, and nothing anywhere names AndroidPerfBuckets::. Its one remaining consumer was arm64/Vif_Dynarec.cpp, which included it twice on consecutive lines and used nothing from it - that duplicate include goes too. Perf jitdump covers this now. PS1DrvTrace.h supplied rate-limited PS1DRV_LOG_/RATE_/CHG_ macros for PS1-mode debugging, each gated on a PS1DRV_TRACE_<CAT> define. No translation unit ever included it.
523 lines
14 KiB
C++
523 lines
14 KiB
C++
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
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// SPDX-FileCopyrightText: 2026 isztld <https://isztld.com/>
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// SPDX-License-Identifier: GPL-3.0
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#include "arm64/Vif_UnpackNEON.h"
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#include "arm64/AsmHelpers.h"
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#include "MTVU.h"
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#include "common/Assertions.h"
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#include "common/Perf.h"
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#include "common/StringUtil.h"
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namespace a64 = vixl::aarch64;
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static void maskedVecWrite(const a64::VRegister& reg, const a64::MemOperand& addr, int xyzw)
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{
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switch (xyzw)
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{
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case 5: // YW
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 4);
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armAsm->St1(reg.V4S(), 1, a64::MemOperand(RSCRATCHADDR)); // Y
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 12);
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armAsm->St1(reg.V4S(), 3, a64::MemOperand(RSCRATCHADDR)); // W
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break;
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case 9: // XW
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 12);
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armAsm->Str(reg.S(), addr); // X
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armAsm->St1(reg.V4S(), 3, a64::MemOperand(RSCRATCHADDR)); // W
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break;
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case 10: //XZ
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 8);
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armAsm->Str(reg.S(), addr); // X
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armAsm->St1(reg.V4S(), 2, a64::MemOperand(RSCRATCHADDR)); // Z
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break;
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case 3: // ZW
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 8);
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armAsm->St1(reg.V2D(), 1, a64::MemOperand(RSCRATCHADDR));
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break;
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case 11: //XZW
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 8);
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armAsm->Str(reg.S(), addr); // X
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armAsm->St1(reg.V2D(), 1, a64::MemOperand(RSCRATCHADDR)); // ZW
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break;
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case 13: // XYW
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 12);
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armAsm->Str(reg.D(), addr);
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armAsm->St1(reg.V4S(), 3, a64::MemOperand(RSCRATCHADDR));
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break;
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case 6: // YZ
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 4);
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armAsm->St1(reg.V4S(), 1, a64::MemOperand(RSCRATCHADDR, 4, a64::PostIndex));
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armAsm->St1(reg.V4S(), 2, a64::MemOperand(RSCRATCHADDR));
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break;
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case 7: // YZW
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 4);
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armAsm->St1(reg.V4S(), 1, a64::MemOperand(RSCRATCHADDR, 4, a64::PostIndex));
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armAsm->St1(reg.V2D(), 1, a64::MemOperand(RSCRATCHADDR));
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break;
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case 12: // XY
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armAsm->Str(reg.D(), addr);
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break;
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case 14: // XYZ
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 8);
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armAsm->Str(reg.D(), addr);
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armAsm->St1(reg.V4S(), 2, a64::MemOperand(RSCRATCHADDR)); // Z
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break;
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case 4:
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 4);
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armAsm->St1(reg.V4S(), 1, a64::MemOperand(RSCRATCHADDR));
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break; // Y
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case 2:
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 8);
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armAsm->St1(reg.V4S(), 2, a64::MemOperand(RSCRATCHADDR));
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break; // Z
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case 1:
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armGetMemOperandInRegister(RSCRATCHADDR, addr, 12);
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armAsm->St1(reg.V4S(), 3, a64::MemOperand(RSCRATCHADDR));
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break; // W
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case 8:
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armAsm->Str(reg.S(), addr);
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break; // X
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case 0:
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Console.Error("maskedVecWrite case 0!");
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break;
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default:
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armAsm->Str(reg.Q(), addr);
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break; // XYZW
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}
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}
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void dVifReset(int idx)
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{
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nVif[idx].vifBlocks.reset();
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const size_t offset = idx ? HostMemoryMap::VIF1recOffset : HostMemoryMap::VIF0recOffset;
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const size_t size = idx ? HostMemoryMap::VIF1recSize : HostMemoryMap::VIF0recSize;
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nVif[idx].recWritePtr = SysMemory::GetCodePtr(offset);
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nVif[idx].recEndPtr = nVif[idx].recWritePtr + (size - _256kb);
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}
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void dVifRelease(int idx)
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{
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nVif[idx].vifBlocks.clear();
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}
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VifUnpackNEON_Dynarec::VifUnpackNEON_Dynarec(const nVifStruct& vif_, const nVifBlock& vifBlock_)
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: v(vif_)
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, vB(vifBlock_)
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{
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const int wl = vB.wl ? vB.wl : 256; //0 is taken as 256 (KH2)
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isFill = (vB.cl < wl);
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usn = (vB.upkType >> 5) & 1;
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doMask = (vB.upkType >> 4) & 1;
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doMode = vB.mode & 3;
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IsAligned = vB.aligned;
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vCL = 0;
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}
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__fi void makeMergeMask(u32& x)
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{
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x = ((x & 0x40) >> 6) | ((x & 0x10) >> 3) | (x & 4) | ((x & 1) << 3);
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}
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__fi void VifUnpackNEON_Dynarec::SetMasks(int cS) const
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{
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const int idx = v.idx;
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const vifStruct& vif = MTVU_VifX;
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//This could have ended up copying the row when there was no row to write.1810080
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u32 m0 = vB.mask; //The actual mask example 0x03020100
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u32 m3 = ((m0 & 0xaaaaaaaa) >> 1) & ~m0; //all the upper bits, so our example 0x01010000 & 0xFCFDFEFF = 0x00010000 just the cols (shifted right for maskmerge)
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u32 m2 = (m0 & 0x55555555) & (~m0 >> 1); // 0x1000100 & 0xFE7EFF7F = 0x00000100 Just the row
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if ((doMask && m2) || doMode)
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{
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armLoadPtr(xmmRow, &vif.MaskRow);
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MSKPATH3_LOG("Moving row");
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}
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if (doMask && m3)
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{
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VIF_LOG("Merging Cols");
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armLoadPtr(xmmCol0, &vif.MaskCol);
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if ((cS >= 2) && (m3 & 0x0000ff00))
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armAsm->Dup(xmmCol1.V4S(), xmmCol0.V4S(), 1);
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if ((cS >= 3) && (m3 & 0x00ff0000))
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armAsm->Dup(xmmCol2.V4S(), xmmCol0.V4S(), 2);
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if ((cS >= 4) && (m3 & 0xff000000))
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armAsm->Dup(xmmCol3.V4S(), xmmCol0.V4S(), 3);
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if ((cS >= 1) && (m3 & 0x000000ff))
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armAsm->Dup(xmmCol0.V4S(), xmmCol0.V4S(), 0);
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}
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//if (doMask||doMode) loadRowCol((nVifStruct&)v);
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}
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void VifUnpackNEON_Dynarec::doMaskWrite(const vixl::aarch64::VRegister& regX) const
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{
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pxAssertMsg(regX.GetCode() <= 1, "Reg Overflow! XMM2 thru XMM6 are reserved for masking.");
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const int cc = std::min(vCL, 3);
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u32 m0 = (vB.mask >> (cc * 8)) & 0xff; //The actual mask example 0xE4 (protect, col, row, clear)
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u32 m3 = ((m0 & 0xaa) >> 1) & ~m0; //all the upper bits (cols shifted right) cancelling out any write protects 0x10
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u32 m2 = (m0 & 0x55) & (~m0 >> 1); // all the lower bits (rows)cancelling out any write protects 0x04
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u32 m4 = (m0 & ~((m3 << 1) | m2)) & 0x55; // = 0xC0 & 0x55 = 0x40 (for merge mask)
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makeMergeMask(m2);
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makeMergeMask(m3);
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makeMergeMask(m4);
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if (doMask && m2) // Merge MaskRow
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{
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mVUmergeRegs(regX, xmmRow, m2);
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}
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if (doMask && m3) // Merge MaskCol
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{
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mVUmergeRegs(regX, armQRegister(xmmCol0.GetCode() + cc), m3);
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}
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if (doMode)
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{
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u32 m5 = ~(m2 | m3 | m4) & 0xf;
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if (!doMask)
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m5 = 0xf;
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if (m5 < 0xf)
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{
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armAsm->Movi(xmmTemp.V4S(), 0);
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if (doMode == 3)
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{
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mVUmergeRegs(xmmRow, regX, m5);
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}
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else
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{
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mVUmergeRegs(xmmTemp, xmmRow, m5);
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armAsm->Add(regX.V4S(), regX.V4S(), xmmTemp.V4S());
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if (doMode == 2)
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mVUmergeRegs(xmmRow, regX, m5);
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}
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}
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else
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{
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if (doMode == 3)
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{
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armAsm->Mov(xmmRow, regX);
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}
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else
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{
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armAsm->Add(regX.V4S(), regX.V4S(), xmmRow.V4S());
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if (doMode == 2)
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{
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armAsm->Mov(xmmRow, regX);
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}
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}
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}
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}
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if (doMask && m4)
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maskedVecWrite(regX, dstIndirect, m4 ^ 0xf);
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else
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armAsm->Str(regX, dstIndirect);
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}
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void VifUnpackNEON_Dynarec::writeBackRow() const
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{
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const int idx = v.idx;
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armStorePtr(xmmRow, &(MTVU_VifX.MaskRow));
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VIF_LOG("nVif: writing back row reg! [doMode = %d]", doMode);
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}
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void VifUnpackNEON_Dynarec::ModUnpack(int upknum, bool PostOp)
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{
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switch (upknum)
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{
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case 0:
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case 1:
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case 2:
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if (PostOp)
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{
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UnpkLoopIteration++;
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UnpkLoopIteration = UnpkLoopIteration & 0x3;
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}
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break;
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case 4:
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case 5:
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case 6:
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if (PostOp)
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{
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UnpkLoopIteration++;
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UnpkLoopIteration = UnpkLoopIteration & 0x1;
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}
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break;
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case 8:
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if (PostOp)
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{
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UnpkLoopIteration++;
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UnpkLoopIteration = UnpkLoopIteration & 0x1;
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}
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break;
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case 9:
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if (!PostOp)
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{
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UnpkLoopIteration++;
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}
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break;
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case 10:
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if (!PostOp)
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{
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UnpkLoopIteration++;
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}
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break;
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case 12:
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break;
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case 13:
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break;
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case 14:
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break;
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case 15:
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break;
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case 3:
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case 7:
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case 11:
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// TODO: Needs hardware testing.
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// Dynasty Warriors 5: Empire - Player 2 chose a character menu.
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Console.Warning("Vpu/Vif: Invalid Unpack %d", upknum);
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break;
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}
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}
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void VifUnpackNEON_Dynarec::ProcessMasks()
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{
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skipProcessing = false;
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inputMasked = false;
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if (!doMask)
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return;
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const int cc = std::min(vCL, 3);
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const u32 full_mask = (vB.mask >> (cc * 8)) & 0xff;
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const u32 rowcol_mask = ((full_mask >> 1) | full_mask) & 0x55; // Rows or Cols being written instead of data, or protected.
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// Every channel is write protected for this cycle, no need to process anything.
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skipProcessing = full_mask == 0xff;
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// All channels are masked, no reason to process anything here.
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inputMasked = rowcol_mask == 0x55;
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}
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void VifUnpackNEON_Dynarec::CompileRoutine()
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{
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const int wl = vB.wl ? vB.wl : 256; //0 is taken as 256 (KH2)
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const int upkNum = vB.upkType & 0xf;
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const u8& vift = nVifT[upkNum];
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const int cycleSize = isFill ? vB.cl : wl;
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const int blockSize = isFill ? wl : vB.cl;
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const int skipSize = blockSize - cycleSize;
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uint vNum = vB.num ? vB.num : 256;
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doMode = (upkNum == 0xf) ? 0 : doMode; // V4_5 has no mode feature.
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UnpkNoOfIterations = 0;
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VIF_LOG("Compiling new block, unpack number %x, mode %x, masking %x, vNum %x", upkNum, doMode, doMask, vNum);
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pxAssume(vCL == 0);
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// Value passed determines # of col regs we need to load
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SetMasks(isFill ? blockSize : cycleSize);
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while (vNum)
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{
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// Determine if reads/processing can be skipped.
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ProcessMasks();
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if (vCL < cycleSize)
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{
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ModUnpack(upkNum, false);
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xUnpack(upkNum);
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xMovDest();
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ModUnpack(upkNum, true);
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dstIndirect = armOffsetMemOperand(dstIndirect, 16);
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srcIndirect = armOffsetMemOperand(srcIndirect, vift);
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vNum--;
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if (++vCL == blockSize)
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vCL = 0;
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}
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else if (isFill)
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{
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xUnpack(upkNum);
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xMovDest();
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// dstIndirect += 16;
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dstIndirect = armOffsetMemOperand(dstIndirect, 16);
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vNum--;
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if (++vCL == blockSize)
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vCL = 0;
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}
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else
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{
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// dstIndirect += (16 * skipSize);
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dstIndirect = armOffsetMemOperand(dstIndirect, 16 * skipSize);
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vCL = 0;
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}
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}
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if (doMode >= 2)
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writeBackRow();
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armAsm->Ret();
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}
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static u16 dVifComputeLength(uint cl, uint wl, u8 num, bool isFill)
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{
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uint length = (num > 0) ? (num * 16) : 4096; // 0 = 256
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if (!isFill)
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{
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uint skipSize = (cl - wl) * 16;
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uint blocks = (num + (wl - 1)) / wl; //Need to round up num's to calculate skip size correctly.
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length += (blocks - 1) * skipSize;
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}
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return std::min(length, 0xFFFFu);
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}
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_vifT __fi nVifBlock* dVifCompile(nVifBlock& block, bool isFill)
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{
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nVifStruct& v = nVif[idx];
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// Check size before the compilation
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if (v.recWritePtr >= v.recEndPtr)
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{
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DevCon.WriteLn("nVif Recompiler Cache Reset! [0x%016" PRIXPTR " > 0x%016" PRIXPTR "]",
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v.recWritePtr, v.recEndPtr);
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dVifReset(idx);
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}
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// Compile the block now. Capacity includes the 256 KB slack past
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// recEndPtr (dVifReset carved it out of the physical region size): the
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// bounds check above only guarantees the routine STARTS below recEndPtr;
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// the slack exists so it can finish past it. Binding capacity at
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// recEndPtr would make vixl abort on an unmanaged-buffer Grow instead —
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// same bug as the mVU cache (SM8650 OutRun 2006, 2026-07-02).
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armSetAsmPtr(v.recWritePtr, v.recEndPtr - v.recWritePtr + _256kb, nullptr);
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block.startPtr = (uptr)armStartBlock();
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block.length = dVifComputeLength(block.cl, block.wl, block.num, isFill);
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v.vifBlocks.add(block);
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VifUnpackNEON_Dynarec(v, block).CompileRoutine();
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Perf::vif.RegisterPC(v.recWritePtr, armGetCurrentCodePointer() - v.recWritePtr, block.upkType /* FIXME ideally a key*/);
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v.recWritePtr = armEndBlock();
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return █
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}
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_vifT __fi void dVifUnpack(const u8* data, bool isFill)
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{
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nVifStruct& v = nVif[idx];
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vifStruct& vif = MTVU_VifX;
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VIFregisters& vifRegs = MTVU_VifXRegs;
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const u8 upkType = (vif.cmd & 0x1f) | (vif.usn << 5);
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const int doMask = isFill ? 1 : (vif.cmd & 0x10);
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nVifBlock block;
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// Performance note: initial code was using u8/u16 field of the struct
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// directly. However reading back the data (as u32) in HashBucket.find
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// leads to various memory stalls. So it is way faster to manually build the data
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// in u32 (aka x86 register).
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//
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// Warning the order of data in hash_key/key0/key1 depends on the nVifBlock struct
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u32 hash_key = (u32)(upkType & 0xFF) << 8 | (vifRegs.num & 0xFF);
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u32 key1 = ((u32)vifRegs.cycle.wl << 24) | ((u32)vifRegs.cycle.cl << 16) | ((u32)(vif.start_aligned & 0xFF) << 8) | ((u32)vifRegs.mode & 0xFF);
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if ((upkType & 0xf) != 9)
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key1 &= 0xFFFF01FF;
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// Zero out the mask parameter if it's unused -- games leave random junk
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// values here which cause false recblock cache misses.
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u32 key0 = doMask ? vifRegs.mask : 0;
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block.hash_key = hash_key;
|
|
block.key0 = key0;
|
|
block.key1 = key1;
|
|
|
|
//DevCon.WriteLn("nVif%d: Recompiled Block!", idx);
|
|
//DevCon.WriteLn(L"[num=% 3d][upkType=0x%02x][scl=%d][cl=%d][wl=%d][mode=%d][m=%d][mask=%s]",
|
|
// block.num, block.upkType, block.scl, block.cl, block.wl, block.mode,
|
|
// doMask >> 4, doMask ? wxsFormat( L"0x%08x", block.mask ).c_str() : L"ignored"
|
|
//);
|
|
|
|
// Seach in cache before trying to compile the block
|
|
nVifBlock* b = v.vifBlocks.find(block);
|
|
if (!b) [[unlikely]]
|
|
{
|
|
b = dVifCompile<idx>(block, isFill);
|
|
}
|
|
|
|
{ // Execute the block
|
|
const VURegs& VU = vuRegs[idx];
|
|
const uint vuMemLimit = idx ? 0x4000 : 0x1000;
|
|
|
|
u8* startmem = VU.Mem + (vif.tag.addr & (vuMemLimit - 0x10));
|
|
u8* endmem = VU.Mem + vuMemLimit;
|
|
|
|
if ((startmem + b->length) <= endmem) [[likely]]
|
|
{
|
|
#if 1
|
|
// No wrapping, you can run the fast dynarec
|
|
((nVifrecCall)b->startPtr)((uptr)startmem, (uptr)data);
|
|
#else
|
|
// comparison mode
|
|
static u8 tmpbuf[512 * 1024];
|
|
((nVifrecCall)b->startPtr)((uptr)tmpbuf, (uptr)data);
|
|
|
|
_nVifUnpack(idx, data, vifRegs.mode, isFill);
|
|
|
|
const u32 words = b->length / 4;
|
|
for (u32 i = 0; i < words; i++)
|
|
{
|
|
if (*((u32*)tmpbuf + i) != *((u32*)startmem + i))
|
|
{
|
|
// fprintf(stderr, "%08X %08X @ %u\n", *((u32*)tmpbuf + i), *((u32*)startmem + i), i);
|
|
pauseCCC(*((u32*)tmpbuf + i), *((u32*)startmem + i), i);
|
|
((nVifrecCall)b->startPtr)((uptr)tmpbuf, (uptr)data);
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
VIF_LOG("Running Interpreter Block: nVif%x - VU Mem Ptr Overflow; falling back to interpreter. Start = %x End = %x num = %x, wl = %x, cl = %x",
|
|
v.idx, vif.tag.addr, vif.tag.addr + (block.num * 16), block.num, block.wl, block.cl);
|
|
_nVifUnpack(idx, data, vifRegs.mode, isFill);
|
|
}
|
|
}
|
|
}
|
|
|
|
template void dVifUnpack<0>(const u8* data, bool isFill);
|
|
template void dVifUnpack<1>(const u8* data, bool isFill);
|