The EE's divide unit was timed on silicon to bound what its recurrence can
be -- eleven rounds of modelling its rounding had never constrained the
hypothesis space, and cycles per quotient bit constrains it hard.
DIV.S and SQRT.S each occupy the FPU for 7 cycles and RSQRT.S for 13, against
this table's 6, 6 and 8. MUL.S is latency 4 / issue interval 1, which is the
one entry the table already has right. Measured with COP0 Count around loops
of k copies of one instruction so the loop overhead falls out as the intercept;
four runs, three byte-identical.
The interesting part is not the numbers but the mix. Interleaved div.s/sqrt.s
costs the sum while div.s/add.s costs the divide alone, so div and sqrt are one
shared non-pipelined unit rather than two that happen to take equally long, and
RSQRT.S at 7+7-1 is two passes through it -- which is what FPU.cpp's RSQRT_S
already assumed from values alone. The latency does not move on any operand
class, including denormals and divide by zero, so there is no early-out.
The table is not touched. It drives game timing, its own comment already calls
itself a hack, and nothing here measured what moving it would do to
compatibility; that is a separate change with a separate burden of proof. The
comment exists so the console run does not have to be taken a third time.
Idea by pstef.
Full ARM64 EE dynarec — dispatcher, iFlushCall, block emitter and opcode subgroups
(Arit/Branch/Jump/LoadStore/Misc/Move/MultDiv/Shift/Templates), the COP0/COP2/FPU/MMI
coprocessor codegen, the register allocator core (iCore), VTLB codegen, and the EE
block-analysis pass. EE GPRs are allocated in NEON registers, per the approach used
in a reference ARM64 PS2 implementation.
Co-Authored-By: Ryan Walklin <ryan@testtoast.com>
Co-Authored-By: Brian Degenhardt <bmd@bmdhacks.com>
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
- Advanced disassembly view for R5900 and R3000
- Register list with change highlight
- Editable memory view
- Conditional execute breakpoints (r5900 only)
- Step over
- Scan for functions (incomplete), show macros
- Enable C++11 for debug tools.
- Expression parser
- Disasm updates for thread safety
Squashed from: https://github.com/PCSX2/pcsx2/pull/1
Thanks to Kingcom for coding it all and mziab for Linux patches
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5905 96395faa-99c1-11dd-bbfe-3dabce05a288
This hopefully lets a few regressed games work again.
Also a speedup, specially in fmv..
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1731 96395faa-99c1-11dd-bbfe-3dabce05a288
Also added COP0 DIE bit handling, that disables the EE's dual issue capabilities.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1029 96395faa-99c1-11dd-bbfe-3dabce05a288
-Added a safety to the VU cycle stealing hack, so it doesn't go berserk :p
Note:
Due to the changed cycle count a lot of games will get "slower".
Especially FMV will be affected.
This is unfortunate, but correct emulation comes first.
You can however enable the ee sync speedhacks, as they're more stable now as well.
This can bring back the lost speed.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@999 96395faa-99c1-11dd-bbfe-3dabce05a288
Added interface.cpp (plugin/pcsx2 interface) and savestate.cpp to SPU2ghz, to help clean up SPU2.cpp.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@463 96395faa-99c1-11dd-bbfe-3dabce05a288
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