Env-var gates are testing-only and the A/B is done. The off-arm never
needed an in-tree gate: prctl(PR_SET_THP_DISABLE) survives execve, so
fx15_thp_ab.sh now disables THP from outside the process (both arms exec
through a symmetric python3 wrapper). Verified on-device: zero arena
hugepages under the wrapper vs 8MB without.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Design credit FEX-Emu (MIT): back the hot rec caches with transparent
hugepages to cut iTLB pressure. Scoped to the EE+IOP and mVU0+mVU1
contiguous pairs (static_asserts pin the layout), leaving the VIF/SW
tail alone; the code half is a private anonymous mapping, which is
what THP backs, and Rocknix ships THP in madvise mode. YAPS2_NO_THP=1
kill-switch for the iTLB A/B (testing-only gate). Linux-only.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
SharedMemoryMappingArea::Create() gains a fixed_base_hint so AllocateMemoryMap can
pin the JIT arena at a constant VA (kArenaBase=4GB, 256MB-stride fallback) on arm64;
the VTLB fastmem backpatch thunk (RecStubs), ArmAddressRecorder relocation hooks
(AsmHelpers), and the cpuTlbMiss rec-vs-interp PC split (R5900) round out the arm64
memory layer. Windows arm64 is a no-op stub.
Co-Authored-By: Ryan Walklin <ryan@testtoast.com>
Co-Authored-By: Brian Degenhardt <bmd@bmdhacks.com>
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Brian DegenhardtandClaude Fable 5
chaoticgd
TellowKrinkle
Ziemas
SternXD
NightFyre
refractionpcsx2
TheTechnician27
GovanifY
Stenzek
Benjamin Moir