33 Commits
Author SHA1 Message Date
8fb919e6f7 arm64: in-process recompiler differential-test + diagnostics framework
DiffJitVsInterp harness (EE/IOP/VU synthetic JIT-vs-interpreter tests) plus the
shared capture/divergence-localizer infrastructure (vu_capture, ee_divtrace,
microVU_Divtrace, VU1Trace) and the test hooks they install in interp/GIF/COP2 paths.
All hook sites are guarded by PCSX2_RECOMPILER_TESTS and compile out of release builds.

Co-Authored-By: Ryan Walklin <ryan@testtoast.com>
Co-Authored-By: Brian Degenhardt <bmd@bmdhacks.com>
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-06-20 20:27:56 -07:00
SternXD d983b2b066 Copyright: Change year from 2002-2025 to 2002-2026 2026-01-15 00:22:32 +01:00
TheTechnician27 23fd57f641 Copyright: Change year from 2002-2024 to 2002-2025 2025-01-20 05:07:26 +01:00
GovanifY 132431b7c8 headers: relicense to GPL-3.0+
also update to 2024 while i'm at it
2024-07-30 17:17:13 -04:00
Stenzek 4608579c31 GIF: Get rid of assertion with side effects 2023-12-24 23:12:12 +10:00
Stenzek d9abe10308 Misc: Remove explicit PCH include, switch to SPDX 2023-12-24 14:03:14 +10:00
Stenzek dc859ca0a6 Misc: Simplify assertion macros 2023-12-24 14:03:14 +10:00
refractionpcsx2 2947e11b9b GIF: Correctly delay FINISH interrupts/flags
[SAVEVERSION+]
2023-09-17 14:52:47 +01:00
Stenzek 81236209db SaveState: Remove exceptions 2023-06-30 21:37:44 +10:00
Stenzek 55e73bb4b9 MTGS: Convert to namespace 2023-06-25 12:54:14 +10:00
refractionpcsx2 35387eeabb GIF: Fix some incorrect unknown register warnings 2023-06-04 18:20:02 +01:00
refractionpcsx2 0e3397239d GS: Correct GSIMR/GSCSR reg init, regression from previous release 2023-01-31 16:55:45 +00:00
Connor McLaughlin edd735ce80 GS: Read local memory without sync when readbacks are disabled 2022-05-29 16:15:34 +01:00
TellowKrinkle 648a958290 GS: Split GS.h into multiple smaller headers 2021-11-14 13:52:20 -06:00
refractionpcsx2 c77e0a3a56 microVU: Enable T-Bit to work with MTVU 2021-07-05 10:26:50 +01:00
refractionpcsx2 b60765e976 Gif: Remove MTVU spam that isn't required
Solves stuttering in MTVU mode in some games, and gets rid of some annoying asserts which mean nothing.
2021-04-05 04:45:04 +01:00
TellowKrinkle 4ffc0d2247 MTVU: Allow stacking of LABEL 2020-12-28 02:12:52 -06:00
TellowKrinkle 3c2f7983a5 MTVU: Cleaned up GS SIGNAL/LABEL/FINISH communication 2020-12-28 02:12:52 -06:00
refractionpcsx2 d78de3237c MTVU: Redesign of how to handle signals, seems more reliable
Added new variables to savestates
2020-12-24 09:03:45 +00:00
refractionpcsx2 6066f48d7c MTVU/GIF: Clang Formatting 2020-12-24 09:03:45 +00:00
refractionpcsx2 3f4bb44310 MTVU: Improve compatibility with games that do GS SIGNAL/LABEL/FINISH 2020-12-24 09:03:45 +00:00
Akash a9b63a2106 PCSX2-GS: Use interrupt mask register bitfields
Previously, the code used a lot of "bitwise AND" to get specific bitfields of the interrupt mask control register, which makes the code look a bit hacky, also it's even more hard for normal people to calculate the value when hexadecimal values are used for the bitwise operations where the register is totally binary. Instead of dealing with all those mess, let's just get the bitfield values from the already implemented nice union of the IMR register. FWIW it also makes the code more readable.
2016-12-01 16:32:27 +05:30
Gregory Hainaut 4796803c33 pcsx2: Remove == true/false for boolean logic (#1556)
As discussed in #1553

Clang Tidy reports goes from 156 to 9.

Remain some macro in spu2x + a deadcode line
2016-09-10 20:08:14 +02:00
Gregory Hainaut 3a9bd90a3b Gif: port code to std::atomic 2016-02-28 15:29:31 +01:00
refractionpcsx2 68de5228a8 GIF Unit: Stop multiple fires of FINISH IRQ's
- Fixes Indiecar Series 2005.
- Savestate bump was required, sorry, not sorry :P
2015-08-12 02:16:23 +01:00