diff --git a/pcsx2/SaveState.h b/pcsx2/SaveState.h
index 9123a2be72..b24870cef8 100644
--- a/pcsx2/SaveState.h
+++ b/pcsx2/SaveState.h
@@ -26,7 +26,7 @@ enum class FreezeAction
 // [SAVEVERSION+]
 // This informs the auto updater that the users savestates will be invalidated.
 
-static const u32 g_SaveVersion = (0x9A58 << 16) | 0x0000;
+static const u32 g_SaveVersion = (0x9A59 << 16) | 0x0000;
 
 
 // the freezing data between submodules and core
diff --git a/pcsx2/VU.h b/pcsx2/VU.h
index da8c71719f..dc39935cd6 100644
--- a/pcsx2/VU.h
+++ b/pcsx2/VU.h
@@ -81,7 +81,7 @@ struct fdivPipe
 {
 	int enable;
 	REG_VI reg;
-	u32 sCycle;
+	u64 sCycle;
 	u32 Cycle;
 	u32 statusflag;
 };
@@ -90,7 +90,7 @@ struct efuPipe
 {
 	int enable;
 	REG_VI reg;
-	u32 sCycle;
+	u64 sCycle;
 	u32 Cycle;
 };
 
@@ -101,7 +101,7 @@ struct fmacPipe
 	int flagreg;
 	u32 xyzwupper;
 	u32 xyzwlower;
-	u32 sCycle;
+	u64 sCycle;
 	u32 Cycle;
 	u32 macflag;
 	u32 statusflag;
@@ -111,7 +111,7 @@ struct fmacPipe
 struct ialuPipe
 {
 	int reg;
-	u32 sCycle;
+	u64 sCycle;
 	u32 Cycle;
 };
 
diff --git a/pcsx2/VU0microInterp.cpp b/pcsx2/VU0microInterp.cpp
index 1cf5e77b8e..9b7502802c 100644
--- a/pcsx2/VU0microInterp.cpp
+++ b/pcsx2/VU0microInterp.cpp
@@ -64,7 +64,7 @@ static void _vu0Exec(VURegs* VU)
 	VU->code = ptr[1];
 	VU0regs_UPPER_OPCODE[VU->code & 0x3f](&uregs);
 
-	u32 cyclesBeforeOp = VU0.cycle - 1;
+	u64 cyclesBeforeOp = VU0.cycle - 1;
 
 	_vuTestUpperStalls(VU, &uregs);
 
@@ -252,7 +252,7 @@ void InterpVU0::Execute(u32 cycles)
 
 	VU0.VI[REG_TPC].UL <<= 3;
 	VU0.flags &= ~VUFLAG_MFLAGSET;
-	u32 startcycles = VU0.cycle;
+	u64 startcycles = VU0.cycle;
 	while ((VU0.cycle - startcycles) < cycles)
 	{
 		if (!(VU0.VI[REG_VPU_STAT].UL & 0x1))
@@ -274,7 +274,7 @@ void InterpVU0::Execute(u32 cycles)
 
 	if (EmuConfig.Speedhacks.EECycleRate != 0 && (!EmuConfig.Gamefixes.VUSyncHack || EmuConfig.Speedhacks.EECycleRate < 0))
 	{
-		u32 cycle_change = VU0.cycle - startcycles;
+		u64 cycle_change = VU0.cycle - startcycles;
 		VU0.cycle -= cycle_change;
 		switch (std::min(static_cast<int>(EmuConfig.Speedhacks.EECycleRate), static_cast<int>(cycle_change)))
 		{
diff --git a/pcsx2/VU1micro.cpp b/pcsx2/VU1micro.cpp
index e6b413214d..9e969d5e76 100644
--- a/pcsx2/VU1micro.cpp
+++ b/pcsx2/VU1micro.cpp
@@ -31,7 +31,7 @@ void vu1Finish(bool add_cycles) {
 		vu1Thread.Get_MTVUChanges();
 		return;
 	}
-	u32 vu1cycles = VU1.cycle;
+	u64 vu1cycles = VU1.cycle;
 	if(VU0.VI[REG_VPU_STAT].UL & 0x100) {
 		VUM_LOG("vu1ExecMicro > Stalling until current microprogram finishes");
 		CpuVU1->Execute(vu1RunCycles);
diff --git a/pcsx2/VU1microInterp.cpp b/pcsx2/VU1microInterp.cpp
index d7b22f66b2..fde3451226 100644
--- a/pcsx2/VU1microInterp.cpp
+++ b/pcsx2/VU1microInterp.cpp
@@ -261,7 +261,7 @@ void InterpVU1::Execute(u32 cycles)
 	const FPControlRegisterBackup fpcr_backup(EmuConfig.Cpu.VU1FPCR);
 
 	VU1.VI[REG_TPC].UL <<= 3;
-	u32 startcycles = VU1.cycle;
+	u64 startcycles = VU1.cycle;
 
 	while ((VU1.cycle - startcycles) < cycles)
 	{
diff --git a/pcsx2/VUmicro.cpp b/pcsx2/VUmicro.cpp
index cd8b9f4221..66b2c6320b 100644
--- a/pcsx2/VUmicro.cpp
+++ b/pcsx2/VUmicro.cpp
@@ -51,7 +51,7 @@ void BaseVUmicroCPU::ExecuteBlock(bool startUp)
 	}
 	else // Continue Executing
 	{
-		u32 cycle = m_Idx ? VU1.cycle : VU0.cycle;
+		u64 cycle = m_Idx ? VU1.cycle : VU0.cycle;
 		s32 delta = (s32)(u32)(cpuRegs.cycle - cycle);
 
 		if (delta > 0)
@@ -70,7 +70,7 @@ void BaseVUmicroCPU::ExecuteBlockJIT(BaseVUmicroCPU* cpu, bool interlocked)
 
 	if (stat & test)
 	{ // VU is running
-		s32 delta = (s32)(u32)(cpuRegs.cycle - VU0.cycle);
+		s64 delta = (s64)(u64)(cpuRegs.cycle - VU0.cycle);
 
 		if (delta > 0)
 		{
diff --git a/pcsx2/VUops.cpp b/pcsx2/VUops.cpp
index 7c0aa9e6a8..22046df621 100644
--- a/pcsx2/VUops.cpp
+++ b/pcsx2/VUops.cpp
@@ -221,7 +221,7 @@ static void _vuFMACTestStall(VURegs* VU, u32 reg, u32 xyzw)
 		if ((VU->fmac[currentpipe].regupper == reg && VU->fmac[currentpipe].xyzwupper & xyzw)
 			|| (VU->fmac[currentpipe].reglower == reg && VU->fmac[currentpipe].xyzwlower & xyzw))
 		{
-			u32 newCycle = VU->fmac[currentpipe].Cycle + VU->fmac[currentpipe].sCycle;
+			u64 newCycle = VU->fmac[currentpipe].Cycle + VU->fmac[currentpipe].sCycle;
 
 			VUM_LOG("FMAC[%d] stall %d", currentpipe, newCycle - VU->cycle);
 			if (newCycle > VU->cycle)
@@ -248,7 +248,7 @@ static __fi void _vuTestFDIVStalls(VURegs* VU, _VURegsNum* VUregsn)
 
 	if (VU->fdiv.enable != 0)
 	{
-		u32 newCycle = VU->fdiv.Cycle + VU->fdiv.sCycle;
+		u64 newCycle = VU->fdiv.Cycle + VU->fdiv.sCycle;
 		VUM_LOG("waiting FDIV pipe %d", newCycle - VU->cycle);
 		if (newCycle > VU->cycle)
 			VU->cycle = newCycle;
@@ -268,7 +268,7 @@ static __fi void _vuTestEFUStalls(VURegs* VU, _VURegsNum* VUregsn)
 	// than WAITP, we're going to overwrite the value in the pipeline, which will break everything.
 	// So the TL;DR of this is that we should be safe to release 1 cycle early and write back P
 	VU->efu.Cycle -= 1;
-	u32 newCycle = VU->efu.sCycle + VU->efu.Cycle;
+	u64 newCycle = VU->efu.sCycle + VU->efu.Cycle;
 
 	VUM_LOG("waiting EFU pipe %d", newCycle - VU->cycle);
 	if (newCycle > VU->cycle)
@@ -286,7 +286,7 @@ static __fi void _vuTestALUStalls(VURegs* VU, _VURegsNum* VUregsn)
 
 		if (VU->ialu[currentpipe].reg & VUregsn->VIread) // Read and written VI regs share the same register
 		{
-			u32 newCycle = VU->ialu[currentpipe].Cycle + VU->ialu[currentpipe].sCycle;
+			u64 newCycle = VU->ialu[currentpipe].Cycle + VU->ialu[currentpipe].sCycle;
 
 			VUM_LOG("ALU[%d] stall %d", currentpipe, newCycle - VU->cycle);
 			if (newCycle > VU->cycle)
diff --git a/pcsx2/Vif0_Dma.cpp b/pcsx2/Vif0_Dma.cpp
index 865679dfeb..fd7e7f0d36 100644
--- a/pcsx2/Vif0_Dma.cpp
+++ b/pcsx2/Vif0_Dma.cpp
@@ -126,7 +126,7 @@ __fi void vif0VUFinish()
 	// Sync up VU0 so we don't errantly wait.
 	while (VU0.VI[REG_VPU_STAT].UL & 0x1)
 	{
-		const int cycle_diff = static_cast<int>(cpuRegs.cycle - VU0.cycle);
+		const s64 cycle_diff = static_cast<int>(cpuRegs.cycle - VU0.cycle);
 
 		if ((EmuConfig.Gamefixes.VUSyncHack && cycle_diff < VU0.nextBlockCycles) || cycle_diff <= 0)
 			break;
@@ -143,7 +143,7 @@ __fi void vif0VUFinish()
 
 	if ((VU0.VI[REG_VPU_STAT].UL & 1))
 	{
-		int _cycles = VU0.cycle;
+		s64 _cycles = VU0.cycle;
 		//DevCon.Warning("Finishing VU0");
 		vu0Finish();
 		_cycles = VU0.cycle - _cycles;
diff --git a/pcsx2/Vif1_Dma.cpp b/pcsx2/Vif1_Dma.cpp
index 664688864f..c85af24247 100644
--- a/pcsx2/Vif1_Dma.cpp
+++ b/pcsx2/Vif1_Dma.cpp
@@ -222,7 +222,7 @@ __fi void vif1VUFinish()
 	// Sync up VU1 so we don't errantly wait.
 	while (!THREAD_VU1 && (VU0.VI[REG_VPU_STAT].UL & 0x100))
 	{
-		const int cycle_diff = static_cast<int>(cpuRegs.cycle - VU1.cycle);
+		const s64 cycle_diff = static_cast<int>(cpuRegs.cycle - VU1.cycle);
 
 		if ((EmuConfig.Gamefixes.VUSyncHack && cycle_diff < VU1.nextBlockCycles) || cycle_diff <= 0)
 			break;
@@ -244,7 +244,7 @@ __fi void vif1VUFinish()
 
 	if (VU0.VI[REG_VPU_STAT].UL & 0x100)
 	{
-		u32 _cycles = VU1.cycle;
+		u64 _cycles = VU1.cycle;
 		//DevCon.Warning("Finishing VU1");
 		vu1Finish(false);
 		if (THREAD_VU1 && !INSTANT_VU1 && (VU0.VI[REG_VPU_STAT].UL & 0x100))
diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl
index b5477f75ff..a0f55101ed 100644
--- a/pcsx2/x86/microVU_Lower.inl
+++ b/pcsx2/x86/microVU_Lower.inl
@@ -1857,7 +1857,7 @@ mVUop(mVU_XGKICK)
 			xMOV(ptr32[&VU1.xgkickcyclecount], 0);
 			xMOV(gprT2, ptr32[&mVU.totalCycles]);
 			xSUB(gprT2, ptr32[&mVU.cycles]);
-			xADD(gprT2, ptr32[&VU1.cycle]);
+			xADD(gprT2, ptr64[&VU1.cycle]);
 			xMOV(ptr32[&VU1.xgkicklastcycle], gprT2);
 			xMOV(gprT1, regS);
 			xAND(gprT1, 0x3FF);