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Fix FPU.cpp: run the EE divide unit's digits instead of rounding a quotient
DIV.S, SQRT.S and RSQRT.S applied a partial truncation law and fell through to a correctly rounded host divide, which left every operand the law did not reach one ULP away from the console. The unit is not a rounding rule at all: it is a radix-2 SRT digit recurrence, so eeDivide() and eeSqrtBits() now run the digits. What that recurrence is, and what it was measured against, is at eeSrtDigit(). The recurrence is not ours: it is PS2Float.cpp's Div() and Sqrt() from GitHubProUser67's proposed PCSX2 soft-float series, carried and since revised in the pcsx2-reliquary fork, whose only documentation is a DOI. The three ops are integer now, so ScopedDivRoundMode and eeISqrt48 go with them and FPUDivFPCR's rounding mode no longer reaches the interpreter. The divide-unit tests move with it. They were written around a model with a residue: the two tripwires are enabled, the console tables assert the console on every cell, and the engine differentials now pin the shape of the one-ULP divergence that is left rather than the region the old law settled.
This commit is contained in:
pstef
+172
-229
@@ -418,181 +418,186 @@ static u32 eeGuardedAddSub(u32 a, u32 b, bool issub)
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return eeRoundToSingle(eeToDouble(a) + eeToDouble(b), true);
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}
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/* Divide two EE singles with exactly one rounding.
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/* The EE's divide/square-root unit, digit by digit.
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Not through eeToDouble(), the way the adder and the multiplier go: their
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results are exact in a double and a quotient is not, so widening and then
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narrowing rounds twice. Chopping would forgive that, but the divide unit
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rounds to nearest (FPUDivFPCR, scoped in by the callers), where the second
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rounding can land a ULP away.
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It is not a correctly rounding divider, and no rounding mode makes it one.
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The exact quotient lies between two singles and silicon returns one of them,
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but which one is decided by where a digit recurrence lands, not by how far the
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exact value sits from either end. So the error reaches nearly a whole ULP in
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both directions on the same divisor, and two operand pairs agreeing in every
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coordinate a rounding rule can see -- branch, divisor, remainder, the exact
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fraction -- can still go opposite ways.
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So rescale instead of widening. Both operands are forced to exponent 127, so
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the division happens between two significands in [1,2) where nothing can
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overflow or underflow and the host performs the EE's single rounding; the
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exponents are added back onto the quotient afterwards. Scaling by a power of
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two leaves a significand alone, so the quotient's significand and its
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rounding do not depend on where the operands sat in the range -- only the
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reassembled exponent does, and that is integer arithmetic.
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It is a radix-2 SRT digit recurrence over the signed digit set {-1, 0, +1},
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partial remainder carried in redundant carry-save form, 24 selections
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producing 25 digits, and no rounding step anywhere in it: no round bit, no
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sticky, no final correction. SQRT.S is the same recurrence with the root so
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far fed back in place of the divisor, and RSQRT.S is SQRT.S followed by DIV.S
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with an ordinary 24-bit single in between, which is what silicon does.
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The divisor must already be known nonzero: a zero divisor is a flag question
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the callers answer first.
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The model is the selection function eeSrtDigit() below.
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The console does not round to nearest; eeDivideTruncates() below covers the
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part of the difference that is settled.
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* DIV.S -- 150,994,944 rows. Eighteen divisors swept exhaustively, every
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one of the 2^23 numerator significands at each, both branches, including
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the seven degenerate divisors that broke every earlier frame. Zero
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result-word disagreements, and zero rows where the recurrence lands
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outside {T, T+1}. Through the same scorer, truncation gets 52,434,906 of
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those rows wrong and round-to-nearest 29,430,553.
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* SQRT.S -- 16,777,216 rows, every significand at both exponent parities.
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Zero disagreements; truncation 3,994,228 and round-to-nearest 4,395,034.
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* A 3000-operand holdout (seed 0x243F6A88, captured before any of this was
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modelled): 2000 div and 1000 sqrt, zero disagreements. 229 of the div
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rows saturate or flush, which the exhaustive sweeps cannot see: they hold
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both exponents at 127.
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Nothing else moves the result. FCR31 has no rounding-mode field on this FPU
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-- bit 0 reads 1 whatever is written and bit 1 never sticks -- and the answer
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is unchanged when the preceding instruction is varied or the case list
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reversed. What that leaves EmuConfig.Cpu.FPUDivFPCR to do is in the block
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below eeSqrtBits().
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This is PS2Float.cpp's Div() and Sqrt() from the proposed PCSX2 soft-float
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series (GitHubProUser67), whose only documentation is M. Prabhu and
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G. Zyner, "167 MHz radix-8 divide and square root using overlapped
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radix-2 stages", DOI 10.1109/ARITH.1995.465363.
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*/
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/* The EE divider's truncation law.
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The divide/square-root unit is not correctly rounded: the exact quotient
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lies between two singles and the unit returns one of them, not always the
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nearer, and which one it returns depends on the operands rather than on a
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rounding mode. This is the part of that choice the captures settle.
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Write the exact division of the two significands (hidden bit restored) as
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lt = ma < mb the branch: does the quotient need a shift
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num = ma << (23 + lt)
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T = num / mb the truncated 24-bit significand
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rem = num - T*mb 0 <= rem < mb
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u = mb - rem how far the exact quotient sits below T+1
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so the unit returns T or T+1 and correct rounding would take T+1 exactly
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when 2*rem >= mb. The unit rounds up only when u is small:
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u > cap => the unit truncates cap = 2^22 on A>=B
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cap = max(2^23, mb-2^22) on A<B
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Evidence, all of it first-party captures from SCPH-90000 (FCR0 0x2E40) in
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captures/fpmatrix/divsqrt/ in the session archive:
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* 150,994,944 rows over eighteen divisors swept exhaustively -- every one
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of the 2^23 numerator significands at each -- of which 57,612,965 have
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u > cap. Not one of them rounds up.
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* 48,799,468 further rows of scattered, band and transverse captures:
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6,937,248 distinct divisor significands, divisor exponent fields 110
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through 145. Again not one violation.
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Rows with u <= cap are unsettled -- 27.5% of them truncate as well, and no
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model this project has built predicts which -- so they keep the correctly
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rounded answer, which is also what both recompilers produce. The implication
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runs one way, so applying the law can only turn a wrong row right.
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Only the A>=B half of the cap ever changes a result: on A<B, u > cap already
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implies correct rounding truncates. The branch is kept because it is the law
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the captures give, and
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EeFpuDivUnitExhaustive.TheAlbHalfOfTheCapCannotChangeAnAnswer holds its
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shape so a tightened cap cannot silently become live.
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Over the exhaustive set this takes the interpreter from 19.49% of quotients
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off by a ULP to 15.44%, and over the scattered set from 13.98% to 9.51%, at
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the price of disagreeing with both recompilers on those rows.
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EeRecFpuDivUnitRounding pins the divergence to this class.
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*/
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static bool eeDivideTruncates(u32 mb, u32 lt, u32 rem)
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/* The partial remainder, in the redundant form the recurrence carries it in.
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No step propagates a carry across the width of the operand, which is why the
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selector below cannot see the true remainder. */
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struct EeSrtRemainder
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{
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const u32 cap = lt ? ((mb > (3u << 22)) ? mb - (1u << 22) : (1u << 23)) : (1u << 22);
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return (mb - rem) > cap;
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u32 sum, carry;
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};
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static __fi EeSrtRemainder eeSrtCarrySave(u32 a, u32 b, u32 c)
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{
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const u32 u = a ^ b;
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const u32 h = (a & b) | (u & c);
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return {u ^ c, h << 1};
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}
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/* The selection function: which of -1, 0, +1 the next digit takes.
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It assimilates the redundant remainder only partially -- the carry word is
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added in above bit 23 while the low 24 bits of the sum are OR-ed back rather
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than added -- so it decides on something other than the remainder, and picks a
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different digit from the one an exact comparison would. The thresholds are
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+2^23 and -2^24, with the binary point between bits 24 and 25; that asymmetry
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is what biases the unit toward truncation. The digit set is redundant, so the
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last digit can still be -1 and the result reach T+1 on rows a truncation could
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never reach. */
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static __fi s32 eeSrtDigit(EeSrtRemainder r)
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{
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constexpr u32 mask = (1u << 24) - 1u;
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const s32 estimate = (s32)(((r.sum & ~mask) + r.carry) | (r.sum & mask));
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return (estimate >= (1 << 23)) - (estimate < (s32)(~0u << 24));
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}
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/* On a zero digit the next digit is selected from the un-recompressed pair
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while the state advances with the recompressed one, so selection and state
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see different splittings of the same value. Drop the distinction and the
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model stops reproducing silicon. */
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static __fi EeSrtRemainder eeSrtSelect(EeSrtRemainder cur, EeSrtRemainder next, s32 digit)
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{
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const u32 m = 0u - (u32)(digit != 0);
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return {(cur.sum & ~m) | (next.sum & m), (cur.carry & ~m) | (next.carry & m)};
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}
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/* The quotient of two 24-bit significands as 25 digits, weights 2^24 down to
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2^0. A positive digit subtracts the divisor as ~divisor with the +1 fed into
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the carry word, which the selector then sees -- that is one of the places
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the estimate and the state come apart. The value returned is 25 bits when
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sma >= smb and 24 bits when it is not; the caller normalises, and the digit
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that falls off the bottom there is simply dropped. */
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static u32 eeDivideSignificand(u32 sma, u32 smb)
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{
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const u32 divisor = smb << 2;
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EeSrtRemainder rem = {sma << 2, 0};
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u32 quotient = 0;
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s32 digit = 1;
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for (int i = 0; i < 24; ++i)
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{
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quotient = (quotient << 1) + (u32)digit;
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const u32 addend = (digit > 0) ? ~divisor : ((digit < 0) ? divisor : 0u);
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rem.carry += (u32)(digit > 0);
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const EeSrtRemainder next = eeSrtCarrySave(rem.sum, rem.carry, addend);
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digit = eeSrtDigit(eeSrtSelect(rem, next, digit));
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rem.sum = next.sum << 1;
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rem.carry = next.carry << 1;
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}
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return (quotient << 1) + (u32)digit;
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}
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static u32 eeDivide(u32 a, u32 b)
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{
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const s32 ea = (s32)((a >> 23) & 0xFF);
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const s32 eb = (s32)((b >> 23) & 0xFF);
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const u32 sign = (a ^ b) & 0x80000000u;
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if (ea == 0)
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return (a ^ b) & 0x80000000; // zero dividend, sign from both operands
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return sign; // zero dividend (denormals are zero), sign from both operands
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// The exact frame, in integers, so the decision below owes nothing to the
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// host's rounding mode. Exponent 255 is an ordinary binade on this FPU, so
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// every finite operand reaches here and the hidden bit is always present.
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// Exponent 255 is an ordinary binade on this FPU, so every finite operand
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// reaches here and the hidden bit is always present. The divisor is already
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// known nonzero: that is a flag question the callers answer first.
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u32 quotient = eeDivideSignificand(0x800000u | (a & 0x7FFFFFu), 0x800000u | (b & 0x7FFFFFu));
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s32 e = ea - eb + 126;
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if (quotient >= (1u << 24))
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{
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const u32 sma = 0x800000u | (a & 0x7FFFFFu);
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const u32 smb = 0x800000u | (b & 0x7FFFFFu);
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const u32 lt = (sma < smb) ? 1u : 0u;
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const u64 num = (u64)sma << (23 + lt);
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const u32 T = (u32)(num / smb);
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const u32 rem = (u32)(num - (u64)T * smb);
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if (eeDivideTruncates(smb, lt, rem))
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{
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// T is already normalised into [2^23, 2^24), so nothing carries out
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// of the significand and the exponent is pure integer. A quotient
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// that only reaches the next binade by rounding up therefore does
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// not reach it here, as on the console.
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const s32 e = ea - eb + 127 - (s32)lt;
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const u32 sign = (a ^ b) & 0x80000000u;
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if (e > 255)
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return sign | 0x7FFFFFFFu; // the EE's maximum, not FLT_MAX
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if (e < 1)
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return sign; // the EE has no denormals to underflow into
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return sign | ((u32)e << 23) | (T - 0x800000u);
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}
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quotient >>= 1;
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++e;
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}
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FPRreg ma, mb, q;
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ma.UL = (a & 0x807FFFFFu) | (127u << 23);
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mb.UL = (b & 0x807FFFFFu) | (127u << 23);
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q.f = ma.f / mb.f;
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// |q| is in (0.5, 2], so its exponent field carries 126, 127 or -- if the
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// rounding pushed it to exactly 2.0 -- 128.
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const s32 e = (s32)((q.UL >> 23) & 0xFF) + ea - eb;
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// No carry out of the significand is possible below this point -- there is
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// no rounding step left that could walk the quotient into the next binade.
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if (e > 255)
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return (q.UL & 0x80000000u) | 0x7FFFFFFFu;
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return sign | 0x7FFFFFFFu; // the EE's maximum, not FLT_MAX
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if (e < 1)
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return q.UL & 0x80000000u; // the EE has no denormals to underflow into
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return (q.UL & 0x807FFFFFu) | ((u32)e << 23);
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}
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/* floor(sqrt(x)) for x < 2^48, exactly. The host sqrt only seeds it: x is
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under 53 bits, so it converts to a double without loss and lands within one
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of the answer, and the fixup loops run unconditionally, so the result does
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not depend on the host's rounding mode. */
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static u32 eeISqrt48(u64 x)
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{
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u64 r = (u64)std::sqrt((double)x);
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while (r > 0 && r * r > x)
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--r;
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while ((r + 1) * (r + 1) <= x)
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++r;
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return (u32)r;
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return sign; // the EE has no denormals to underflow into
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return sign | ((u32)e << 23) | (quotient & 0x7FFFFFu);
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}
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/* sqrt(|Ft|) as EE bits, including the top binade.
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Integer, for the same reason eeDivide is: the square-root unit is the divide
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unit, and it misses the correctly rounded answer under the same law.
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The same recurrence as eeDivideSignificand(), with the root so far fed back
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in place of a fixed divisor: adding digit d at weight w to the root adds
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d*(2*root + d*w) to its square, which is what has to leave the partial
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remainder, so the addend is rebuilt each step instead of being a constant.
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Everything else -- the carry-save state, the selector, the zero-digit quirk,
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the absence of any rounding step -- is shared, and so is the evidence: see
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the block comment above eeSrtDigit().
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Put the operand's significand where the root is a 24-bit integer. With E the
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exponent field and m the significand with its hidden bit,
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The radicand is placed so the root is a 24-bit integer. With E the exponent
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field, the significand's hidden bit restored, and the result's exponent
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(E + 127) / 2 rounded down, the operand's own exponent parity decides how far
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to shift: one place when E is odd, two when it is even. The top binade needs
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no special case: in integers it is just another odd E.
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*/
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static u32 eeSqrtSignificand(u32 m)
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{
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EeSrtRemainder rem = {m, 0};
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u32 root = 0;
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s32 digit = 1;
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k = 23 if E is odd, 24 if E is even (|Ft| = X * 2^(E-150-k))
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X = m << k 2^46 <= X < 2^48
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R = floor(sqrt(X)) 2^23 <= R < 2^24
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rem = X - R*R, u = (R+1)^2 - X = 2R+1-rem
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for (int i = 0; i < 24; ++i)
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{
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const u32 addend_base = root + ((u32)digit << (24 - i));
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root += (u32)digit << (25 - i);
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const u32 addend = (digit > 0) ? ~addend_base : ((digit < 0) ? addend_base : 0u);
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rem.carry += (u32)(digit > 0);
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const EeSrtRemainder next = eeSrtCarrySave(rem.sum, rem.carry, addend);
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digit = eeSrtDigit(eeSrtSelect(rem, next, digit));
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rem.sum = next.sum << 1;
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rem.carry = next.carry << 1;
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}
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// The last digit carries weight 2^1, below the root's least significant
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// bit, so it only reaches the result by borrowing out of it.
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root += (u32)digit << 1;
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return (root >> 2) & 0xFFFFFFu;
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}
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so the unit returns R or R+1, correct rounding takes R+1 exactly when
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X > (R+0.5)^2 -- i.e. rem > R, with no ties possible since (R+0.5)^2 is
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never an integer -- and E-150-k is even by construction, so the result's
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exponent field 150 + (E-150-k)/2 is exact integer arithmetic.
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The truncation law is the one eeDivideTruncates() applies, with the constant
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that goes with it:
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u > 2^23 => the unit truncates
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2^23 is half of sqrt's minimum span 2R+1 >= 2^24 + 1, as 2^22 is half of
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div's minimum span mb >= 2^23. Measured by
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captures/fpmatrix/divsqrt/scatter/sqgain.c over the two exhaustive console
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sweeps (16,777,216 rows, every significand at both exponent parities,
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SCPH-90000, FCR0 0x2E40):
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* 10,845,747 rows have u > 2^23. Not one of them rounds up.
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* An odd-exponent row rounds up at u = 2^23 exactly, so the bound is
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attained.
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It takes sqrt from 26.20% of roots off by a ULP to 11.55%. The rest is the
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same unsolved region as div's, and keeps the correctly rounded answer. */
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static u32 eeSqrtBits(u32 t)
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{
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const u32 E = (t >> 23) & 0xFFu;
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@@ -601,78 +606,21 @@ static u32 eeSqrtBits(u32 t)
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// do both recompilers (they take |Ft| first). See
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// EeRecFpu.SqrtSOfNegativeZeroIsPositiveZero.
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const int k = (E & 1u) ? 23 : 24;
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const u64 X = (u64)(0x800000u | (t & 0x7FFFFFu)) << k;
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const u32 R = eeISqrt48(X);
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const u64 rem = X - (u64)R * R;
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const u32 u = (u32)(2ull * R + 1ull - rem);
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// The mode the divide unit runs in, honoured here rather than through the
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// host FPCR because this arithmetic is integer. sqrt's result is always
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// positive, so toward-negative-infinity is the same as toward zero and
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// toward-positive-infinity is "up whenever the root is inexact". The
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// truncation law sits on top: it can only take the increment away, so under
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// toward-positive-infinity it suppresses a round-up the mode asked for.
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// That is deliberate -- the law is what the console does, the non-nearest
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// modes are a compatibility knob for behaviour it does not have. All four
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// modes are pinned by
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// EeRecFpuDivUnitRounding.SqrtSHonoursEveryDivideUnitRoundingMode.
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bool round_up;
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switch (EmuConfig.Cpu.FPUDivFPCR.GetRoundMode())
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{
|
||||
case FPRoundMode::Nearest: round_up = rem > (u64)R; break;
|
||||
case FPRoundMode::PositiveInfinity: round_up = rem != 0; break;
|
||||
default: round_up = false; break;
|
||||
}
|
||||
|
||||
u32 sig = (round_up && u <= (1u << 23)) ? R + 1u : R;
|
||||
s32 e = 150 + (((s32)E - 150 - k) / 2); // the numerator is always even
|
||||
if (sig == 0x1000000u) // rounded out of the binade
|
||||
{
|
||||
sig = 0x800000u;
|
||||
++e;
|
||||
}
|
||||
return ((u32)e << 23) | (sig - 0x800000u);
|
||||
const u32 m = (0x800000u | (t & 0x7FFFFFu)) << ((E & 1u) ? 1 : 2);
|
||||
return (((E + 127u) >> 1) << 23) | (eeSqrtSignificand(m) & 0x7FFFFFu);
|
||||
}
|
||||
|
||||
/* The EE's divide/square-root unit rounds to nearest even when the rest of the
|
||||
FPU is chopping toward zero, which is why PCSX2 carries a second control
|
||||
register, FPUDivFPCR, whose only difference from FPUFPCR is the rounding
|
||||
mode. Both recompilers swap the host rounding mode around DIV/SQRT/RSQRT
|
||||
/* Nothing in the interpreter swaps EmuConfig.Cpu.FPUDivFPCR into the host FPCR
|
||||
any more: DIV.S, SQRT.S and RSQRT.S are integer arithmetic now, and no
|
||||
rounding mode reaches a digit recurrence. That register is PCSX2's surrogate
|
||||
for the divide unit rounding to nearest while the rest of the FPU chops, and
|
||||
both recompilers still swap it in, because they run these ops on host singles
|
||||
(arm64 recDIV_S_xmm / recSQRT_S_xmm / recRSQRT_S_xmm in iFPU-arm64.cpp and
|
||||
the DOUBLE:: twins in iFPUd-arm64.cpp; x86 iFPU.cpp / iFPUd.cpp do the same
|
||||
with xLDMXCSR). The interpreter never did, so those three ops came out one
|
||||
ULP low against both recompilers and the console whenever a game is in the
|
||||
default chop mode.
|
||||
|
||||
Gated the way the emitters gate it: where the two registers already agree
|
||||
there is nothing to swap.
|
||||
the DOUBLE:: twins in iFPUd-arm64.cpp; x86 iFPU.cpp / iFPUd.cpp with
|
||||
xLDMXCSR): 1.0 rsqrt 1.5 is 0x3F5105EB on the console and 0x3F5105EC without
|
||||
the swap. So the two engines part company on every operand silicon is not
|
||||
correctly rounded on, which EeRecFpuDivUnitRounding and EeRecFpuRsqrt pin.
|
||||
*/
|
||||
class ScopedDivRoundMode
|
||||
{
|
||||
public:
|
||||
__fi ScopedDivRoundMode()
|
||||
: m_swap(EmuConfig.Cpu.FPUFPCR.bitmask != EmuConfig.Cpu.FPUDivFPCR.bitmask)
|
||||
{
|
||||
if (m_swap)
|
||||
{
|
||||
m_prev = FPControlRegister::GetCurrent();
|
||||
FPControlRegister::SetCurrent(EmuConfig.Cpu.FPUDivFPCR);
|
||||
}
|
||||
}
|
||||
__fi ~ScopedDivRoundMode()
|
||||
{
|
||||
if (m_swap)
|
||||
FPControlRegister::SetCurrent(m_prev);
|
||||
}
|
||||
|
||||
ScopedDivRoundMode(const ScopedDivRoundMode&) = delete;
|
||||
ScopedDivRoundMode& operator=(const ScopedDivRoundMode&) = delete;
|
||||
|
||||
private:
|
||||
FPControlRegister m_prev;
|
||||
bool m_swap;
|
||||
};
|
||||
|
||||
void ABS_S() {
|
||||
_FdValUl_ = _FsValUl_ & 0x7fffffff;
|
||||
@@ -754,7 +702,6 @@ void CVT_W() {
|
||||
}
|
||||
|
||||
void DIV_S() {
|
||||
const ScopedDivRoundMode div_round;
|
||||
if (checkDivideByZero( _FdValUl_, _FtValUl_, _FsValUl_, FPUflagD | FPUflagSD, FPUflagI | FPUflagSI)) return;
|
||||
_FdValUl_ = eeDivide( _FsValUl_, _FtValUl_ );
|
||||
}
|
||||
@@ -1043,7 +990,6 @@ void NEG_S() {
|
||||
}
|
||||
|
||||
void RSQRT_S() {
|
||||
const ScopedDivRoundMode div_round;
|
||||
clearFPUFlags(FPUflagD | FPUflagI);
|
||||
|
||||
if ( ( _FtValUl_ & 0x7F800000 ) == 0 ) { // Ft is zero (Denormals are Zero)
|
||||
@@ -1066,23 +1012,20 @@ void RSQRT_S() {
|
||||
// gives 0x3F5105EB.
|
||||
//
|
||||
|
||||
// Neither operand is clamped any more, and it has to be both: with the clamp
|
||||
// left on the sqrt alone, rsqrt(2^128, 2^128) came out right only because
|
||||
// the two clamps cancelled. Unclamping both fixed that row and 13 others,
|
||||
// taking RSQRT.S from 17/32 to 31/32 against the console.
|
||||
// Neither operand is clamped any more, which is all-or-nothing by design:
|
||||
// unclamping only the sqrt used to break rsqrt(2^128, 2^128), which came out
|
||||
// right solely because its two clamps cancelled. Unclamping both fixes that
|
||||
// row and 13 others. Scored against the console over the corpus, RSQRT.S
|
||||
// went 17/32 to 31/32.
|
||||
//
|
||||
// rsqrt(EEMAX, EEMAX) is still 1 ULP out, and it is not the two-step
|
||||
// rounding it was filed as: silicon composes the two steps exactly as
|
||||
// below, with a plain 24-bit single in between, and it is the divide/
|
||||
// square-root unit itself that is not correctly rounded. This computes the
|
||||
// correctly-rounded answer; ee_fpu_divunit_console_tests.cpp has the
|
||||
// capture and how far silicon sits from it.
|
||||
// The composition itself comes from a dedicated console capture: 2231
|
||||
// operand pairs over two probes, each pair run as sqrt.s, rsqrt.s and
|
||||
// div.s, and rsqrt.s equals div.s(Fs, sqrt.s(Ft)) on every row, with a
|
||||
// plain 24-bit single in between. See ee_fpu_divunit_console_tests.cpp.
|
||||
_FdValUl_ = eeDivide( _FsValUl_, eeSqrtBits( _FtValUl_ ) );
|
||||
}
|
||||
|
||||
void SQRT_S() {
|
||||
// No ScopedDivRoundMode: eeSqrtBits() reads FPUDivFPCR's rounding mode
|
||||
// itself. DIV.S and RSQRT.S still need it for eeDivide()'s host division.
|
||||
clearFPUFlags(FPUflagI | FPUflagD);
|
||||
|
||||
// Invalid-operation keys off the SIGN BIT ALONE. -0 and the negative
|
||||
|
||||
Reference in New Issue
Block a user