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https://github.com/ARMSX2/ARMSX2.git
synced 2026-08-24 16:50:16 -07:00
EE/FPU: read and write an FPR through an accessor
The slot is 64 bits and the architectural register is 32, so a word view of the union is only right while the two coincide. Word() and SetWord() replace f/UL/SL and are the identity, so nothing that runs changes; what it buys is that the compiler names every place that reads a slot as a word, which is the set the next commit has to relocate. The x86 tier is not built here and still reads the members directly.
This commit is contained in:
pstef
+66
-52
@@ -30,23 +30,23 @@
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#define _Fs_ ( ( cpuRegs.code >> 11 ) & 0x1F )
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#define _Fd_ ( ( cpuRegs.code >> 6 ) & 0x1F )
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// Floats
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#define _FtValf_ fpuRegs.fpr[ _Ft_ ].f
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#define _FsValf_ fpuRegs.fpr[ _Fs_ ].f
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#define _FdValf_ fpuRegs.fpr[ _Fd_ ].f
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#define _FAValf_ fpuRegs.ACC.f
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/* The word is never an lvalue here: a slot is wider than the word it holds
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(R5900.h), so reads go through the accessor and writes through a setter.
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*/
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// U32's
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#define _FtValUl_ fpuRegs.fpr[ _Ft_ ].UL
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#define _FsValUl_ fpuRegs.fpr[ _Fs_ ].UL
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#define _FdValUl_ fpuRegs.fpr[ _Fd_ ].UL
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#define _FAValUl_ fpuRegs.ACC.UL
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#define _FtValUl_ fpuRegs.fpr[ _Ft_ ].Word()
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#define _FsValUl_ fpuRegs.fpr[ _Fs_ ].Word()
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#define _FdValUl_ fpuRegs.fpr[ _Fd_ ].Word()
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#define _FAValUl_ fpuRegs.ACC.Word()
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// S32's - useful for ensuring sign extension when needed.
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#define _FtValSl_ fpuRegs.fpr[ _Ft_ ].SL
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#define _FsValSl_ fpuRegs.fpr[ _Fs_ ].SL
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#define _FdValSl_ fpuRegs.fpr[ _Fd_ ].SL
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#define _FAValSl_ fpuRegs.ACC.SL
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// S32 - useful for ensuring sign extension when needed.
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#define _FsValSl_ static_cast<s32>( _FsValUl_ )
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// Destination writes
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#define _SetFsVal_( w ) fpuRegs.fpr[ _Fs_ ].SetWord( w )
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#define _SetFdVal_( w ) fpuRegs.fpr[ _Fd_ ].SetWord( w )
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#define _SetFAVal_( w ) fpuRegs.ACC.SetWord( w )
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// FPU Control Reg (FCR31)
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#define _ContVal_ fpuRegs.fprc[ 31 ]
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@@ -64,6 +64,20 @@
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//****************************************************************
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static u32 floatToBits(float f)
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{
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u32 bits;
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std::memcpy(&bits, &f, sizeof(bits));
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return bits;
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}
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static float bitsToFloat(u32 bits)
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{
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float f;
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std::memcpy(&f, &bits, sizeof(f));
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return f;
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}
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/* The EE value of a raw FPR word, exactly, as a double.
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The only way an operand enters this file: every arithmetic op, every flag
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@@ -219,10 +233,9 @@ bool checkDivideByZero(u32& xReg, u32 yDivisorReg, u32 zDividendReg, u32 cFlagsT
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#ifdef comparePrecision
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// This compare discards the least-significant bit(s) in order to solve some rounding issues.
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#define C_cond_S(cond) { \
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FPRreg tempA, tempB; \
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tempA.UL = _FsValUl_ & comparePrecision; \
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tempB.UL = _FtValUl_ & comparePrecision; \
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_ContVal_ = ( ( tempA.f ) cond ( tempB.f ) ) ? \
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const float tempA = bitsToFloat( _FsValUl_ & comparePrecision ); \
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const float tempB = bitsToFloat( _FtValUl_ & comparePrecision ); \
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_ContVal_ = ( ( tempA ) cond ( tempB ) ) ? \
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( _ContVal_ | FPUflagC ) : \
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( _ContVal_ & ~FPUflagC ); \
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}
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@@ -344,20 +357,16 @@ static u32 eeRoundToSingle(double exact, bool addsub = false)
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return sign | static_cast<u32>((bits >> 29) & 0x7FFFFFu);
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}
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FPRreg r;
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if (mag >= 0x1p126)
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{
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/* Scale down by 2^4, round there, then add the 4 exponents back. The
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scaled exponent field is at most 251, so the +4 cannot carry into
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the sign, and the >= 2^126 floor keeps the scaled value normal, so
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nothing is flushed on the way through. */
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r.f = static_cast<float>(exact * 0x1p-4);
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r.UL += 4u << 23;
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return r.UL;
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return floatToBits(static_cast<float>(exact * 0x1p-4)) + (4u << 23);
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}
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r.f = static_cast<float>(exact);
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return r.UL;
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return floatToBits(static_cast<float>(exact));
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}
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/* The EE FPU's adder carries no guard bits to the right of the mantissa. A
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@@ -721,7 +730,7 @@ static u32 eeSqrtBits(u32 t)
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*/
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void ABS_S() {
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_FdValUl_ = _FsValUl_ & 0x7fffffff;
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_SetFdVal_( _FsValUl_ & 0x7fffffff );
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clearFPUFlags( FPUflagO | FPUflagU );
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}
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@@ -730,13 +739,13 @@ void ABS_S() {
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*/
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void ADD_S() {
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const double exact = eeToDouble( _FsValUl_ ) + eeToDouble( _FtValUl_ );
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_FdValUl_ = eeGuardedAddSub( _FsValUl_, _FtValUl_, false );
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_SetFdVal_( eeGuardedAddSub( _FsValUl_, _FtValUl_, false ) );
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raiseOrClearOU( exact );
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}
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void ADDA_S() {
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const double exact = eeToDouble( _FsValUl_ ) + eeToDouble( _FtValUl_ );
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_FAValUl_ = eeGuardedAddSub( _FsValUl_, _FtValUl_, false );
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_SetFAVal_( eeGuardedAddSub( _FsValUl_, _FtValUl_, false ) );
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raiseOrClearOU( exact );
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}
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@@ -790,13 +799,13 @@ void CTC1() {
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}
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void CVT_S() {
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_FdValf_ = (float)_FsValSl_;
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_SetFdVal_( floatToBits( (float)_FsValSl_ ) );
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}
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void CVT_W() {
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if ( ( _FsValUl_ & 0x7F800000 ) <= 0x4E800000 ) { _FdValSl_ = (s32)_FsValf_; }
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else if ( ( _FsValUl_ & 0x80000000 ) == 0 ) { _FdValUl_ = 0x7fffffff; }
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else { _FdValUl_ = 0x80000000; }
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if ( ( _FsValUl_ & 0x7F800000 ) <= 0x4E800000 ) { _SetFdVal_( (u32)(s32)bitsToFloat( _FsValUl_ ) ); }
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else if ( ( _FsValUl_ & 0x80000000 ) == 0 ) { _SetFdVal_( 0x7fffffff ); }
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else { _SetFdVal_( 0x80000000 ); }
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}
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void DIV_S() {
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@@ -804,8 +813,13 @@ void DIV_S() {
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// and RSQRT.S.
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clearFPUFlags(FPUflagI | FPUflagD);
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if (checkDivideByZero( _FdValUl_, _FtValUl_, _FsValUl_, FPUflagD | FPUflagSD, FPUflagI | FPUflagSI)) return;
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_FdValUl_ = eeDivide( _FsValUl_, _FtValUl_ );
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u32 saturated;
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if (checkDivideByZero( saturated, _FtValUl_, _FsValUl_, FPUflagD | FPUflagSD, FPUflagI | FPUflagSI))
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{
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_SetFdVal_( saturated );
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return;
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}
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_SetFdVal_( eeDivide( _FsValUl_, _FtValUl_ ) );
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}
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/* The EE multiplier's one-ULP deficit.
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@@ -983,7 +997,7 @@ static u32 eeMulRound(u32 fs, u32 ft, double exact)
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The A-forms name their single-precision product too, because the guarded adder
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needs its bits, and that takes the accumulate out of the compiler's reach as
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well: `_FAValf_ += fs * ft` is one expression a contracting compiler can turn
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well: `acc += fs * ft` is one expression a contracting compiler can turn
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into a single-rounded FMA, with only the -ffp-contract=off line in
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pcsx2/CMakeLists.txt between it and that. On corpus cases 567 and 1130 the
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fused value is the console's, so a contracting build hid the guard-bit defect
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@@ -1010,7 +1024,7 @@ static u32 eeMulAccumulate(u32 fs, u32 ft, u32 accbits, bool issub)
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void MADD_S() {
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const double product = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
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const double acc = eeToDouble( _FAValUl_ );
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_FdValUl_ = eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, false );
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_SetFdVal_( eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, false ) );
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raiseOrClearOU( product );
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if (madAccumulandOverflowed( product )) return;
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raiseOrClearOU( acc + madFlushedProduct( product ) );
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@@ -1019,14 +1033,14 @@ void MADD_S() {
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void MADDA_S() {
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const double product = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
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const double acc = eeToDouble( _FAValUl_ );
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_FAValUl_ = eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, false );
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_SetFAVal_( eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, false ) );
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raiseOrClearOU( product );
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if (madAccumulandOverflowed( product )) return;
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raiseOrClearOU( acc + madFlushedProduct( product ) );
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}
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void MAX_S() {
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_FdValUl_ = fp_max( _FsValUl_, _FtValUl_ );
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_SetFdVal_( fp_max( _FsValUl_, _FtValUl_ ) );
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clearFPUFlags( FPUflagO | FPUflagU );
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}
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@@ -1036,18 +1050,18 @@ void MFC1() {
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}
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void MIN_S() {
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_FdValUl_ = fp_min(_FsValUl_, _FtValUl_);
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_SetFdVal_( fp_min( _FsValUl_, _FtValUl_ ) );
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clearFPUFlags( FPUflagO | FPUflagU );
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}
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void MOV_S() {
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_FdValUl_ = _FsValUl_;
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_SetFdVal_( _FsValUl_ );
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}
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void MSUB_S() {
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const double product = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
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const double acc = eeToDouble( _FAValUl_ );
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_FdValUl_ = eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, true );
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_SetFdVal_( eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, true ) );
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raiseOrClearOU( product );
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if (madAccumulandOverflowed( product )) return;
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raiseOrClearOU( acc - madFlushedProduct( product ) );
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@@ -1056,14 +1070,14 @@ void MSUB_S() {
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void MSUBA_S() {
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const double product = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
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const double acc = eeToDouble( _FAValUl_ );
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_FAValUl_ = eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, true );
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_SetFAVal_( eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, true ) );
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raiseOrClearOU( product );
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if (madAccumulandOverflowed( product )) return;
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raiseOrClearOU( acc - madFlushedProduct( product ) );
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}
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void MTC1() {
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_FsValUl_ = cpuRegs.GPR.r[_Rt_].UL[0];
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_SetFsVal_( cpuRegs.GPR.r[_Rt_].UL[0] );
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}
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/* The product of two EE singles is 48 significand bits, so a double holds it
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@@ -1076,18 +1090,18 @@ void MTC1() {
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*/
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void MUL_S() {
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const double exact = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
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_FdValUl_ = eeMulRound( _FsValUl_, _FtValUl_, exact );
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_SetFdVal_( eeMulRound( _FsValUl_, _FtValUl_, exact ) );
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raiseOrClearOU( exact );
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}
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void MULA_S() {
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const double exact = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
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_FAValUl_ = eeMulRound( _FsValUl_, _FtValUl_, exact );
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_SetFAVal_( eeMulRound( _FsValUl_, _FtValUl_, exact ) );
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raiseOrClearOU( exact );
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}
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void NEG_S() {
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_FdValUl_ = (_FsValUl_ ^ 0x80000000);
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_SetFdVal_( _FsValUl_ ^ 0x80000000 );
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clearFPUFlags( FPUflagO | FPUflagU );
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}
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@@ -1110,7 +1124,7 @@ void RSQRT_S() {
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// time the division happens. Console rows 59 and 63: rsqrt(+0, -0) is
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// +0x7FFFFFFF and rsqrt(-0, -0) is -0x7FFFFFFF, and an xor rule flips
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// both.
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_FdValUl_ = ( _FsValUl_ & 0x80000000 ) | 0x7FFFFFFF;
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_SetFdVal_( ( _FsValUl_ & 0x80000000 ) | 0x7FFFFFFF );
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return;
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}
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@@ -1131,7 +1145,7 @@ void RSQRT_S() {
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// operand pairs over two probes, each pair run as sqrt.s, rsqrt.s and
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// div.s, and rsqrt.s equals div.s(Fs, sqrt.s(Ft)) on every row, with a
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// plain 24-bit single in between. See ee_fpu_divunit_console_tests.cpp.
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_FdValUl_ = eeDivide( _FsValUl_, eeSqrtBits( _FtValUl_ ) );
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_SetFdVal_( eeDivide( _FsValUl_, eeSqrtBits( _FtValUl_ ) ) );
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}
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void SQRT_S() {
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@@ -1148,18 +1162,18 @@ void SQRT_S() {
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if ( _FtValUl_ & 0x80000000 )
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_ContVal_ |= FPUflagI | FPUflagSI;
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_FdValUl_ = eeSqrtBits( _FtValUl_ );
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_SetFdVal_( eeSqrtBits( _FtValUl_ ) );
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}
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void SUB_S() {
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const double exact = eeToDouble( _FsValUl_ ) - eeToDouble( _FtValUl_ );
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_FdValUl_ = eeGuardedAddSub( _FsValUl_, _FtValUl_, true );
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_SetFdVal_( eeGuardedAddSub( _FsValUl_, _FtValUl_, true ) );
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raiseOrClearOU( exact );
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}
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void SUBA_S() {
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const double exact = eeToDouble( _FsValUl_ ) - eeToDouble( _FtValUl_ );
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_FAValUl_ = eeGuardedAddSub( _FsValUl_, _FtValUl_, true );
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_SetFAVal_( eeGuardedAddSub( _FsValUl_, _FtValUl_, true ) );
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raiseOrClearOU( exact );
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}
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@@ -1175,14 +1189,14 @@ void LWC1() {
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u32 addr;
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addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s16)(cpuRegs.code & 0xffff); // force sign extension to 32bit
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if (addr & 0x00000003) { Console.Error( "FPU (LWC1 Opcode): Invalid Unaligned Memory Address" ); return; } // Should signal an exception?
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fpuRegs.fpr[_Rt_].UL = memRead32(addr);
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fpuRegs.fpr[_Rt_].SetWord( memRead32(addr) );
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}
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void SWC1() {
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u32 addr;
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addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s16)(cpuRegs.code & 0xffff); // force sign extension to 32bit
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if (addr & 0x00000003) { Console.Error( "FPU (SWC1 Opcode): Invalid Unaligned Memory Address" ); return; } // Should signal an exception?
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memWrite32(addr, fpuRegs.fpr[_Rt_].UL);
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memWrite32(addr, fpuRegs.fpr[_Rt_].Word());
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}
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} } }
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