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Fix FPU.cpp: the interpreter clamped away the EE's top binade before every op
Exponent 255 is an ordinary exponent on this FPU: 0x7F800000 is 2^128, 0x7FFFFFFF is the largest number the machine has, and there is no Inf and no NaN. That is one binade above IEEE single, so fpuDouble() folded every such operand down to +/-0x7F7FFFFF on the way in and clampToEeRange() folded a host infinity back to the same word on the way out. ADD.S, SUB.S, MUL.S, their A-forms and the four multiply-accumulates now read their operands through eeToDouble() and round once through a new eeRoundToSingle(). Why the double arithmetic in between is exact, and how the top binade is rounded with no host single to round it in, is at eeGuardedAddSub, MUL_S and eeRoundToSingle. The multiplier's one-ULP deficit had to move across with it or it would have been lost here: it sat on top of fpuDouble() and read the operands as clamped, which changed ft's mantissa and so changed its own predicate. eeMulRound applies it to what eeRoundToSingle produces instead, and the six multiply forms reach it through eeMulProduct's replacement, eeMulAccumulate. One behavior changed beyond the range: an overflowing product now ends a MADD/MSUB, value as well as flag, where the value path used to carry on accumulating and land a binade away. The fast path is untouched. It computes in host singles and cannot hold these values at all; the warning against changing posFmax to suit it is at the top of ee_fpu_overflow_console_conformance_tests.cpp. DIV and RSQRT still read operands through fpuDouble and still saturate through checkDivideByZero's posFmax. A quotient of two singles is not exact in a double, so the eeToDouble route would double-round under the divide unit's round-to-nearest; they need the normalise-and-reassemble treatment the next commit gives them.
This commit is contained in:
pstef
+181
-130
@@ -6,7 +6,6 @@
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#include "common/FPControl.h"
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#include <cfloat>
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#include <cmath>
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#include <cstring>
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@@ -248,11 +247,16 @@ namespace COP1 {
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// FPU Opcodes
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//****************************************************************
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/* The operand model as bits: exponent 0 is zero on this FPU -- there are no
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denormals -- and exponent 255 is clamped away, for the reason at eeToDouble().
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fpuDouble() is this same mapping read back as a float; the guard-bit adder
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below needs it as bits.
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*/
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/* The operand model as bits. Exponent 0 is zero on this FPU -- there are no
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denormals -- and exponent 255 folds to +-0x7F7FFFFF, since a host single
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cannot hold the EE's top binade at all. fpuDouble() is this same mapping read
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back as a float.
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The arithmetic ops no longer use either: the fold destroys the operand
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before they see it, so they read eeToDouble() and round through
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eeRoundToSingle(). Still the model for the compare ops (C.EQ and friends),
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which only part from the unfolded operands where both are in the top binade,
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and those rows pass against the capture. */
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static u32 fpuOperandBits(u32 f)
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{
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switch (f & 0x7f800000)
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@@ -270,6 +274,53 @@ float fpuDouble(u32 f)
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return r.f;
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}
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/* Round an exact result into the EE encoding. This is the only rounding step
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the arithmetic ops below perform.
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Three things a bare (float) cast does not do:
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* Saturation is at the EE's maximum, 0x7FFFFFFF, not at FLT_MAX. On
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silicon, add.s of +2^128 to itself is 2^129, out of range, and comes
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back 0x7FFFFFFF; add.s of 0x7F7FFFFF to itself is exactly 0x7FFFFFFF and
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comes back unrounded. Folding either to 0x7F7FFFFF, which is what
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clampToEeRange did to a host infinity, is a whole binade short.
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* The top binade has no host single. Anything at or above 2^126 is rounded
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through a scaled-down copy and its exponent put back afterwards. Scaling
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by a power of two is exact and leaves the mantissa alone, so the rounding
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decision is bit-identical to the one the host would have made if float
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had the range.
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* Denormal results flush to signed zero, written out rather than left to
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the ambient FPCR's FZ.
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The (float) casts round under the host FPCR, so the EE's rounding mode is
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honoured here without naming it -- including the divide/sqrt unit's separate
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mode, which its callers scope in.
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*/
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static u32 eeRoundToSingle(double exact)
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{
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const double mag = std::fabs(exact);
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if (mag > kEeFpuMax)
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return (std::signbit(exact) ? 0x80000000u : 0u) | 0x7FFFFFFFu;
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FPRreg r;
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if (mag >= 0x1p126)
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{
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/* Scale down by 2^4, round there, then add the 4 exponents back. The
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scaled exponent field is at most 251, so the +4 cannot carry into
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the sign, and the >= 2^126 floor keeps the scaled value normal, so
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nothing is flushed on the way through. */
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r.f = static_cast<float>(exact * 0x1p-4);
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r.UL += 4u << 23;
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return r.UL;
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}
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r.f = static_cast<float>(exact);
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if ((r.UL & 0x7F800000) == 0)
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r.UL &= 0x80000000; // denormal or zero -- the EE has only the zero
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return r.UL;
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}
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/* The EE FPU's adder carries no guard bits to the right of the mantissa. A
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compliant adder shifts the smaller operand right into extra bits it keeps for
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the rounding decision; whatever shifts past this one's mantissa is gone.
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@@ -297,7 +348,7 @@ float fpuDouble(u32 f)
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The console rows this reproduces, with their corpus ordinals, are tabulated in
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tests/ctest/core/recompilers/ee_fpu_guarded_addsub_console_tests.cpp.
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*/
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static float fpuAddSubGuarded(u32 a, u32 b, bool issub)
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static void fpuGuardMask(u32& a, u32& b)
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{
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const s32 diff = (s32)((a >> 23) & 0xFF) - (s32)((b >> 23) & 0xFF);
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@@ -309,106 +360,23 @@ static float fpuAddSubGuarded(u32 a, u32 b, bool issub)
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a &= 0x80000000;
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else if (diff <= -2)
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a &= 0xffffffffu << (-diff - 1);
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FPRreg fa, fb;
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fa.UL = a;
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fb.UL = b;
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return issub ? (fa.f - fb.f) : (fa.f + fb.f);
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}
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/* The EE multiplier's one-ULP deficit.
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/* The EE's adder: mask the guard bits away, add exactly, round once.
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The console's multiply array is not a correctly-rounding multiplier: it
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comes back exactly one step closer to zero on a large fraction of operands,
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and which operands depends on operand order. Upstream states the rule in a
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comment (pcsx2/x86/iFPU.cpp:500) and never tests it; FpuMulHack is a
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one-point sample of it.
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The mask is what makes the add exact. Within 24 exponents the sum needs 48
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bits of the double's 53; beyond that the mask has already reduced the
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smaller operand to +-0. So eeRoundToSingle() below is the only rounding, as
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on the hardware.
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Measured on SCPH-90000 (FCR0 0x2e40), captures/fpmul/, 25M probes:
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* mul.s(1.0, x) was measured for every one of the 2^23 significands.
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8257536 come back one ULP low and 131072 exact -- and nothing ever came
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back high, or two ULP low, in 16.8M probes.
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* mul.s(x, 1.0) is exact for all 2^23. The asymmetry is total, not
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statistical: the predicate reads ft and never fs, which is exactly why
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the operation is not commutative.
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* Unchanged across twelve exponent-field pairs from (1,254) to (254,1),
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so it is a significand-domain effect with no exponent term.
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Bits 1,3,5,7,9 of ft's mantissa are the sign bits of the five lowest
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radix-4 Booth digits, which is what identifies the mechanism: ft is the
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recoded operand and the array's low columns are not built, so each low
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negative digit's two's-complement correction is dropped. The bit-11 term is
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a boundary effect at the truncation column; it is written as measured, not
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derived.
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What this does not model: the deficit is smaller than one ULP -- at most
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~27308 against an ULP of 2^23 -- so it only reaches the result when the
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exact product has nothing below the ULP to absorb it. That is the tail test
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below, and it is the whole of the modelled class. When the tail is non-zero
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the console is one ULP low iff the tail is smaller than the deficit, and the
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deficit is not identifiable from mul.s observations: the instruction only
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ever exposes the one comparison it performs. That residual is ~0.1% of
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random operand pairs.
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*/
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static bool eeMulDefectiveFt(u32 ft)
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Subtraction is addition of the negated operand, as IEEE defines it: that gets
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the zero signs right, including for a masked +-0. */
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static u32 eeGuardedAddSub(u32 a, u32 b, bool issub)
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{
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const u32 m = ft & 0x7FFFFF;
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if (m & 0x2AA) // a negative Booth digit among 0..4
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return true;
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const u32 h = (m >> 12) & 0xF;
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return ((m >> 11) & 1u) != ((h >= 8 && h <= 13) ? 1u : 0u);
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}
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static bool eeMulOneUlpLow(u32 fs, u32 ft)
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{
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if ((fs & 0x7F800000) == 0 || (ft & 0x7F800000) == 0)
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return false; // a zero operand (denormals are zero): the product is zero
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const u64 a = 0x800000u | (fs & 0x7FFFFF);
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const u64 b = 0x800000u | (ft & 0x7FFFFF);
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const u64 prod = a * b; // 47 or 48 significant bits, exact in 64
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const int k = (prod >> 47) ? 24 : 23;
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if (prod & ((1ull << k) - 1u))
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return false; // the tail below the ULP absorbs the deficit
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return eeMulDefectiveFt(ft);
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}
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/* fpuDouble() both operands, multiply, apply the deficit.
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The predicate is fed the operands as multiplied, not the guest registers:
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fpuDouble() clamps an exponent-0xff operand down to +/-Fmax, and that
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changes ft's mantissa. (Clamping there is a separate and known gap against
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silicon, which treats exponent 0xff as an ordinary binade; this models the
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multiplier on top of whatever fpuDouble hands it, rather than smuggling in a
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second change.)
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Applied only where it was measured. A saturating result, a flushed one, and
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a decrement that would walk the exponent field out of the normals are all
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left alone.
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*/
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static u32 eeMulProduct(u32 fs, u32 ft)
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{
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FPRreg s, t, p;
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s.f = fpuDouble( fs );
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t.f = fpuDouble( ft );
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p.f = s.f * t.f;
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// A saturated result is not a rounded one. Testing p.f for an infinity is
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// not enough: under round-toward-zero an overflowing product comes back as
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// Fmax, so checkOverflow() never sees it and the bit pattern is
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// indistinguishable from a product that genuinely landed on Fmax -- which
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// silicon does decrement (1.0 * FLT_MAX -> 0x7F7FFFFE). float x float is
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// exact in double, so ask the exact product instead.
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if (!(std::fabs( static_cast<double>(s.f) * static_cast<double>(t.f) ) <= FLT_MAX))
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return p.UL;
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if ((p.UL & 0x7F800000) == 0) // flushed, zero, or a denormal on its way out
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return p.UL;
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if ((p.UL & 0x7FFFFFFF) == 0x00800000) // a decrement would leave the normals
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return p.UL;
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return eeMulOneUlpLow( s.UL, t.UL ) ? p.UL - 1u : p.UL;
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fpuGuardMask(a, b);
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if (issub)
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b ^= 0x80000000;
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return eeRoundToSingle(eeToDouble(a) + eeToDouble(b));
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}
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/* The EE's divide/square-root unit rounds to nearest even when the rest of the
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@@ -460,15 +428,13 @@ void ABS_S() {
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*/
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void ADD_S() {
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const double exact = eeToDouble( _FsValUl_ ) + eeToDouble( _FtValUl_ );
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_FdValf_ = fpuAddSubGuarded( fpuOperandBits( _FsValUl_ ), fpuOperandBits( _FtValUl_ ), false );
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clampToEeRange( _FdValUl_ );
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_FdValUl_ = eeGuardedAddSub( _FsValUl_, _FtValUl_, false );
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raiseOrClearOU( exact );
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}
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void ADDA_S() {
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const double exact = eeToDouble( _FsValUl_ ) + eeToDouble( _FtValUl_ );
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_FAValf_ = fpuAddSubGuarded( fpuOperandBits( _FsValUl_ ), fpuOperandBits( _FtValUl_ ), false );
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clampToEeRange( _FAValUl_ );
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_FAValUl_ = eeGuardedAddSub( _FsValUl_, _FtValUl_, false );
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raiseOrClearOU( exact );
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}
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@@ -538,6 +504,86 @@ void DIV_S() {
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clampToEeRange( _FdValUl_ );
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}
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/* The EE multiplier's one-ULP deficit.
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The console's multiply array is not a correctly-rounding multiplier: it
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comes back exactly one step closer to zero on a large fraction of operands,
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and which operands depends on operand order. Upstream states the rule in a
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comment (`pcsx2/x86/iFPU.cpp:500`) and never tests it; FpuMulHack is a
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one-point sample of it.
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Measured on SCPH-90000 (FCR0 0x2e40), captures/fpmul/ in the session
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archive, 25M probes over three runs:
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* `mul.s(1.0, x)` was measured for all 2^23 significands. 8257536 of them
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come back one ULP low and 131072 exact -- and nothing ever came back
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high, or two ULP low, in 16.8M probes.
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* `mul.s(x, 1.0)` is exact for all 2^23. The asymmetry is total, not
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statistical: the predicate reads ft and never fs, which is exactly why
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the operation is not commutative.
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* Unchanged across twelve exponent-field pairs from (1,254) to (254,1),
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so it is a significand-domain effect with no exponent term.
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Bits 1,3,5,7,9 of ft's mantissa are the sign bits of the five lowest
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radix-4 Booth digits, which is what identifies the mechanism: ft is the
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recoded operand and the array's low columns are not built, so each low
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negative digit's two's-complement correction is dropped. The bit-11 term
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does not follow from that mechanism; it is what the capture shows at the
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truncation column. In Booth form the same predicate reads "exact iff digits
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0..4 are non-negative and (d5<0) == (d7<0)", which was checked equivalent
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over the whole 2^23 space.
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What this does not model: the deficit is smaller than one ULP -- at most
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~27308 against an ULP of 2^23 -- so it only reaches the result when the
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exact product has nothing below the ULP to absorb it. That is the `tail`
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test below, and it is the whole of the modelled class. When the tail is
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non-zero the console is one ULP low iff the tail is smaller than the
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deficit, and the deficit is not identifiable from mul.s observations: it is
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only ever visible through the single comparison the instruction performs.
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That residual is ~0.1% of random operand pairs and 0 rows of the console
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corpus.
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Applied only where it was measured; the three guards are in eeMulRound().
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*/
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static bool eeMulDefectiveFt(u32 ft)
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{
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const u32 m = ft & 0x7FFFFF;
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if (m & 0x2AA) // a negative Booth digit among 0..4
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return true;
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const u32 h = (m >> 12) & 0xF;
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return ((m >> 11) & 1u) != ((h >= 8 && h <= 13) ? 1u : 0u);
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}
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static bool eeMulOneUlpLow(u32 fs, u32 ft)
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{
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if ((fs & 0x7F800000) == 0 || (ft & 0x7F800000) == 0)
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return false; // a zero operand (denormals are zero): the product is zero
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const u64 a = 0x800000u | (fs & 0x7FFFFF);
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const u64 b = 0x800000u | (ft & 0x7FFFFF);
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const u64 prod = a * b; // 47 or 48 significant bits, exact in 64
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const int k = (prod >> 47) ? 24 : 23;
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if (prod & ((1ull << k) - 1u))
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return false; // the tail below the ULP absorbs the deficit
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return eeMulDefectiveFt(ft);
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}
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/* eeRoundToSingle() for a product, plus the multiplier defect. */
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static u32 eeMulRound(u32 fs, u32 ft, double exact)
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{
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const u32 w = eeRoundToSingle(exact);
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if (std::fabs(exact) > kEeFpuMax) // saturated: never measured, leave it
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return w;
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if ((w & 0x7F800000) == 0) // flushed to zero
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return w;
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if ((w & 0x7FFFFFFF) == 0x00800000) // a decrement would leave the normals
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return w;
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return eeMulOneUlpLow(fs, ft) ? w - 1u : w;
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}
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/* The Instruction Set manual has an overly complicated way of
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determining the flags that are set. Hopefully this shorter
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method provides a similar outcome and is faster. (cottonvibes)
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@@ -558,25 +604,34 @@ void DIV_S() {
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fpuDouble; the flag path uses the architectural value in both. That
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inconsistency in the value path is pre-existing and left alone.
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*/
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/* fd = ACC +/- fs * ft, in the two rounding steps the ISA mandates: the product
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lands in an EE single before the accumulate sees it, and an overflowing one
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ends the instruction there rather than being accumulated. That is the test
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madAccumulandOverflowed() has always made for the flag; the value follows it
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now too.
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*/
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static u32 eeMulAccumulate(u32 fs, u32 ft, u32 accbits, bool issub)
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{
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const double product = eeToDouble( fs ) * eeToDouble( ft );
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const u32 rounded = eeMulRound( fs, ft, product ) ^ (issub ? 0x80000000u : 0u);
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if (madAccumulandOverflowed( product ))
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return rounded;
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return eeGuardedAddSub( accbits, rounded, false );
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}
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void MADD_S() {
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FPRreg temp;
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const double product = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
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const double acc = eeToDouble( _FAValUl_ );
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temp.UL = eeMulProduct( _FsValUl_, _FtValUl_ );
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_FdValf_ = fpuAddSubGuarded( fpuOperandBits( _FAValUl_ ), fpuOperandBits( temp.UL ), false );
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clampToEeRange( _FdValUl_ );
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_FdValUl_ = eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, false );
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raiseOrClearOU( product );
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if (madAccumulandOverflowed( product )) return;
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raiseOrClearOU( acc + madFlushedProduct( product ) );
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}
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void MADDA_S() {
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FPRreg temp;
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const double product = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
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const double acc = eeToDouble( _FAValUl_ );
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temp.UL = eeMulProduct( _FsValUl_, _FtValUl_ );
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_FAValf_ = fpuAddSubGuarded( _FAValUl_, temp.UL, false );
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clampToEeRange( _FAValUl_ );
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_FAValUl_ = eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, false );
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raiseOrClearOU( product );
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if (madAccumulandOverflowed( product )) return;
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raiseOrClearOU( acc + madFlushedProduct( product ) );
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@@ -602,24 +657,18 @@ void MOV_S() {
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}
|
||||
|
||||
void MSUB_S() {
|
||||
FPRreg temp;
|
||||
const double product = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
|
||||
const double acc = eeToDouble( _FAValUl_ );
|
||||
temp.UL = eeMulProduct( _FsValUl_, _FtValUl_ );
|
||||
_FdValf_ = fpuAddSubGuarded( fpuOperandBits( _FAValUl_ ), fpuOperandBits( temp.UL ), true );
|
||||
clampToEeRange( _FdValUl_ );
|
||||
_FdValUl_ = eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, true );
|
||||
raiseOrClearOU( product );
|
||||
if (madAccumulandOverflowed( product )) return;
|
||||
raiseOrClearOU( acc - madFlushedProduct( product ) );
|
||||
}
|
||||
|
||||
void MSUBA_S() {
|
||||
FPRreg temp;
|
||||
const double product = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
|
||||
const double acc = eeToDouble( _FAValUl_ );
|
||||
temp.UL = eeMulProduct( _FsValUl_, _FtValUl_ );
|
||||
_FAValf_ = fpuAddSubGuarded( _FAValUl_, temp.UL, true );
|
||||
clampToEeRange( _FAValUl_ );
|
||||
_FAValUl_ = eeMulAccumulate( _FsValUl_, _FtValUl_, _FAValUl_, true );
|
||||
raiseOrClearOU( product );
|
||||
if (madAccumulandOverflowed( product )) return;
|
||||
raiseOrClearOU( acc - madFlushedProduct( product ) );
|
||||
@@ -629,17 +678,21 @@ void MTC1() {
|
||||
_FsValUl_ = cpuRegs.GPR.r[_Rt_].UL[0];
|
||||
}
|
||||
|
||||
/* The product of two EE singles is 48 significand bits, so a double holds it
|
||||
exactly at any exponent and eeRoundToSingle() does the only rounding. The
|
||||
multiplier's own one-ULP deficit rides on top, in eeMulRound(); what it
|
||||
models and what it does not is at eeMulDefectiveFt. The flags stay on the
|
||||
exact product, per raiseOrClearOU().
|
||||
*/
|
||||
void MUL_S() {
|
||||
const double exact = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
|
||||
_FdValUl_ = eeMulProduct( _FsValUl_, _FtValUl_ );
|
||||
clampToEeRange( _FdValUl_ );
|
||||
_FdValUl_ = eeMulRound( _FsValUl_, _FtValUl_, exact );
|
||||
raiseOrClearOU( exact );
|
||||
}
|
||||
|
||||
void MULA_S() {
|
||||
const double exact = eeToDouble( _FsValUl_ ) * eeToDouble( _FtValUl_ );
|
||||
_FAValUl_ = eeMulProduct( _FsValUl_, _FtValUl_ );
|
||||
clampToEeRange( _FAValUl_ );
|
||||
_FAValUl_ = eeMulRound( _FsValUl_, _FtValUl_, exact );
|
||||
raiseOrClearOU( exact );
|
||||
}
|
||||
|
||||
@@ -722,15 +775,13 @@ void SQRT_S() {
|
||||
|
||||
void SUB_S() {
|
||||
const double exact = eeToDouble( _FsValUl_ ) - eeToDouble( _FtValUl_ );
|
||||
_FdValf_ = fpuAddSubGuarded( fpuOperandBits( _FsValUl_ ), fpuOperandBits( _FtValUl_ ), true );
|
||||
clampToEeRange( _FdValUl_ );
|
||||
_FdValUl_ = eeGuardedAddSub( _FsValUl_, _FtValUl_, true );
|
||||
raiseOrClearOU( exact );
|
||||
}
|
||||
|
||||
void SUBA_S() {
|
||||
const double exact = eeToDouble( _FsValUl_ ) - eeToDouble( _FtValUl_ );
|
||||
_FAValf_ = fpuAddSubGuarded( fpuOperandBits( _FsValUl_ ), fpuOperandBits( _FtValUl_ ), true );
|
||||
clampToEeRange( _FAValUl_ );
|
||||
_FAValUl_ = eeGuardedAddSub( _FsValUl_, _FtValUl_, true );
|
||||
raiseOrClearOU( exact );
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user