diff --git a/pcsx2/x86/iFPU.cpp b/pcsx2/x86/iFPU.cpp
index b9fad09fa8..bae66f300e 100644
--- a/pcsx2/x86/iFPU.cpp
+++ b/pcsx2/x86/iFPU.cpp
@@ -177,8 +177,7 @@ void recMFC1()
 
 		// both in xmm, sign extend and insert lower bits
 		const int temp = _allocTempXMMreg(XMMT_FPS);
-		xMOVAPS(xRegisterSSE(temp), xRegisterSSE(regs));
-		xPSRA.D(xRegisterSSE(temp), 31);
+		xPSRA.D(xRegisterSSE(temp), xRegisterSSE(regs), 31);
 		xMOVSS(xRegisterSSE(xmmregt), xRegisterSSE(regs));
 		xINSERTPS(xRegisterSSE(xmmregt), xRegisterSSE(temp), _MM_MK_INSERTPS_NDX(0, 1, 0));
 		_freeXMMreg(temp);
@@ -436,8 +435,7 @@ void FPU_ADD_SUB(int regd, int regt, int issub)
 
 	x86SetJ8(j8Ptr[0]);
 	//diff = 25 .. 255 , expt < expd
-	xMOVAPS(xRegisterSSE(xmmtemp), xRegisterSSE(regt));
-	xAND.PS(xRegisterSSE(xmmtemp), ptr[s_neg]);
+	xAND.PS(xRegisterSSE(xmmtemp), xRegisterSSE(regt), ptr[s_neg]);
 	if (issub)
 		xSUB.SS(xRegisterSSE(regd), xRegisterSSE(xmmtemp));
 	else
diff --git a/pcsx2/x86/iFPUd.cpp b/pcsx2/x86/iFPUd.cpp
index 074de8d8c1..c741666614 100644
--- a/pcsx2/x86/iFPUd.cpp
+++ b/pcsx2/x86/iFPUd.cpp
@@ -169,8 +169,7 @@ void ToPS2FPU_Full(int reg, bool flags, int absreg, bool acc, bool addsub)
 	if (flags && acc)
 		xAND(ptr32[&fpuRegs.ACCflag], ~1);
 
-	xMOVAPS(xRegisterSSE(absreg), xRegisterSSE(reg));
-	xAND.PD(xRegisterSSE(absreg), ptr[&s_const.dbl_s_pos]);
+	xAND.PD(xRegisterSSE(absreg), xRegisterSSE(reg), ptr[&s_const.dbl_s_pos]);
 
 	xUCOMI.SD(xRegisterSSE(absreg), ptr[&s_const.dbl_cvt_overflow]);
 	u8* to_complex = JAE8(0);
diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl
index a46d60dcbe..fb8138f2e9 100644
--- a/pcsx2/x86/microVU_Lower.inl
+++ b/pcsx2/x86/microVU_Lower.inl
@@ -516,13 +516,11 @@ mVUop(mVU_ESIN)
 		SSE_ADDSS(mVU, xmmPQ, Fs); // pq = X + s2 * X^3
 
 		SSE_MULSS(mVU, t2, t1);    // t2 = X^3 * X^2
-		xMOVAPS       (Fs, t2);    // fs = X^5
-		xMUL.SS       (Fs, ptr32[mVUglob.S3]); // ps = s3 * X^5
+		xMUL.SS       (Fs, t2, ptr32[mVUglob.S3]); // ps = s3 * X^5
 		SSE_ADDSS(mVU, xmmPQ, Fs); // pq = X + s2 * X^3 + s3 * X^5
 
 		SSE_MULSS(mVU, t2, t1);    // t2 = X^5 * X^2
-		xMOVAPS       (Fs, t2);    // fs = X^7
-		xMUL.SS       (Fs, ptr32[mVUglob.S4]); // fs = s4 * X^7
+		xMUL.SS       (Fs, t2, ptr32[mVUglob.S4]); // fs = s4 * X^7
 		SSE_ADDSS(mVU, xmmPQ, Fs); // pq = X + s2 * X^3 + s3 * X^5 + s4 * X^7
 
 		SSE_MULSS(mVU, t2, t1);    // t2 = X^7 * X^2
diff --git a/pcsx2/x86/microVU_Upper.inl b/pcsx2/x86/microVU_Upper.inl
index 42fbdc97d4..25fccc5b2f 100644
--- a/pcsx2/x86/microVU_Upper.inl
+++ b/pcsx2/x86/microVU_Upper.inl
@@ -80,8 +80,7 @@ static void mVUupdateFlags(mV, const xmm& reg, const xmm& regT1in = xEmptyReg, c
 	if (sFLAG.doFlag && CHECK_VUOVERFLOWHACK)
 	{
 		//Calculate overflow
-		xMOVAPS(regT1, regT2);
-		xAND.PS(regT1, ptr128[&sse4_compvals[1][0]]); // Remove sign flags (we don't care)
+		xAND.PS(regT1, regT2, ptr128[&sse4_compvals[1][0]]); // Remove sign flags (we don't care)
 		xCMPNLT.PS(regT1, ptr128[&sse4_compvals[0][0]]); // Compare if T1 == FLT_MAX
 		xMOVMSKPS(gprT2, regT1); // Grab sign bits  for equal results
 		xAND(gprT2, AND_XYZW); // Grab "Is FLT_MAX" bits from the previous calculation
@@ -490,8 +489,7 @@ static void mVU_FTOIx(mP, const float* addr, microOpcode opEnum)
 		// So for unrepresentable positive values, xor with 0xffffffff to turn 0x80000000 into 0x7fffffff.
 		if (addr)
 			xMUL.PS(Fs, ptr128[addr]);
-		xMOVAPS(t1, Fs);
-		xPCMP.GTD(t1, ptr128[mVUglob.I32MAXF]);
+		xPCMP.GTD(t1, Fs, ptr128[mVUglob.I32MAXF]);
 		xCVTTPS2DQ(Fs, Fs);
 		xPXOR(Fs, t1);
 
@@ -546,15 +544,13 @@ mVUop(mVU_CLIP)
 		mVUallocCFLAGa(mVU, gprT1, cFLAG.lastWrite);
 		xSHL(gprT1, 6);
 
-		xMOVAPS  (t1, ptr128[mVUglob.exponent]);
-		xPAND    (t1, Fs);
+		xPAND    (t1, Fs, ptr128[mVUglob.exponent]);
 		xPXOR    (t2, t2);
 		xPCMP.EQD(t1, t2); // Denormal check
 		xPANDN   (t1, Fs); // If denormal, set to zero, which can't be greater than any nonnegative denormal in Ft
 		xPAND    (Ft, ptr128[mVUglob.absclip]);
 
-		xMOVAPS  (Fs, ptr128[mVUglob.signbit]);
-		xPXOR    (Fs, t1); // Negate
+		xPXOR    (Fs, t1, ptr128[mVUglob.signbit]); // Negate
 		xPCMP.GTD(t1, Ft); // +w, +z, +y, +x
 		xPCMP.GTD(Fs, Ft); // -w, -z, -y, -x