mirror of
https://github.com/ARMSX2/ARMSX1.git
synced 2026-08-24 16:53:35 -07:00
171 lines
5.9 KiB
C
171 lines
5.9 KiB
C
#ifndef DMA_H
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#define DMA_H
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#include <stdint.h>
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#define PSX_DMAR_BEGIN 0x1f801080
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#define PSX_DMAR_SIZE 0x80
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#define PSX_DMAR_END 0x1f8010ff
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#include "../bus.h"
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#include "ic.h"
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typedef struct {
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uint32_t madr;
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uint32_t bcr;
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uint32_t chcr;
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} dma_channel_t;
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typedef struct {
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uint32_t bus_delay;
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uint32_t io_base, io_size;
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psx_bus_t* bus;
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psx_ic_t* ic;
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dma_channel_t mdec_in;
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dma_channel_t mdec_out;
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dma_channel_t gpu;
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dma_channel_t cdrom;
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dma_channel_t spu;
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dma_channel_t pio;
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dma_channel_t otc;
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int mdec_in_irq_delay;
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int mdec_out_irq_delay;
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int cdrom_irq_delay;
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int spu_irq_delay;
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int gpu_irq_delay;
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int otc_irq_delay;
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uint32_t dpcr;
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uint32_t dicr;
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} psx_dma_t;
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psx_dma_t* psx_dma_create(void);
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void psx_dma_init(psx_dma_t*, psx_bus_t*, psx_ic_t*);
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void psx_dma_do_mdec_in(psx_dma_t*);
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void psx_dma_do_mdec_out(psx_dma_t*);
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void psx_dma_do_gpu(psx_dma_t*);
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void psx_dma_do_cdrom(psx_dma_t*);
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void psx_dma_do_spu(psx_dma_t*);
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void psx_dma_do_pio(psx_dma_t*);
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void psx_dma_do_otc(psx_dma_t*);
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void psx_dma_perform(psx_dma_t*, int);
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uint32_t psx_dma_read32(psx_dma_t*, uint32_t);
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uint16_t psx_dma_read16(psx_dma_t*, uint32_t);
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uint8_t psx_dma_read8(psx_dma_t*, uint32_t);
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void psx_dma_write32(psx_dma_t*, uint32_t, uint32_t);
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void psx_dma_write16(psx_dma_t*, uint32_t, uint16_t);
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void psx_dma_write8(psx_dma_t*, uint32_t, uint8_t);
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void psx_dma_destroy(psx_dma_t*);
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void psx_dma_update(psx_dma_t*, int);
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typedef void (*psx_dma_do_fn_t)(psx_dma_t*);
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/*
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0-2 DMA0, MDECin Priority (0..7; 0=Highest, 7=Lowest)
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3 DMA0, MDECin Master Enable (0=Disable, 1=Enable)
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4-6 DMA1, MDECout Priority (0..7; 0=Highest, 7=Lowest)
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7 DMA1, MDECout Master Enable (0=Disable, 1=Enable)
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8-10 DMA2, GPU Priority (0..7; 0=Highest, 7=Lowest)
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11 DMA2, GPU Master Enable (0=Disable, 1=Enable)
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12-14 DMA3, CDROM Priority (0..7; 0=Highest, 7=Lowest)
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15 DMA3, CDROM Master Enable (0=Disable, 1=Enable)
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16-18 DMA4, SPU Priority (0..7; 0=Highest, 7=Lowest)
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19 DMA4, SPU Master Enable (0=Disable, 1=Enable)
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20-22 DMA5, PIO Priority (0..7; 0=Highest, 7=Lowest)
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23 DMA5, PIO Master Enable (0=Disable, 1=Enable)
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24-26 DMA6, OTC Priority (0..7; 0=Highest, 7=Lowest)
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27 DMA6, OTC Master Enable (0=Disable, 1=Enable)
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28-30 Unknown, Priority Offset or so? (R/W)
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31 Unknown, no effect? (R/W)
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*/
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#define DPCR_DMA0EN 0x00000008
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#define DPCR_DMA1EN 0x00000080
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#define DPCR_DMA2EN 0x00000800
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#define DPCR_DMA3EN 0x00008000
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#define DPCR_DMA4EN 0x00080000
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#define DPCR_DMA5EN 0x00800000
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#define DPCR_DMA6EN 0x08000000
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/*
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0 Transfer Direction (0=To Main RAM, 1=From Main RAM)
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1 Memory Address Step (0=Forward;+4, 1=Backward;-4)
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2-7 Not used (always zero)
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8 Chopping Enable (0=Normal, 1=Chopping; run CPU during DMA gaps)
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9-10 SyncMode, Transfer Synchronisation/Mode (0-3):
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0 Start immediately and transfer all at once (used for CDROM, OTC)
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1 Sync blocks to DMA requests (used for MDEC, SPU, and GPU-data)
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2 Linked-List mode (used for GPU-command-lists)
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3 Reserved (not used)
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11-15 Not used (always zero)
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16-18 Chopping DMA Window Size (1 SHL N words)
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19 Not used (always zero)
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20-22 Chopping CPU Window Size (1 SHL N clks)
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23 Not used (always zero)
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24 Start/Busy (0=Stopped/Completed, 1=Start/Enable/Busy)
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25-27 Not used (always zero)
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28 Start/Trigger (0=Normal, 1=Manual Start; use for SyncMode=0)
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29 Unknown (R/W) Pause? (0=No, 1=Pause?) (For SyncMode=0 only?)
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30 Unknown (R/W)
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31 Not used (always zero)
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*/
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#define CHCR_TDIR_MASK 0x00000001
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#define CHCR_STEP_MASK 0x00000002
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#define CHCR_CPEN_MASK 0x00000100
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#define CHCR_SYNC_MASK 0x00000600
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#define CHCR_CDWS_MASK 0x00070000
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#define CHCR_CCWS_MASK 0x00380000
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#define CHCR_BUSY_MASK 0x01000000
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#define CHCR_TRIG_MASK 0x10000000
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#define SYNC_SHIF 9
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#define CDWS_SHIF 16
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#define CCWS_SHIF 19
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#define CHCR_TDIR(c) (dma->c.chcr & CHCR_TDIR_MASK)
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#define CHCR_STEP(c) (dma->c.chcr & CHCR_STEP_MASK)
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#define CHCR_CPEN(c) (dma->c.chcr & CHCR_CPEN_MASK)
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#define CHCR_SYNC(c) ((dma->c.chcr & CHCR_SYNC_MASK) >> SYNC_SHIF)
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#define CHCR_CDWS(c) ((dma->c.chcr & CHCR_CDWS_MASK) >> CDWS_SHIF)
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#define CHCR_CCWS(c) ((dma->c.chcr & CHCR_CCWS_MASK) >> CCWS_SHIF)
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#define CHCR_BUSY(c) (dma->c.chcr & CHCR_BUSY_MASK)
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#define CHCR_TRIG(c) (dma->c.chcr & CHCR_TRIG_MASK)
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#define BCR_SIZE(c) (dma->c.bcr & 0xffff)
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#define BCR_BCNT(c) ((dma->c.bcr >> 16) & 0xffff)
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/*
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0-5 Unknown (read/write-able)
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6-14 Not used (always zero)
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15 Force IRQ (sets bit31) (0=None, 1=Force Bit31=1)
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16-22 IRQ Enable setting bit24-30 upon DMA0..DMA6 (0=None, 1=Enable)
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23 IRQ Enable setting bit31 when bit24-30=nonzero (0=None, 1=Enable)
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24-30 IRQ Flags for DMA0..DMA6 (Write 1 to reset) (0=None, 1=IRQ)
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31 IRQ Signal (0-to-1 triggers 1F801070h.bit3) (0=None, 1=IRQ) (R)
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*/
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#define DICR_FORCE 0x00008000
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#define DICR_FLGEN 0x007f0000
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#define DICR_IRQEN 0x00800000
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#define DICR_FLAGS 0x7f000000
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#define DICR_IRQSI 0x80000000
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#define DICR_DMA0EN 0x00010000
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#define DICR_DMA1EN 0x00020000
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#define DICR_DMA2EN 0x00040000
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#define DICR_DMA3EN 0x00080000
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#define DICR_DMA4EN 0x00100000
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#define DICR_DMA5EN 0x00200000
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#define DICR_DMA6EN 0x00400000
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#define DICR_DMA0FL 0x01000000
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#define DICR_DMA1FL 0x02000000
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#define DICR_DMA2FL 0x04000000
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#define DICR_DMA3FL 0x08000000
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#define DICR_DMA4FL 0x10000000
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#define DICR_DMA5FL 0x20000000
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#define DICR_DMA6FL 0x40000000
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#endif |