From c73cd1c3183e93b33ecad5d75611628346479682 Mon Sep 17 00:00:00 2001 From: Lycoder Date: Tue, 30 May 2023 23:00:30 -0300 Subject: [PATCH] Tidy up some files --- psx/bus.c | 4 ++-- psx/bus.h | 2 -- psx/dev/dma.c | 7 ++++--- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/psx/bus.c b/psx/bus.c index 6b360a0..19e15be 100644 --- a/psx/bus.c +++ b/psx/bus.c @@ -219,5 +219,5 @@ void psx_bus_init_spu(psx_bus_t* bus, psx_spu_t* spu) { bus->spu = spu; } - -#undef HANDLE_READ \ No newline at end of file +#undef HANDLE_READ +#undef HANDLE_WRITE \ No newline at end of file diff --git a/psx/bus.h b/psx/bus.h index 832cc9b..839ceda 100644 --- a/psx/bus.h +++ b/psx/bus.h @@ -7,8 +7,6 @@ struct psx_bus_t; typedef struct psx_bus_t psx_bus_t; -#define PSX_GPUSTAT 0x1f801814 - psx_bus_t* psx_bus_create(); void psx_bus_init(psx_bus_t*); uint32_t psx_bus_read32(psx_bus_t*, uint32_t); diff --git a/psx/dev/dma.c b/psx/dev/dma.c index b3ff346..0c6a32a 100644 --- a/psx/dev/dma.c +++ b/psx/dev/dma.c @@ -36,7 +36,7 @@ uint32_t psx_dma_read32(psx_dma_t* dma, uint32_t offset) { int channel = (offset >> 4) & 0x7; int reg = (offset >> 2) & 0x3; - log_error("DMA channel %u register %u read %08x", channel, reg, (CR(channel, reg))); + log_error("DMA channel %u register %u (%08x) read %08x", channel, reg, PSX_DMAR_BEGIN + offset, (CR(channel, reg))); return CR(channel, reg); } else { @@ -86,7 +86,7 @@ void psx_dma_write32(psx_dma_t* dma, uint32_t offset, uint32_t value) { CR(channel, reg) = value; - log_error("DMA channel %u register %u write %08x", channel, reg, value); + log_error("DMA channel %u register %u write (%08x) %08x", channel, reg, PSX_DMAR_BEGIN + offset, value); if (reg == 2) { g_psx_dma_do_table[channel](dma); @@ -228,7 +228,8 @@ void psx_dma_do_otc(psx_dma_t* dma) { } // Clear BCR and CHCR trigger and busy bits - dma->otc.chcr &= ~(CHCR_BUSY_MASK | CHCR_TRIG_MASK); + dma->otc.chcr = 0; + //dma->otc.chcr &= ~(CHCR_BUSY_MASK | CHCR_TRIG_MASK); dma->otc.bcr = 0; }