sunxi-DT-overlays/sun5i-a13

This document describes overlays provided in the kernel packages
For generic Armbian overlays documentation please see
https://docs.armbian.com/User-Guide_Allwinner_overlays/

### Platform:

sun5i-a13 (Allwinner A13)

### Platform details:

I2C bus 0 is used for the AXP209 PMIC

### Provided overlays:

- analog-codec
- i2c1
- i2c2
- nand
- pwm
- spi0
- spi1
- spi2
- spi-jedec-nor
- spi-spidev
- uart0
- uart1
- uart2
- uart3

### Overlay details:

### analog-codec

Activates SoC analog codec driver that provides HP Out and Mic In
functionality

### i2c1

Activates TWI/I2C bus 1

I2C1 pins (SCL, SDA): PB15, PB16

### i2c2

Activates TWI/I2C bus 2

I2C2 pins (SCL, SDA): PB17, PB18

### nand

Activates NAND controller

This overlay should not be used until mainline MLC NAND support
allows using NAND storage reliably

### pwm

Activates hardware PWM controller

PWM pins (PWM0): PB2

### spi0

Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it

SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3

### spi1

Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it

SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9

### spi2

Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it

SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0

### spi-jedec-nor

Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
supported by the kernel SPI NOR driver

SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3
SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9
SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0

Parameters:

param_spinor_spi_bus (int)
	SPI bus to activate SPI NOR flash support on
	Required
	Supported values: 0, 1, 2

param_spinor_max_freq (int)
	Maximum SPI frequency
	Optional
	Default: 1000000
	Range: 3000 - 100000000

### spi-spidev

Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
where X is the bus number and Y is the CS number

SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3
SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9
SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0

Parameters:

param_spidev_spi_bus (int)
	SPI bus to activate mcp2515 support on
	Required
	Supported values: 0, 1, 2

param_spidev_max_freq (int)
	Maximum SPIdev frequency
	Optional
	Default: 1000000
	Range: 3000 - 100000000

### uart 0

Activates serial port 0 (/dev/ttyS0)

UART 0 pins (TX, RX): PF2, PF4

### uart 1

Activates serial port 1 (/dev/ttyS1)

UART 1 pins a (TX, RX): PE10, PE11
UART 1 pins b (TX, RX): PG3, PG4

Parameters:

param_uart1_pins (char)
	UART 1 pinmux variant
	Optional
	Default: a
	Supported values: a, b
	Determines what pins UART 1 is exposed on if UART 1 is used

### uart2

Activates serial port 2 (/dev/ttyS2)

UART 2 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5

Parameters:

param_uart2_rtscts (bool)
	Enable RTS and CTS pins
	Optional
	Default: 0
	Set to 1 to enable CTS and RTS pins

### uart3

Activates serial port 3 (/dev/ttyS3)

UART 3 pins (TX, RX, RTS, CTS): PG9, PG10, PG12, PG11

Parameters:

param_uart3_rtscts (bool)
	Enable RTS and CTS pins
	Optional
	Default: 0
	Set to 1 to enable CTS and RTS pins