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04e6e5c7a0
Since some special hardware or panel need to invert dclk,
so we add dclk invert config at dts display timing node:
dts sample:
display-timings {
timing0: timing0 {
...
pixelclk-active = <1>;
...
}
}
Change-Id: I64f053ecda0f607bdd6fd392a0922489502ac274
Signed-off-by: Sandy Huang <hjc@rock-chips.com>