Files
linux/drivers/clk
Eric Anholt b3822a1078 clk: bcm2835: Fix setting of PLL divider clock rates
commit 773b3966dd3cdaeb68e7f2edfe5656abac1dc411 upstream.

Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write.  It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.

Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-04-12 09:09:02 -07:00
..
2015-09-17 11:15:14 -07:00
2015-07-20 11:11:36 -07:00
2015-11-25 14:06:16 -08:00
2015-10-01 15:24:34 -07:00
2015-07-20 11:11:32 -07:00
2015-05-21 11:55:05 -07:00
2015-07-20 11:11:22 -07:00
2015-07-20 11:11:33 -07:00
2015-11-30 13:00:54 -08:00
2015-07-20 10:53:00 -07:00
2015-11-30 16:29:15 -08:00
2015-07-20 11:11:35 -07:00
2015-07-20 10:53:04 -07:00
2015-07-20 10:53:05 -07:00