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Files

Yakir Yang 455be1a2af drm: bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1

There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit 45970584ea (FROMLIST: drm: bridge:
analogix/dp: add some rk3288 special registers setting).

The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.

Change-Id: I8cb806d23144697225f626aaa2af19e6379dfe51
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

2016-03-29 20:15:46 +08:00

analogix

drm: bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1

2016-03-29 20:15:46 +08:00

dw_hdmi-ahb-audio.c

drm: bridge/dw_hdmi-ahb-audio: allow larger buffer sizes

2015-10-09 17:17:30 +01:00

dw_hdmi-audio.h

drm: bridge/dw_hdmi-ahb-audio: parse ELD from HDMI driver

2015-10-09 17:17:24 +01:00

dw_hdmi.c

drm: bridge/dw_hdmi: replace CTS calculation for the ACR