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7258416c51
Most of these relate to endianness problems, and are purely cosmetic. But a couple of them were legit -- listen interval parsing and some of the rate selection code would malfunction on BE systems. There's still one cosmetic warning remaining, in the (admittedly) ugly code in cw1200_spi.c. It's there because the hardware needs 16-bit SPI transfers, but many SPI controllers only operate 8 bits at a time. If there's a cleaner way of handling this, I'm all ears. Signed-off-by: Solomon Peachy <pizza@shaftnet.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>