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Yakir Yang 13320df7cf FROMLIST: drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

(am from https://patchwork.kernel.org/patch/8312791/)

Change-Id: Ia7f37daf40fa2d0516d5c44737ad36b5822c6015
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

2016-03-21 19:39:40 +08:00

arm

MALI: rockchip: not to use sg_dma_len.

2016-03-09 15:26:53 +08:00

drm

FROMLIST: drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range

2016-03-21 19:39:40 +08:00

host1x

rk: revert to v3.10

2015-11-11 15:57:28 +08:00

ipu-v3

gpu: ipu-v3: Assign of_node of child platform devices to corresponding ports