Pull non-transparent bridge updates from Jon Mason:
"NTB driver bug fixes to address a missed call to pci_enable_msix,
NTB-RP Link Up issue, Xeon Doorbell errata workaround, ntb_transport
link down race, and correct dmaengine_get/put usage.
Also, clean-ups to remove duplicate defines and document a hardware
errata. Finally, some changes to improve performance"
* tag 'ntb-3.13' of git://github.com/jonmason/ntb:
NTB: Disable interrupts and poll under high load
NTB: Enable Snoop on Primary Side
NTB: Document HW errata
NTB: remove duplicate defines
NTB: correct dmaengine_get/put usage
NTB: Fix ntb_transport link down race
ntb: Fix missed call to pci_enable_msix()
NTB: Fix NTB-RP Link Up
NTB: Xeon Doorbell errata workaround
Enable Snoop from Primary to Secondary side on BAR23 and BAR45 on all
TLPs. Previously, Snoop was only enabled from Secondary to Primary
side. This can have a performance improvement on some workloads.
Also, make the code more obvious about how the link is being enabled.
Signed-off-by: Jon Mason <jon.mason@intel.com>
dmaengine_get() causes the initialization of the per-cpu channel tables.
It needs to be called prior to dma_find_channel().
Initial version by Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Jon Mason <jon.mason@intel.com>
A WARN_ON is being hit in ntb_qp_link_work due to the NTB transport link
being down while the ntb qp link is still active. This is caused by the
transport link being brought down prior to the qp link worker thread
being terminated. To correct this, shutdown the qp's prior to bringing
the transport link down. Also, only call the qp worker thread if it is
in interrupt context, otherwise call the function directly.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Current MSI-X enablement code assumes MSI-Xs were successfully
allocated in case less than requested vectors were available.
That assumption is wrong, since MSI-Xs should be enabled with
a repeated call to pci_enable_msix(). This update fixes this.
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
Signed-off-by: Jon Mason <jon.mason@intel.com>
The Xeon NTB-RP setup, the transparent side does not get a link up/down
interrupt. Since the presence of a NTB device on the transparent side
means that we have a NTB link up, we can work around the lack of an
interrupt by simply calling the link up function to notify the upper
layers.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Modifications to the 14th bit of the B2BDOORBELL register will not be
mirrored to the remote system due to a hardware issue. To get around
the issue, shrink the number of available doorbell bits by 1. The max
number of doorbells was being used as a way to referencing the Link
Doorbell bit. Since this would no longer work, the driver must now
explicitly reference that bit.
This does not affect the xeon_errata_workaround case, as it is not using
the b2bdoorbell register.
Signed-off-by: Jon Mason <jon.mason@intel.com>
PCI core will initialize device MSI/MSI-X capability in
pci_msi_init_pci_dev(). So device driver should use
pci_dev->msi_cap/msix_cap to determine whether the device
support MSI/MSI-X instead of using
pci_find_capability(pci_dev, PCI_CAP_ID_MSI/MSIX).
Access to PCIe device config space again will consume more time.
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Jon Mason <jon.mason@intel.com>
Add support for Non-Transparent Bridge connected to a PCI-E Root Port on
the remote system (also known as NTB-RP mode). This allows for a NTB
enabled system to be connected to a non-NTB enabled system/slot.
Modifications to the registers and BARs/MWs on the Secondary side by the
remote system are reflected into registers on the Primary side for the
local system. Similarly, modifications of registers and BARs/MWs on
Primary side by the local system are reflected into registers on the
Secondary side for the Remote System. This allows communication between
the 2 sides via these registers and BARs/MWs.
Note: there is not a fix for the Xeon Errata (that was already worked
around in NTB-B2B mode) for NTB-RP mode. Due to this limitation, NTB-RP
will not work on the Secondary side with the Xeon Errata workaround
enabled. To get around this, disable the workaround via the
xeon_errata_workaround=0 modparm. However, this can cause the hang
described in the errata.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Many variable names in the NTB driver refer to the primary or secondary
side. However, these variables will be used to access the reverse case
when in NTB-RP mode. Make these names more generic in anticipation of
NTB-RP support.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Allocate and use a DMA engine channel to transmit and receive data over
NTB. If none is allocated, fall back to using the CPU to transfer data.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Correct the issues on NTB that prevented it from working on x86_32 and
modify the Kconfig to allow it to be permitted to be used in that
environment as well.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Add support for new Intel NTB devices on upcoming Xeon hardware. Since
the Xeon hardware design is already in place in the driver, all that is
needed are the new device ids.
Remove the device IDs for NTB devs running in Transparent Bridge mode,
as this driver is not being used for those devices.
Rename the device IDs for NTB devs running in NTB-RP mode to better
identify their usage model. "PS" to denote the Primary Side of NTB, and
"SS" to denote the secondary side. The primary side is the interface
exposed to the local system, and the secondary side is the interface
exposed to the remote system.
Signed-off-by: Jon Mason <jon.mason@intel.com>
The BWD NTB device will drop the link if an error is encountered on the
point-to-point PCI bridge. The link will stay down until all errors are
cleared and the link is re-established. On link down, check to see if
the error is detected, if so do the necessary housekeeping to try and
recover from the error and reestablish the link.
There is a potential race between the 2 NTB devices recovering at the
same time. If the times are synchronized, the link will not recover and the
driver will be stuck in this loop forever. Add a random interval to the
recovery time to prevent this race.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Debugfs was setup in NTB to only have a single debugfs directory. This
resulted in the leaking of debugfs directories and files when multiple
NTB devices were present, due to each device stomping on the variables
containing the previous device's values (thus preventing them from being
freed on cleanup). Correct this by creating a secondary directory of
the PCI BDF for each device present, and nesting the previously existing
information in those directories.
Signed-off-by: Jon Mason <jon.mason@intel.com>
