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Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Browse Source 
Pull arm-soc: soc specific changes (part 2) from Olof Johansson:
 "This adds support for the spear13xx platform, which has first been
  under review a long time ago and finally been completed after generic
  spear work has gone into the clock, dt and pinctrl branches.

  Also a number of updates for the samsung socs are part of this branch."

Fix up trivial conflicts in drivers/gpio/gpio-samsung.c that look much
worse than they are: the exonys5 init code was refactored in commit
fd454997d6 ("gpio: samsung: refactor gpiolib init for exynos4/5"), and
then commit f10590c983 ("ARM: EXYNOS: add GPC4 bank instance") added a
new gpio chip define and did tiny updates to the init code.

So the conflict diff looks like hell, but it's actually a fairly simple
change.

* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits)
  ARM: exynos: fix building with CONFIG_OF disabled
  ARM: EXYNOS: Add AUXDATA for i2c controllers
  ARM: dts: Update device tree source files for EXYNOS5250
  ARM: EXYNOS: Add device tree support for interrupt combiner
  ARM: EXYNOS: Add irq_domain support for interrupt combiner
  ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5
  ARM: EXYNOS: update irqs for EXYNOS5250 SoC
  ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
  ARM: EXYNOS: add GPC4 bank instance
  ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition
  ARM: EXYNOS: Modify the GIC physical address for static io-mapping
  ARM: EXYNOS: Add watchdog timer clock instance
  pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res
  SPEAr: Update MAINTAINERS and Documentation
  SPEAr13xx: Add defconfig
  SPEAr13xx: Add compilation support
  SPEAr13xx: Add dts and dtsi files
  pinctrl: Add SPEAr13xx pinctrl drivers
  pinctrl: SPEAr: Create macro for declaring GPIO PINS
  SPEAr13xx: Add common clock framework support
  ...
This commit is contained in:
Linus Torvalds
2012-05-26 13:05:55 -07:00
parent 84a442b9a1 820f3dd796
commit 30b842889e
81 changed files with 9649 additions and 304 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
Documentation/arm/SPEAr/overview.txt
View File

@@ -8,9 +8,8 @@ Introduction
weblink : http://www.st.com/spear
The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
supported by the 'spear' platform of ARM Linux. Currently SPEAr300,
SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX
series is in progress.
supported by the 'spear' platform of ARM Linux. Currently SPEAr1310,
SPEAr1340, SPEAr300, SPEAr310, SPEAr320 and SPEAr600 SOCs are supported.
Hierarchy in SPEAr is as follows:
@@ -26,33 +25,36 @@ Introduction
- SPEAr600 (SOC)
- SPEAr600 Evaluation Board
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
- SPEAr1300 (SOC)
- SPEAr1310 (SOC)
- SPEAr1310 Evaluation Board
- SPEAr1340 (SOC)
- SPEAr1340 Evaluation Board
Configuration
-------------
A generic configuration is provided for each machine, and can be used as the
default by
make spear600_defconfig
make spear300_defconfig
make spear310_defconfig
make spear320_defconfig
make spear13xx_defconfig
make spear3xx_defconfig
make spear6xx_defconfig
Layout
------
The common files for multiple machine families (SPEAr3XX, SPEAr6XX and
SPEAr13XX) are located in the platform code contained in arch/arm/plat-spear
The common files for multiple machine families (SPEAr3xx, SPEAr6xx and
SPEAr13xx) are located in the platform code contained in arch/arm/plat-spear
with headers in plat/.
Each machine series have a directory with name arch/arm/mach-spear followed by
series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx.
Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
mach-spear* doesn't contains board specific files as they fully support
Flattened Device Tree.
Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c, for
spear6xx is mach-spear6xx/spear6xx.c and for spear13xx family is
mach-spear13xx/spear13xx.c. mach-spear* also contain soc/machine specific
files, like spear1310.c, spear1340.c spear300.c, spear310.c, spear320.c and
spear600.c. mach-spear* doesn't contains board specific files as they fully
support Flattened Device Tree.
Document Author

52
Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt Normal file
View File

@@ -0,0 +1,52 @@
* Samsung Exynos Interrupt Combiner Controller
Samsung's Exynos4 architecture includes a interrupt combiner controller which
can combine interrupt sources as a group and provide a single interrupt request
for the group. The interrupt request from each group are connected to a parent
interrupt controller, such as GIC in case of Exynos4210.
The interrupt combiner controller consists of multiple combiners. Upto eight
interrupt sources can be connected to a combiner. The combiner outputs one
combined interrupt for its eight interrupt sources. The combined interrupt
is usually connected to a parent interrupt controller.
A single node in the device tree is used to describe the interrupt combiner
controller module (which includes multiple combiners). A combiner in the
interrupt controller module shares config/control registers with other
combiners. For example, a 32-bit interrupt enable/disable config register
can accommodate upto 4 interrupt combiners (with each combiner supporting
upto 8 interrupt sources).
Required properties:
- compatible: should be "samsung,exynos4210-combiner".
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: should be <2>. The meaning of the cells are
* First Cell: Combiner Group Number.
* Second Cell: Interrupt number within the group.
- reg: Base address and size of interrupt combiner registers.
- interrupts: The list of interrupts generated by the combiners which are then
connected to a parent interrupt controller. The format of the interrupt
specifier depends in the interrupt parent controller.
Optional properties:
- samsung,combiner-nr: The number of interrupt combiners supported. If this
property is not specified, the default number of combiners is assumed
to be 16.
- interrupt-parent: pHandle of the parent interrupt controller, if not
inherited from the parent node.
Example:
The following is a an example from the Exynos4210 SoC dtsi file.
combiner:interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10440000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};

16
Documentation/devicetree/bindings/arm/spear.txt
View File

@@ -2,25 +2,25 @@ ST SPEAr Platforms Device Tree Bindings
---------------------------------------
Boards with the ST SPEAr600 SoC shall have the following properties:
Required root node property:
compatible = "st,spear600";
Boards with the ST SPEAr300 SoC shall have the following properties:
Required root node property:
compatible = "st,spear300";
Boards with the ST SPEAr310 SoC shall have the following properties:
Required root node property:
compatible = "st,spear310";
Boards with the ST SPEAr320 SoC shall have the following properties:
Required root node property:
compatible = "st,spear320";
Boards with the ST SPEAr1310 SoC shall have the following properties:
Required root node property:
compatible = "st,spear1310";
Boards with the ST SPEAr1340 SoC shall have the following properties:
Required root node property:
compatible = "st,spear1340";

47
Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
View File

@@ -4,6 +4,8 @@ Required properties:
- compatible : "st,spear300-pinmux"
: "st,spear310-pinmux"
: "st,spear320-pinmux"
: "st,spear1310-pinmux"
: "st,spear1340-pinmux"
- reg : Address range of the pinctrl registers
- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
- Its values for SPEAr300:
@@ -89,6 +91,37 @@ For SPEAr320 machines:
"rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
"i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
For SPEAr1310 machines:
"i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp",
"i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp",
"smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp",
"smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp",
"nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp",
"keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp",
"gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp",
"sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp",
"uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp",
"uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp",
"i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp",
"i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp",
"i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp",
"can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp",
"pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp",
"ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp"
For SPEAr1340 machines:
"pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp",
"keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp",
"spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp",
"pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp",
"vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp",
"cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp",
"uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp",
"rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp",
"sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp",
"miphy_dbg_grp", "pcie_grp", "sata_grp"
Valid values for function names are:
For All SPEAr3xx machines:
"firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
@@ -106,3 +139,17 @@ For SPEAr320 machines:
"uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
"can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
"mii0_1", "i2c1", "i2c2"
For SPEAr1310 machines:
"i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
"rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0",
"gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3",
"uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1",
"i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"
For SPEAr1340 machines:
"pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1",
"pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0",
"uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf",
"xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata"

13
MAINTAINERS
View File

@@ -6350,14 +6350,25 @@ F: include/linux/compiler.h
SPEAR PLATFORM SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
S: Maintained
F: arch/arm/plat-spear/
SPEAR13XX MACHINE SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
S: Maintained
F: arch/arm/mach-spear13xx/
SPEAR3XX MACHINE SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
@@ -6366,6 +6377,8 @@ F: arch/arm/mach-spear3xx/
SPEAR6XX MACHINE SUPPORT
M: Rajeev Kumar <rajeev-dlh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
M: Viresh Kumar <viresh.kumar@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear

2
arch/arm/Makefile
View File

@@ -186,6 +186,8 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
machine-$(CONFIG_ARCH_VT8500) := vt8500
machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_FOOTBRIDGE) := footbridge
machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
machine-$(CONFIG_MACH_SPEAR1340) := spear13xx
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx

48
arch/arm/boot/dts/exynos5250-smdk5250.dts
View File

@@ -23,4 +23,52 @@
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
};
i2c@12C60000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpb3 0 2 3 0>,
<&gpb3 1 2 3 0>;
eeprom@50 {
compatible = "samsung,s524ad0xd1";
reg = <0x50>;
};
};
i2c@12C70000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpb3 2 2 3 0>,
<&gpb3 3 2 3 0>;
eeprom@51 {
compatible = "samsung,s524ad0xd1";
reg = <0x51>;
};
};
i2c@12C80000 {
status = "disabled";
};
i2c@12C90000 {
status = "disabled";
};
i2c@12CA0000 {
status = "disabled";
};
i2c@12CB0000 {
status = "disabled";
};
i2c@12CC0000 {
status = "disabled";
};
i2c@12CD0000 {
status = "disabled";
};
};

60
arch/arm/boot/dts/exynos5250.dtsi
View File

@@ -23,11 +23,11 @@
compatible = "samsung,exynos5250";
interrupt-parent = <&gic>;
gic:interrupt-controller@10490000 {
gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10490000 0x1000>, <0x10480000 0x100>;
reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
};
watchdog {
@@ -42,30 +42,6 @@
interrupts = <0 43 0>, <0 44 0>;
};
sdhci@12200000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12200000 0x100>;
interrupts = <0 75 0>;
};
sdhci@12210000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12210000 0x100>;
interrupts = <0 76 0>;
};
sdhci@12220000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12220000 0x100>;
interrupts = <0 77 0>;
};
sdhci@12230000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12230000 0x100>;
interrupts = <0 78 0>;
};
serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
@@ -94,48 +70,64 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
interrupts = <0 56 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
interrupts = <0 57 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
interrupts = <0 58 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
interrupts = <0 59 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CA0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
interrupts = <0 60 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CB0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>;
interrupts = <0 61 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CC0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CC0000 0x100>;
interrupts = <0 62 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CD0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CD0000 0x100>;
interrupts = <0 63 0>;
#address-cells = <1>;
#size-cells = <0>;
};
amba {
@@ -157,13 +149,13 @@
interrupts = <0 35 0>;
};
mdma0: pdma@10800000 {
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
};
mdma1: pdma@11C10000 {
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>;
@@ -242,6 +234,12 @@
#gpio-cells = <4>;
};
gpc4: gpio-controller@114002E0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114002E0 0x20>;
#gpio-cells = <4>;
};
gpd0: gpio-controller@11400160 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400160 0x20>;
@@ -388,19 +386,19 @@
gpv2: gpio-controller@10D10040 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10040 0x20>;
reg = <0x10D10060 0x20>;
#gpio-cells = <4>;
};
gpv3: gpio-controller@10D10060 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10060 0x20>;
reg = <0x10D10080 0x20>;
#gpio-cells = <4>;
};
gpv4: gpio-controller@10D10080 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10080 0x20>;
reg = <0x10D100C0 0x20>;
#gpio-cells = <4>;
};

292
arch/arm/boot/dts/spear1310-evb.dts Normal file
View File

@@ -0,0 +1,292 @@
/*
* DTS file for SPEAr1310 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear1310.dtsi"
/ {
model = "ST SPEAr1310 Evaluation Board";
compatible = "st,spear1310-evb", "st,spear1310";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
pinmux@e0700000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
i2c0-pmx {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
i2s1 {
st,pins = "i2s1_grp";
st,function = "i2s1";
};
gpio {
st,pins = "arm_gpio_grp";
st,function = "arm_gpio";
};
eth {
st,pins = "gmii_grp";
st,function = "gmii";
};
ssp0 {
st,pins = "ssp0_grp";
st,function = "ssp0";
};
kbd {
st,pins = "keyboard_6x6_grp";
st,function = "keyboard";
};
sdhci {
st,pins = "sdhci_grp";
st,function = "sdhci";
};
smi-pmx {
st,pins = "smi_2_chips_grp";
st,function = "smi";
};
uart0 {
st,pins = "uart0_grp";
st,function = "uart0";
};
rs485 {
st,pins = "rs485_0_1_tdm_0_1_grp";
st,function = "rs485_0_1_tdm_0_1";
};
i2c1_2 {
st,pins = "i2c_1_2_grp";
st,function = "i2c_1_2";
};
pci {
st,pins = "pcie0_grp","pcie1_grp",
"pcie2_grp";
st,function = "pci";
};
smii {
st,pins = "smii_0_1_2_grp";
st,function = "smii_0_1_2";
};
nand {
st,pins = "nand_8bit_grp",
"nand_16bit_grp";
st,function = "nand";
};
};
};
ahci@b1000000 {
status = "okay";
};
cf@b2800000 {
status = "okay";
};
dma@ea800000 {
status = "okay";
};
dma@eb000000 {
status = "okay";
};
fsmc: flash@b0000000 {
status = "okay";
};
gmac0: eth@e2000000 {
status = "okay";
};
sdhci@b3000000 {
status = "okay";
};
smi: flash@ea000000 {
status = "okay";
clock-rate=<50000000>;
flash@e6000000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xe6000000 0x800000>;
st,smi-fast-mode;
partition@0 {
label = "xloader";
reg = <0x0 0x10000>;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x40000>;
};
partition@50000 {
label = "linux";
reg = <0x50000 0x2c0000>;
};
partition@310000 {
label = "rootfs";
reg = <0x310000 0x4f0000>;
};
};
};
spi0: spi@e0100000 {
status = "okay";
};
ehci@e4800000 {
status = "okay";
};
ehci@e5800000 {
status = "okay";
};
ohci@e4000000 {
status = "okay";
};
ohci@e5000000 {
status = "okay";
};
apb {
adc@e0080000 {
status = "okay";
};
gpio0: gpio@e0600000 {
status = "okay";
};
gpio1: gpio@e0680000 {
status = "okay";
};
i2c0: i2c@e0280000 {
status = "okay";
};
i2c1: i2c@5cd00000 {
status = "okay";
};
kbd@e0300000 {
linux,keymap = < 0x00000001
0x00010002
0x00020003
0x00030004
0x00040005
0x00050006
0x00060007
0x00070008
0x00080009
0x0100000a
0x0101000c
0x0102000d
0x0103000e
0x0104000f
0x01050010
0x01060011
0x01070012
0x01080013
0x02000014
0x02010015
0x02020016
0x02030017
0x02040018
0x02050019
0x0206001a
0x0207001b
0x0208001c
0x0300001d
0x0301001e
0x0302001f
0x03030020
0x03040021
0x03050022
0x03060023
0x03070024
0x03080025
0x04000026
0x04010027
0x04020028
0x04030029
0x0404002a
0x0405002b
0x0406002c
0x0407002d
0x0408002e
0x0500002f
0x05010030
0x05020031
0x05030032
0x05040033
0x05050034
0x05060035
0x05070036
0x05080037
0x06000038
0x06010039
0x0602003a
0x0603003b
0x0604003c
0x0605003d
0x0606003e
0x0607003f
0x06080040
0x07000041
0x07010042
0x07020043
0x07030044
0x07040045
0x07050046
0x07060047
0x07070048
0x07080049
0x0800004a
0x0801004b
0x0802004c
0x0803004d
0x0804004e
0x0805004f
0x08060050
0x08070051
0x08080052 >;
autorepeat;
st,mode = <0>;
status = "okay";
};
rtc@e0580000 {
status = "okay";
};
serial@e0000000 {
status = "okay";
};
wdt@ec800620 {
status = "okay";
};
};
};
};

184
arch/arm/boot/dts/spear1310.dtsi Normal file
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/*
* DTS file for all SPEAr1310 SoCs
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear13xx.dtsi"
/ {
compatible = "st,spear1310";
ahb {
ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 68 0x4>;
status = "disabled";
};
ahci@b1800000 {
compatible = "snps,spear-ahci";
reg = <0xb1800000 0x10000>;
interrupts = <0 69 0x4>;
status = "disabled";
};
ahci@b4000000 {
compatible = "snps,spear-ahci";
reg = <0xb4000000 0x10000>;
interrupts = <0 70 0x4>;
status = "disabled";
};
gmac1: eth@5c400000 {
compatible = "st,spear600-gmac";
reg = <0x5c400000 0x8000>;
interrupts = <0 95 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
gmac2: eth@5c500000 {
compatible = "st,spear600-gmac";
reg = <0x5c500000 0x8000>;
interrupts = <0 96 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
gmac3: eth@5c600000 {
compatible = "st,spear600-gmac";
reg = <0x5c600000 0x8000>;
interrupts = <0 97 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
gmac4: eth@5c700000 {
compatible = "st,spear600-gmac";
reg = <0x5c700000 0x8000>;
interrupts = <0 98 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
spi1: spi@5d400000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x5d400000 0x1000>;
interrupts = <0 99 0x4>;
status = "disabled";
};
apb {
i2c1: i2c@5cd00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5cd00000 0x1000>;
interrupts = <0 87 0x4>;
status = "disabled";
};
i2c2: i2c@5ce00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5ce00000 0x1000>;
interrupts = <0 88 0x4>;
status = "disabled";
};
i2c3: i2c@5cf00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5cf00000 0x1000>;
interrupts = <0 89 0x4>;
status = "disabled";
};
i2c4: i2c@5d000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d000000 0x1000>;
interrupts = <0 90 0x4>;
status = "disabled";
};
i2c5: i2c@5d100000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d100000 0x1000>;
interrupts = <0 91 0x4>;
status = "disabled";
};
i2c6: i2c@5d200000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d200000 0x1000>;
interrupts = <0 92 0x4>;
status = "disabled";
};
i2c7: i2c@5d300000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d300000 0x1000>;
interrupts = <0 93 0x4>;
status = "disabled";
};
serial@5c800000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5c800000 0x1000>;
interrupts = <0 82 0x4>;
status = "disabled";
};
serial@5c900000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5c900000 0x1000>;
interrupts = <0 83 0x4>;
status = "disabled";
};
serial@5ca00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5ca00000 0x1000>;
interrupts = <0 84 0x4>;
status = "disabled";
};
serial@5cb00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5cb00000 0x1000>;
interrupts = <0 85 0x4>;
status = "disabled";
};
serial@5cc00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5cc00000 0x1000>;
interrupts = <0 86 0x4>;
status = "disabled";
};
thermal@e07008c4 {
st,thermal-flags = <0x7000>;
};
};
};
};

308
arch/arm/boot/dts/spear1340-evb.dts Normal file
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/*
* DTS file for SPEAr1340 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear1340.dtsi"
/ {
model = "ST SPEAr1340 Evaluation Board";
compatible = "st,spear1340-evb", "st,spear1340";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
pinmux@e0700000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
pads_as_gpio {
st,pins = "pads_as_gpio_grp";
st,function = "pads_as_gpio";
};
fsmc {
st,pins = "fsmc_8bit_grp";
st,function = "fsmc";
};
kbd {
st,pins = "keyboard_row_col_grp",
"keyboard_col5_grp";
st,function = "keyboard";
};
uart0 {
st,pins = "uart0_grp", "uart0_enh_grp";
st,function = "uart0";
};
i2c0-pmx {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
i2c1-pmx {
st,pins = "i2c1_grp";
st,function = "i2c1";
};
spdif-in {
st,pins = "spdif_in_grp";
st,function = "spdif_in";
};
spdif-out {
st,pins = "spdif_out_grp";
st,function = "spdif_out";
};
ssp0 {
st,pins = "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs3_grp";
st,function = "ssp0";
};
pwm {
st,pins = "pwm2_grp", "pwm3_grp";
st,function = "pwm";
};
smi-pmx {
st,pins = "smi_grp";
st,function = "smi";
};
i2s {
st,pins = "i2s_in_grp", "i2s_out_grp";
st,function = "i2s";
};
gmac {
st,pins = "gmii_grp", "rgmii_grp";
st,function = "gmac";
};
cam3 {
st,pins = "cam3_grp";
st,function = "cam3";
};
cec0 {
st,pins = "cec0_grp";
st,function = "cec0";
};
cec1 {
st,pins = "cec1_grp";
st,function = "cec1";
};
sdhci {
st,pins = "sdhci_grp";
st,function = "sdhci";
};
clcd {
st,pins = "clcd_grp";
st,function = "clcd";
};
sata {
st,pins = "sata_grp";
st,function = "sata";
};
};
};
dma@ea800000 {
status = "okay";
};
dma@eb000000 {
status = "okay";
};
fsmc: flash@b0000000 {
status = "okay";
};
gmac0: eth@e2000000 {
status = "okay";
};
sdhci@b3000000 {
status = "okay";
};
smi: flash@ea000000 {
status = "okay";
clock-rate=<50000000>;
flash@e6000000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xe6000000 0x800000>;
st,smi-fast-mode;
partition@0 {
label = "xloader";
reg = <0x0 0x10000>;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x40000>;
};
partition@50000 {
label = "linux";
reg = <0x50000 0x2c0000>;
};
partition@310000 {
label = "rootfs";
reg = <0x310000 0x4f0000>;
};
};
};
spi0: spi@e0100000 {
status = "okay";
};
ehci@e4800000 {
status = "okay";
};
ehci@e5800000 {
status = "okay";
};
ohci@e4000000 {
status = "okay";
};
ohci@e5000000 {
status = "okay";
};
apb {
adc@e0080000 {
status = "okay";
};
gpio0: gpio@e0600000 {
status = "okay";
};
gpio1: gpio@e0680000 {
status = "okay";
};
i2c0: i2c@e0280000 {
status = "okay";
};
i2c1: i2c@b4000000 {
status = "okay";
};
kbd@e0300000 {
linux,keymap = < 0x00000001
0x00010002
0x00020003
0x00030004
0x00040005
0x00050006
0x00060007
0x00070008
0x00080009
0x0100000a
0x0101000c
0x0102000d
0x0103000e
0x0104000f
0x01050010
0x01060011
0x01070012
0x01080013
0x02000014
0x02010015
0x02020016
0x02030017
0x02040018
0x02050019
0x0206001a
0x0207001b
0x0208001c
0x0300001d
0x0301001e
0x0302001f
0x03030020
0x03040021
0x03050022
0x03060023
0x03070024
0x03080025
0x04000026
0x04010027
0x04020028
0x04030029
0x0404002a
0x0405002b
0x0406002c
0x0407002d
0x0408002e
0x0500002f
0x05010030
0x05020031
0x05030032
0x05040033
0x05050034
0x05060035
0x05070036
0x05080037
0x06000038
0x06010039
0x0602003a
0x0603003b
0x0604003c
0x0605003d
0x0606003e
0x0607003f
0x06080040
0x07000041
0x07010042
0x07020043
0x07030044
0x07040045
0x07050046
0x07060047
0x07070048
0x07080049
0x0800004a
0x0801004b
0x0802004c
0x0803004d
0x0804004e
0x0805004f
0x08060050
0x08070051
0x08080052 >;
autorepeat;
st,mode = <0>;
status = "okay";
};
rtc@e0580000 {
status = "okay";
};
serial@e0000000 {
status = "okay";
};
serial@b4100000 {
status = "okay";
};
wdt@ec800620 {
status = "okay";
};
};
};
};

56
arch/arm/boot/dts/spear1340.dtsi Normal file
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/*
* DTS file for all SPEAr1340 SoCs
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear13xx.dtsi"
/ {
compatible = "st,spear1340";
ahb {
ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 72 0x4>;
status = "disabled";
};
spi1: spi@5d400000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x5d400000 0x1000>;
interrupts = <0 99 0x4>;
status = "disabled";
};
apb {
i2c1: i2c@b4000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xb4000000 0x1000>;
interrupts = <0 104 0x4>;
status = "disabled";
};
serial@b4100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb4100000 0x1000>;
interrupts = <0 105 0x4>;
status = "disabled";
};
thermal@e07008c4 {
st,thermal-flags = <0x2a00>;
};
};
};
};

262
arch/arm/boot/dts/spear13xx.dtsi Normal file
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@@ -0,0 +1,262 @@
/*
* DTS file for all SPEAr13xx SoCs
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&L2>;
};
};
gic: interrupt-controller@ec801000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = < 0xec801000 0x1000 >,
< 0xec800100 0x0100 >;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 8 0x04
0 9 0x04>;
};
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0xed000000 0x1000>;
cache-unified;
cache-level = <2>;
};
memory {
name = "memory";
device_type = "memory";
reg = <0 0x40000000>;
};
chosen {
bootargs = "console=ttyAMA0,115200";
};
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
0xb0000000 0xb0000000 0x10000000
0xe0000000 0xe0000000 0x10000000>;
sdhci@b3000000 {
compatible = "st,sdhci-spear";
reg = <0xb3000000 0x100>;
interrupts = <0 28 0x4>;
status = "disabled";
};
cf@b2800000 {
compatible = "arasan,cf-spear1340";
reg = <0xb2800000 0x100>;
interrupts = <0 29 0x4>;
status = "disabled";
};
dma@ea800000 {
compatible = "snps,dma-spear1340";
reg = <0xea800000 0x1000>;
interrupts = <0 19 0x4>;
status = "disabled";
};
dma@eb000000 {
compatible = "snps,dma-spear1340";
reg = <0xeb000000 0x1000>;
interrupts = <0 59 0x4>;
status = "disabled";
};
fsmc: flash@b0000000 {
compatible = "st,spear600-fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb0000000 0x1000 /* FSMC Register */
0xb0800000 0x0010>; /* NAND Base */
reg-names = "fsmc_regs", "nand_data";
interrupts = <0 20 0x4
0 21 0x4
0 22 0x4
0 23 0x4>;
st,ale-off = <0x20000>;
st,cle-off = <0x10000>;
status = "disabled";
};
gmac0: eth@e2000000 {
compatible = "st,spear600-gmac";
reg = <0xe2000000 0x8000>;
interrupts = <0 23 0x4
0 24 0x4>;
interrupt-names = "macirq", "eth_wake_irq";
status = "disabled";
};
smi: flash@ea000000 {
compatible = "st,spear600-smi";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xea000000 0x1000>;
interrupts = <0 30 0x4>;
status = "disabled";
};
spi0: spi@e0100000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xe0100000 0x1000>;
interrupts = <0 31 0x4>;
status = "disabled";
};
ehci@e4800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe4800000 0x1000>;
interrupts = <0 64 0x4>;
status = "disabled";
};
ehci@e5800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe5800000 0x1000>;
interrupts = <0 66 0x4>;
status = "disabled";
};
ohci@e4000000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe4000000 0x1000>;
interrupts = <0 65 0x4>;
status = "disabled";
};
ohci@e5000000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe5000000 0x1000>;
interrupts = <0 67 0x4>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
0xb0000000 0xb0000000 0x10000000
0xe0000000 0xe0000000 0x10000000>;
gpio0: gpio@e0600000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0600000 0x1000>;
interrupts = <0 24 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio1: gpio@e0680000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0680000 0x1000>;
interrupts = <0 25 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
kbd@e0300000 {
compatible = "st,spear300-kbd";
reg = <0xe0300000 0x1000>;
status = "disabled";
};
i2c0: i2c@e0280000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xe0280000 0x1000>;
interrupts = <0 41 0x4>;
status = "disabled";
};
rtc@e0580000 {
compatible = "st,spear-rtc";
reg = <0xe0580000 0x1000>;
interrupts = <0 36 0x4>;
status = "disabled";
};
serial@e0000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xe0000000 0x1000>;
interrupts = <0 36 0x4>;
status = "disabled";
};
adc@e0080000 {
compatible = "st,spear600-adc";
reg = <0xe0080000 0x1000>;
interrupts = <0 44 0x4>;
status = "disabled";
};
timer@e0380000 {
compatible = "st,spear-timer";
reg = <0xe0380000 0x400>;
interrupts = <0 37 0x4>;
};
timer@ec800600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xec800600 0x20>;
interrupts = <1 13 0x301>;
};
wdt@ec800620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0xec800620 0x20>;
status = "disabled";
};
thermal@e07008c4 {
compatible = "st,thermal-spear1340";
reg = <0xe07008c4 0x4>;
};
};
};
};

95
arch/arm/configs/spear13xx_defconfig Normal file
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CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
# CONFIG_SWP_EMULATE is not set
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_ATA=y
# CONFIG_SATA_PMP is not set
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_PATA_ARASAN_CF=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
CONFIG_STMMAC_ETH=y
# CONFIG_WLAN is not set
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_SPEAR=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_RAW_DRIVER=y
CONFIG_MAX_RAW_DEVS=8192
CONFIG_I2C=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_MPCORE_WATCHDOG=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SPEAR=y
CONFIG_RTC_CLASS=y
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC=y
CONFIG_DMATEST=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_AUTOFS4_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_INFO=y

14
arch/arm/mach-exynos/Kconfig
View File

@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
bool "SAMSUNG EXYNOS5250"
default y
depends on ARCH_EXYNOS5
select SAMSUNG_DMADEV
help
Enable EXYNOS5250 SoC support
@@ -70,7 +71,7 @@ config EXYNOS4_MCT
help
Use MCT (Multi Core Timer) as kernel timers
config EXYNOS4_DEV_DMA
config EXYNOS_DEV_DMA
bool
help
Compile in amba device definitions for DMA controller
@@ -80,6 +81,11 @@ config EXYNOS4_DEV_AHCI
help
Compile in platform device definitions for AHCI
config EXYNOS_DEV_DRM
bool
help
Compile in platform device definitions for core DRM device
config EXYNOS4_SETUP_FIMD0
bool
help
@@ -161,7 +167,7 @@ config EXYNOS4_SETUP_USB_PHY
help
Common setup code for USB PHY controller
config EXYNOS4_SETUP_SPI
config EXYNOS_SETUP_SPI
bool
help
Common setup code for SPI GPIO configurations.
@@ -224,7 +230,7 @@ config MACH_ARMLEX4210
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select EXYNOS4_DEV_AHCI
select EXYNOS4_DEV_DMA
select EXYNOS_DEV_DMA
select EXYNOS4_SETUP_SDHCI
help
Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@@ -362,7 +368,7 @@ config MACH_SMDK4212
select SAMSUNG_DEV_KEYPAD
select SAMSUNG_DEV_PWM
select EXYNOS_DEV_SYSMMU
select EXYNOS4_DEV_DMA
select EXYNOS_DEV_DMA
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C7

7
arch/arm/mach-exynos/Makefile
View File

@@ -50,10 +50,11 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
obj-y += dev-uart.o
obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
obj-$(CONFIG_EXYNOS_DEV_DRM) += dev-drm.o
obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
@@ -68,4 +69,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
obj-$(CONFIG_EXYNOS4_SETUP_SPI) += setup-spi.o
obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o

3
arch/arm/mach-exynos/Makefile.boot
View File

@@ -1,2 +1,5 @@
zreladdr-y += 0x40008000
params_phys-y := 0x40000100
dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb

10
arch/arm/mach-exynos/clock-exynos4212.c
View File

@@ -92,6 +92,16 @@ static struct clk init_clocks_off[] = {
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.enable = exynos4212_clk_ip_isp1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.0",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.1",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 3),
}
};

51
arch/arm/mach-exynos/clock-exynos5.c
View File

@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
};
static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
.clk = {
.name = "mout_bpll_fout",
},
.sources = &clk_src_bpll_fout,
.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
};
static struct clk *exynos5_clk_src_bpll_list[] = {
[0] = &clk_fin_bpll,
[1] = &exynos5_clk_mout_bpll_fout.clk,
};
static struct clksrc_sources exynos5_clk_src_bpll = {
.sources = exynos5_clk_src_bpll_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
};
static struct clksrc_clk exynos5_clk_mout_bpll = {
.clk = {
.name = "mout_bpll",
},
.sources = &clk_src_bpll,
.sources = &exynos5_clk_src_bpll,
.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
};
@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
};
static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
.clk = {
.name = "mout_mpll_fout",
},
.sources = &clk_src_mpll_fout,
.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
};
static struct clk *exynos5_clk_src_mpll_list[] = {
[0] = &clk_fin_mpll,
[1] = &exynos5_clk_mout_mpll_fout.clk,
};
static struct clksrc_sources exynos5_clk_src_mpll = {
.sources = exynos5_clk_src_mpll_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
};
struct clksrc_clk exynos5_clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
},
.sources = &clk_src_mpll,
.sources = &exynos5_clk_src_mpll,
.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
};
@@ -473,6 +509,11 @@ static struct clk exynos5_init_clocks_off[] = {
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "watchdog",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "hsmmc",
.devname = "exynos4-sdhci.0",
@@ -1031,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mout_apll,
&exynos5_clk_sclk_apll,
&exynos5_clk_mout_bpll,
&exynos5_clk_mout_bpll_fout,
&exynos5_clk_mout_bpll_user,
&exynos5_clk_mout_cpll,
&exynos5_clk_mout_epll,
&exynos5_clk_mout_mpll,
&exynos5_clk_mout_mpll_fout,
&exynos5_clk_mout_mpll_user,
&exynos5_clk_vpllsrc,
&exynos5_clk_sclk_vpll,
@@ -1098,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = {
&exynos5_clk_sclk_hdmi27m,
&exynos5_clk_sclk_hdmiphy,
&clk_fout_bpll,
&clk_fout_bpll_div2,
&clk_fout_cpll,
&clk_fout_mpll_div2,
&exynos5_clk_armclk,
};
@@ -1263,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
clk_fout_apll.ops = &exynos5_fout_apll_ops;
clk_fout_bpll.rate = bpll;
clk_fout_bpll_div2.rate = bpll >> 1;
clk_fout_cpll.rate = cpll;
clk_fout_mpll.rate = mpll;
clk_fout_mpll_div2.rate = mpll >> 1;
clk_fout_epll.rate = epll;
clk_fout_vpll.rate = vpll;

182
arch/arm/mach-exynos/common.c
View File

@@ -19,6 +19,9 @@
#include <linux/serial_core.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
@@ -265,12 +268,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
}, {
.virtual = (unsigned long)S5P_VA_GIC_CPU,
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
.length = SZ_64K,
.length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_DIST,
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
.length = SZ_64K,
.length = SZ_4K,
.type = MT_DEVICE,
},
};
@@ -399,6 +402,7 @@ struct combiner_chip_data {
void __iomem *base;
};
static struct irq_domain *combiner_irq_domain;
static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
static inline void __iomem *combiner_base(struct irq_data *data)
@@ -411,14 +415,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
static void combiner_mask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->irq % 32);
u32 mask = 1 << (data->hwirq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}
static void combiner_unmask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->irq % 32);
u32 mask = 1 << (data->hwirq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}
@@ -474,49 +478,131 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
irq_set_chained_handler(irq, combiner_handle_cascade_irq);
}
static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
unsigned int irq_start)
static void __init combiner_init_one(unsigned int combiner_nr,
void __iomem *base)
{
unsigned int i;
unsigned int max_nr;
if (soc_is_exynos5250())
max_nr = EXYNOS5_MAX_COMBINER_NR;
else
max_nr = EXYNOS4_MAX_COMBINER_NR;
if (combiner_nr >= max_nr)
BUG();
combiner_data[combiner_nr].base = base;
combiner_data[combiner_nr].irq_offset = irq_start;
combiner_data[combiner_nr].irq_offset = irq_find_mapping(
combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
/* Disable all interrupts */
__raw_writel(combiner_data[combiner_nr].irq_mask,
base + COMBINER_ENABLE_CLEAR);
}
/* Setup the Linux IRQ subsystem */
#ifdef CONFIG_OF
static int combiner_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq,
unsigned int *out_type)
{
if (d->of_node != controller)
return -EINVAL;
for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+ MAX_IRQ_IN_COMBINER; i++) {
irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
irq_set_chip_data(i, &combiner_data[combiner_nr]);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
if (intsize < 2)
return -EINVAL;
*out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
*out_type = 0;
return 0;
}
#else
static int combiner_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq,
unsigned int *out_type)
{
return -EINVAL;
}
#endif
static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
irq_set_chip_data(irq, &combiner_data[hw >> 3]);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
return 0;
}
static struct irq_domain_ops combiner_irq_domain_ops = {
.xlate = combiner_irq_domain_xlate,
.map = combiner_irq_domain_map,
};
void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
{
int i, irq, irq_base;
unsigned int max_nr, nr_irq;
if (np) {
if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
pr_warning("%s: number of combiners not specified, "
"setting default as %d.\n",
__func__, EXYNOS4_MAX_COMBINER_NR);
max_nr = EXYNOS4_MAX_COMBINER_NR;
}
} else {
max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
EXYNOS4_MAX_COMBINER_NR;
}
nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
if (IS_ERR_VALUE(irq_base)) {
irq_base = COMBINER_IRQ(0, 0);
pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
}
combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
&combiner_irq_domain_ops, &combiner_data);
if (WARN_ON(!combiner_irq_domain)) {
pr_warning("%s: irq domain init failed\n", __func__);
return;
}
for (i = 0; i < max_nr; i++) {
combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
irq = IRQ_SPI(i);
#ifdef CONFIG_OF
if (np)
irq = irq_of_parse_and_map(np, i);
#endif
combiner_cascade_irq(i, irq);
}
}
#ifdef CONFIG_OF
int __init combiner_of_init(struct device_node *np, struct device_node *parent)
{
void __iomem *combiner_base;
combiner_base = of_iomap(np, 0);
if (!combiner_base) {
pr_err("%s: failed to map combiner registers\n", __func__);
return -ENXIO;
}
combiner_init(combiner_base, np);
return 0;
}
static const struct of_device_id exynos4_dt_irq_match[] = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
{ .compatible = "samsung,exynos4210-combiner",
.data = combiner_of_init, },
{},
};
#endif
void __init exynos4_init_irq(void)
{
int irq;
unsigned int gic_bank_offset;
gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
@@ -528,12 +614,8 @@ void __init exynos4_init_irq(void)
of_irq_init(exynos4_dt_irq_match);
#endif
for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
}
if (!of_have_populated_dt())
combiner_init(S5P_VA_COMBINER_BASE, NULL);
/*
* The parameters of s5p_init_irq() are for VIC init.
@@ -545,18 +627,9 @@ void __init exynos4_init_irq(void)
void __init exynos5_init_irq(void)
{
int irq;
#ifdef CONFIG_OF
of_irq_init(exynos4_dt_irq_match);
#endif
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
}
/*
* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because EXYNOS4
@@ -565,30 +638,18 @@ void __init exynos5_init_irq(void)
s5p_init_irq(NULL, 0);
}
struct bus_type exynos4_subsys = {
.name = "exynos4-core",
.dev_name = "exynos4-core",
};
struct bus_type exynos5_subsys = {
.name = "exynos5-core",
.dev_name = "exynos5-core",
struct bus_type exynos_subsys = {
.name = "exynos-core",
.dev_name = "exynos-core",
};
static struct device exynos4_dev = {
.bus = &exynos4_subsys,
};
static struct device exynos5_dev = {
.bus = &exynos5_subsys,
.bus = &exynos_subsys,
};
static int __init exynos_core_init(void)
{
if (soc_is_exynos5250())
return subsys_system_register(&exynos5_subsys, NULL);
else
return subsys_system_register(&exynos4_subsys, NULL);
return subsys_system_register(&exynos_subsys, NULL);
}
core_initcall(exynos_core_init);
@@ -675,10 +736,7 @@ static int __init exynos_init(void)
{
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
if (soc_is_exynos5250())
return device_register(&exynos5_dev);
else
return device_register(&exynos4_dev);
return device_register(&exynos4_dev);
}
/* uart registration process */

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