Ziyuan Xu d963dcb622 phy: rockchip: csi2-dphy[-hw]: Revise initcall when ROCKCHIP_THUNDER_BOOT_ISP=y ...

The csi2-dphy depends on csi2-dphy-hw, assign different levels to them.
No need to pay attention to INITCALL_ASYNC.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Ieda3c7737c4e07af3d9664ceee8868ba55dbefbe

2025-06-30 07:36:41 +00:00

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allwinner

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amlogic

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broadcom

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cadence

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freescale

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hisilicon

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ingenic

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intel

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lantiq

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marvell

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mediatek

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microchip

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motorola

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mscc

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qualcomm

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ralink

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renesas

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rockchip

phy: rockchip: csi2-dphy[-hw]: Revise initcall when ROCKCHIP_THUNDER_BOOT_ISP=y

2025-06-30 07:36:41 +00:00

samsung

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socionext

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st

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sunplus

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tegra

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ti

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xilinx

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Kconfig

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Makefile

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phy-can-transceiver.c

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phy-core-mipi-dphy.c

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phy-core.c

phy: core: Call phy_core_init() early when CONFIG_INITCALL_ASYNC=y

2025-04-21 02:19:49 +00:00

phy-lgm-usb.c

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phy-lpc18xx-usb-otg.c

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phy-pistachio-usb.c

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phy-xgene.c

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