Files
Elaine Zhang a56129cb0c Revert "clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228"
This reverts commit a3f77b5d16.

RK3228 Only GPLL and CPLL, GPLL is a common clock, does not allow dclk_vop
to change its frequency, CPLL is used by GMAC, if dclk_vop use
CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags will
affect the GMAC function.

Change-Id: I2c959a19f115b34720364586c374fc6e01fc8eb4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2025-01-24 09:58:23 +00:00
..
2025-01-10 17:48:57 +08:00