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splitmodes
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4 Commits

Author SHA1 Message Date
Shawn Lin
4ca55c87f9 PCI: rockchip: dw: Add retrain link support 
Speed change is set via dw_pcie_setup_rc(), so if both of links
support gen2 or gen3, auto speed change will happen. However, if
it's not, provide a manual speed change for EP function driver.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ib0dc765452aef0723968c5d48b5b44de24ca141e
 2024-09-25 15:41:56 +08:00
Jon Lin
94664c08ae PCI: dw: rockchip: Support rockchip_dw_pcie_pm_ctrl_for_user 
Some PCIe devices have custom power management measures that do
not rely on the PCIe framework, such as PCIe wifi, which rely on
the reset of the PCIe controller to avoid or solve potential fault
problems.

Change-Id: I7bdb0bd9edfb837a03a12790521e71adc6cd99fe
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2024-05-22 17:22:24 +08:00
Jon Lin
daf69def71 PCI: aspm_ext: Supoprt to check l1ss state 
Change-Id: I585d01908751cefb66935951d42cd854299469fa
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2024-04-08 19:56:14 +08:00
Jon Lin
d591c3f6ef PCI: Add ROCKCHIP PCIe ASPM interface 
Change-Id: I1156bd10e352145d745899067bf43afda92d5a30
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2022-06-22 15:03:47 +08:00