Commit Graph

9 Commits

Author SHA1 Message Date
Zhihuan He
58231cec6b memory: rockchip: dsmc: fix io width config error
The io_width in diff cs should set the same value at the same time.

Change-Id: I2a872ba487bde9aa56f0a3490acbb526a1521475
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2024-12-20 16:04:55 +08:00
Zhihuan He
629b36c6b3 memory: rockchip: dsmc: set 0.5x refresh rate allow for xccela psram
Change-Id: I3195579b8c1d597f25e0a9711cd3edc5a6599ab4
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2024-12-20 16:04:55 +08:00
Zhihuan He
a921bd7a8f memory: dsmc: fix bug in multi cs and region
Change-Id: I792667c6a4a7e9f120da29b1fef19cbd2b40ed9e
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2024-10-22 17:24:18 +08:00
Zhihuan He
afd515fb5e memory: rockchip: dsmc: add data training for dll
Change-Id: I8b54fd9276f2680fbc3b2b66c9a81a58c18668cd
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2024-09-06 11:09:17 +08:00
Zhihuan He
4f418e6887 memory: rockchip: dsmc: modify DMA API to interleaved
Change-Id: I5e7404388e8d916ee3e2796bde22ac272ac265d7
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2024-09-06 11:09:17 +08:00
Zhihuan He
06ef7e6dc3 memory: rockchip: dsmc: add dsmc local bus slave driver
Change-Id: Icf4c4abe11595d4069e36265db5441f52593896a
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2024-09-05 20:29:50 +08:00
Zhihuan He
87315bab6b memory: rockchip: dsmc: add rk3506 support
Change-Id: I11459d02100fd388ffeae11685a58ec5620e5bf6
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2024-09-04 17:47:25 +08:00
Zhihuan He
555d39b979 memory: rockchip: dsmc: modify node get
Change-Id: I2f8951da7fa878c6d34b9c9587fb3b4262799e8c
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2024-06-20 19:09:11 +08:00
Zhihuan He
7f06ef1c10 memory: rockchip: add dsmc driver
Change-Id: Ie3a7dbe89b34421d476b91a6021c3e81b10b591f
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2024-06-20 09:14:53 +08:00