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Merge 5.10.148 into android12-5.10-lts
Changes in 5.10.148
nilfs2: fix NULL pointer dereference at nilfs_bmap_lookup_at_level()
nilfs2: fix use-after-free bug of struct nilfs_root
nilfs2: fix leak of nilfs_root in case of writer thread creation failure
nilfs2: replace WARN_ONs by nilfs_error for checkpoint acquisition failure
ceph: don't truncate file in atomic_open
Makefile.extrawarn: Move -Wcast-function-type-strict to W=1
docs: update mediator information in CoC docs
perf tools: Fixup get_current_dir_name() compilation
xsk: Inherit need_wakeup flag for shared sockets
ALSA: pcm: oss: Fix race at SNDCTL_DSP_SYNC
mm: gup: fix the fast GUP race against THP collapse
powerpc/64s/radix: don't need to broadcast IPI for radix pmd collapse flush
fs: fix UAF/GPF bug in nilfs_mdt_destroy
compiler_attributes.h: move __compiletime_{error|warning}
firmware: arm_scmi: Add SCMI PM driver remove routine
dmaengine: xilinx_dma: Fix devm_platform_ioremap_resource error handling
dmaengine: xilinx_dma: cleanup for fetching xlnx,num-fstores property
dmaengine: xilinx_dma: Report error in case of dma_set_mask_and_coherent API failure
ARM: dts: fix Moxa SDIO 'compatible', remove 'sdhci' misnomer
scsi: qedf: Fix a UAF bug in __qedf_probe()
net/ieee802154: fix uninit value bug in dgram_sendmsg
ALSA: hda/hdmi: Fix the converter reuse for the silent stream
um: Cleanup syscall_handler_t cast in syscalls_32.h
um: Cleanup compiler warning in arch/x86/um/tls_32.c
arch: um: Mark the stack non-executable to fix a binutils warning
net: atlantic: fix potential memory leak in aq_ndev_close()
drm/amd/display: update gamut remap if plane has changed
drm/amd/display: skip audio setup when audio stream is enabled
mmc: core: Replace with already defined values for readability
mmc: core: Terminate infinite loop in SD-UHS voltage switch
usb: mon: make mmapped memory read only
USB: serial: ftdi_sio: fix 300 bps rate for SIO
rpmsg: qcom: glink: replace strncpy() with strscpy_pad()
Revert "clk: ti: Stop using legacy clkctrl names for omap4 and 5"
random: restore O_NONBLOCK support
random: clamp credited irq bits to maximum mixed
ALSA: hda: Fix position reporting on Poulsbo
efi: Correct Macmini DMI match in uefi cert quirk
scsi: stex: Properly zero out the passthrough command structure
USB: serial: qcserial: add new usb-id for Dell branded EM7455
random: avoid reading two cache lines on irq randomness
random: use expired timer rather than wq for mixing fast pool
wifi: cfg80211: fix u8 overflow in cfg80211_update_notlisted_nontrans()
wifi: cfg80211/mac80211: reject bad MBSSID elements
wifi: cfg80211: ensure length byte is present before access
wifi: cfg80211: fix BSS refcounting bugs
wifi: cfg80211: avoid nontransmitted BSS list corruption
wifi: mac80211_hwsim: avoid mac80211 warning on bad rate
wifi: mac80211: fix crash in beacon protection for P2P-device
wifi: cfg80211: update hidden BSSes to avoid WARN_ON
Input: xpad - add supported devices as contributed on github
Input: xpad - fix wireless 360 controller breaking after suspend
misc: pci_endpoint_test: Aggregate params checking for xfer
misc: pci_endpoint_test: Fix pci_endpoint_test_{copy,write,read}() panic
Linux 5.10.148
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: Ieced30eaa00066cb2fc36836250f8f0a553f490f
This commit is contained in:
Greg Kroah-Hartman
@@ -34,8 +34,8 @@ Example:
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Use specific request line passing from dma
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For example, MMC request line is 5
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sdhci: sdhci@98e00000 {
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compatible = "moxa,moxart-sdhci";
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mmc: mmc@98e00000 {
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compatible = "moxa,moxart-mmc";
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reg = <0x98e00000 0x5C>;
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interrupts = <5 0>;
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clocks = <&clk_apb>;
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@@ -51,7 +51,7 @@ the Technical Advisory Board (TAB) or other maintainers if you're
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uncertain how to handle situations that come up. It will not be
|
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considered a violation report unless you want it to be. If you are
|
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uncertain about approaching the TAB or any other maintainers, please
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reach out to our conflict mediator, Mishi Choudhary <mishi@linux.com>.
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reach out to our conflict mediator, Joanna Lee <joanna.lee@gesmer.com>.
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In the end, "be kind to each other" is really what the end goal is for
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everybody. We know everyone is human and we all fail at times, but the
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2
Makefile
2
Makefile
@@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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VERSION = 5
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PATCHLEVEL = 10
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SUBLEVEL = 147
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SUBLEVEL = 148
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EXTRAVERSION =
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NAME = Dare mighty things
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@@ -79,7 +79,7 @@
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clocks = <&ref12>;
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};
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&sdhci {
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&mmc {
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status = "okay";
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};
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@@ -93,8 +93,8 @@
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clock-names = "PCLK";
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};
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sdhci: sdhci@98e00000 {
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compatible = "moxa,moxart-sdhci";
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mmc: mmc@98e00000 {
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compatible = "moxa,moxart-mmc";
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reg = <0x98e00000 0x5C>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_apb>;
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@@ -997,15 +997,6 @@ pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long addre
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pmd = *pmdp;
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pmd_clear(pmdp);
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/*
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* pmdp collapse_flush need to ensure that there are no parallel gup
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* walk after this call. This is needed so that we can have stable
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* page ref count when collapsing a page. We don't allow a collapse page
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* if we have gup taken on the page. We can ensure that by sending IPI
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* because gup walk happens with IRQ disabled.
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*/
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serialize_against_pte_lookup(vma->vm_mm);
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radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
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return pmd;
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@@ -131,10 +131,18 @@ export LDS_ELF_FORMAT := $(ELF_FORMAT)
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# The wrappers will select whether using "malloc" or the kernel allocator.
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LINK_WRAPS = -Wl,--wrap,malloc -Wl,--wrap,free -Wl,--wrap,calloc
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# Avoid binutils 2.39+ warnings by marking the stack non-executable and
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# ignorning warnings for the kallsyms sections.
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LDFLAGS_EXECSTACK = -z noexecstack
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ifeq ($(CONFIG_LD_IS_BFD),y)
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LDFLAGS_EXECSTACK += $(call ld-option,--no-warn-rwx-segments)
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endif
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LD_FLAGS_CMDLINE = $(foreach opt,$(KBUILD_LDFLAGS),-Wl,$(opt))
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# Used by link-vmlinux.sh which has special support for um link
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export CFLAGS_vmlinux := $(LINK-y) $(LINK_WRAPS) $(LD_FLAGS_CMDLINE)
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export LDFLAGS_vmlinux := $(LDFLAGS_EXECSTACK)
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# When cleaning we don't include .config, so we don't include
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# TT or skas makefiles and don't clean skas_ptregs.h.
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@@ -6,10 +6,9 @@
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#include <asm/unistd.h>
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#include <sysdep/ptrace.h>
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typedef long syscall_handler_t(struct pt_regs);
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typedef long syscall_handler_t(struct syscall_args);
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extern syscall_handler_t *sys_call_table[];
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#define EXECUTE_SYSCALL(syscall, regs) \
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((long (*)(struct syscall_args)) \
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(*sys_call_table[syscall]))(SYSCALL_ARGS(®s->regs))
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((*sys_call_table[syscall]))(SYSCALL_ARGS(®s->regs))
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@@ -65,9 +65,6 @@ static int get_free_idx(struct task_struct* task)
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struct thread_struct *t = &task->thread;
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int idx;
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if (!t->arch.tls_array)
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return GDT_ENTRY_TLS_MIN;
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for (idx = 0; idx < GDT_ENTRY_TLS_ENTRIES; idx++)
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if (!t->arch.tls_array[idx].present)
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return idx + GDT_ENTRY_TLS_MIN;
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@@ -240,9 +237,6 @@ static int get_tls_entry(struct task_struct *task, struct user_desc *info,
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{
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struct thread_struct *t = &task->thread;
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if (!t->arch.tls_array)
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goto clear;
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if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
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return -EINVAL;
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@@ -62,7 +62,7 @@ quiet_cmd_vdso = VDSO $@
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-Wl,-T,$(filter %.lds,$^) $(filter %.o,$^) && \
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sh $(srctree)/$(src)/checkundef.sh '$(NM)' '$@'
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VDSO_LDFLAGS = -fPIC -shared -Wl,--hash-style=sysv
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VDSO_LDFLAGS = -fPIC -shared -Wl,--hash-style=sysv -z noexecstack
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GCOV_PROFILE := n
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#
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@@ -981,8 +981,8 @@ static const struct memdev {
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#endif
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[5] = { "zero", 0666, &zero_fops, 0 },
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[7] = { "full", 0666, &full_fops, 0 },
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[8] = { "random", 0666, &random_fops, 0 },
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[9] = { "urandom", 0666, &urandom_fops, 0 },
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[8] = { "random", 0666, &random_fops, FMODE_NOWAIT },
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[9] = { "urandom", 0666, &urandom_fops, FMODE_NOWAIT },
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#ifdef CONFIG_PRINTK
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[11] = { "kmsg", 0644, &kmsg_fops, 0 },
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#endif
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@@ -902,20 +902,23 @@ void __cold add_bootloader_randomness(const void *buf, size_t len)
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EXPORT_SYMBOL_GPL(add_bootloader_randomness);
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struct fast_pool {
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struct work_struct mix;
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unsigned long pool[4];
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unsigned long last;
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unsigned int count;
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struct timer_list mix;
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};
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static void mix_interrupt_randomness(struct timer_list *work);
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static DEFINE_PER_CPU(struct fast_pool, irq_randomness) = {
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#ifdef CONFIG_64BIT
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#define FASTMIX_PERM SIPHASH_PERMUTATION
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.pool = { SIPHASH_CONST_0, SIPHASH_CONST_1, SIPHASH_CONST_2, SIPHASH_CONST_3 }
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.pool = { SIPHASH_CONST_0, SIPHASH_CONST_1, SIPHASH_CONST_2, SIPHASH_CONST_3 },
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#else
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#define FASTMIX_PERM HSIPHASH_PERMUTATION
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.pool = { HSIPHASH_CONST_0, HSIPHASH_CONST_1, HSIPHASH_CONST_2, HSIPHASH_CONST_3 }
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.pool = { HSIPHASH_CONST_0, HSIPHASH_CONST_1, HSIPHASH_CONST_2, HSIPHASH_CONST_3 },
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#endif
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.mix = __TIMER_INITIALIZER(mix_interrupt_randomness, 0)
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};
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/*
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@@ -957,7 +960,7 @@ int __cold random_online_cpu(unsigned int cpu)
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}
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#endif
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static void mix_interrupt_randomness(struct work_struct *work)
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static void mix_interrupt_randomness(struct timer_list *work)
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{
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struct fast_pool *fast_pool = container_of(work, struct fast_pool, mix);
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/*
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@@ -988,7 +991,7 @@ static void mix_interrupt_randomness(struct work_struct *work)
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local_irq_enable();
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mix_pool_bytes(pool, sizeof(pool));
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credit_init_bits(max(1u, (count & U16_MAX) / 64));
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credit_init_bits(clamp_t(unsigned int, (count & U16_MAX) / 64, 1, sizeof(pool) * 8));
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memzero_explicit(pool, sizeof(pool));
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}
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@@ -1011,10 +1014,11 @@ void add_interrupt_randomness(int irq)
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if (new_count < 1024 && !time_is_before_jiffies(fast_pool->last + HZ))
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return;
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if (unlikely(!fast_pool->mix.func))
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INIT_WORK(&fast_pool->mix, mix_interrupt_randomness);
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fast_pool->count |= MIX_INFLIGHT;
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queue_work_on(raw_smp_processor_id(), system_highpri_wq, &fast_pool->mix);
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if (!timer_pending(&fast_pool->mix)) {
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fast_pool->mix.expires = jiffies;
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add_timer_on(&fast_pool->mix, raw_smp_processor_id());
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}
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}
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EXPORT_SYMBOL_GPL(add_interrupt_randomness);
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@@ -1306,6 +1310,11 @@ static ssize_t random_read_iter(struct kiocb *kiocb, struct iov_iter *iter)
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{
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int ret;
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if (!crng_ready() &&
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((kiocb->ki_flags & (IOCB_NOWAIT | IOCB_NOIO)) ||
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(kiocb->ki_filp->f_flags & O_NONBLOCK)))
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return -EAGAIN;
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ret = wait_for_random_bytes();
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if (ret != 0)
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return ret;
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@@ -56,7 +56,7 @@ static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
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};
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static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
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"abe-clkctrl:0018:26",
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"abe_cm:clk:0018:26",
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"pad_clks_ck",
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"slimbus_clk",
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NULL,
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@@ -76,7 +76,7 @@ static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
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};
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static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
|
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"abe-clkctrl:0020:26",
|
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"abe_cm:clk:0020:26",
|
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"pad_clks_ck",
|
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"slimbus_clk",
|
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NULL,
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@@ -89,7 +89,7 @@ static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
|
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};
|
||||
|
||||
static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
|
||||
"abe-clkctrl:0028:26",
|
||||
"abe_cm:clk:0028:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
@@ -102,7 +102,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst =
|
||||
};
|
||||
|
||||
static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
|
||||
"abe-clkctrl:0030:26",
|
||||
"abe_cm:clk:0030:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
@@ -115,7 +115,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst =
|
||||
};
|
||||
|
||||
static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
|
||||
"abe-clkctrl:0038:26",
|
||||
"abe_cm:clk:0038:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
@@ -183,18 +183,18 @@ static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst =
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
|
||||
{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
|
||||
{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
|
||||
{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
|
||||
{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
|
||||
{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
|
||||
{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
|
||||
{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
|
||||
{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
|
||||
{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0040:8" },
|
||||
{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
|
||||
{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
|
||||
{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
|
||||
{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
|
||||
{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
|
||||
{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" },
|
||||
{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
|
||||
{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
|
||||
{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
|
||||
{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" },
|
||||
{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
|
||||
{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
|
||||
{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
|
||||
{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
|
||||
{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
|
||||
{ 0 },
|
||||
};
|
||||
@@ -287,7 +287,7 @@ static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
|
||||
{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" },
|
||||
{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
@@ -320,7 +320,7 @@ static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" },
|
||||
{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
@@ -336,7 +336,7 @@ static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" },
|
||||
{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
@@ -372,12 +372,12 @@ static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
|
||||
};
|
||||
|
||||
static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
|
||||
"l3-init-clkctrl:0038:24",
|
||||
"l3_init_cm:clk:0038:24",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
|
||||
"l3-init-clkctrl:0038:25",
|
||||
"l3_init_cm:clk:0038:25",
|
||||
NULL,
|
||||
};
|
||||
|
||||
@@ -418,7 +418,7 @@ static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initcon
|
||||
};
|
||||
|
||||
static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
|
||||
"l3-init-clkctrl:0040:24",
|
||||
"l3_init_cm:clk:0040:24",
|
||||
NULL,
|
||||
};
|
||||
|
||||
@@ -452,14 +452,14 @@ static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __ini
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" },
|
||||
{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" },
|
||||
{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" },
|
||||
{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" },
|
||||
{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" },
|
||||
{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" },
|
||||
{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
|
||||
{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
|
||||
{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
|
||||
{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
|
||||
{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c0:8" },
|
||||
{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
@@ -530,7 +530,7 @@ static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
|
||||
};
|
||||
|
||||
static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
|
||||
"l4-per-clkctrl:00c0:26",
|
||||
"l4_per_cm:clk:00c0:26",
|
||||
"pad_clks_ck",
|
||||
NULL,
|
||||
};
|
||||
@@ -570,12 +570,12 @@ static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" },
|
||||
{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" },
|
||||
{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" },
|
||||
{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" },
|
||||
{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" },
|
||||
{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" },
|
||||
{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" },
|
||||
{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" },
|
||||
{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" },
|
||||
{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" },
|
||||
{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" },
|
||||
{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" },
|
||||
{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
|
||||
{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
|
||||
{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
|
||||
@@ -588,14 +588,14 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
|
||||
{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
|
||||
{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
|
||||
{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
|
||||
{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" },
|
||||
{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" },
|
||||
{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" },
|
||||
{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" },
|
||||
{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
@@ -630,7 +630,7 @@ static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initcon
|
||||
{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
|
||||
{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
|
||||
{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
|
||||
{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" },
|
||||
{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" },
|
||||
{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
|
||||
{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
|
||||
{ 0 },
|
||||
@@ -644,7 +644,7 @@ static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
|
||||
};
|
||||
|
||||
static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
|
||||
"emu-sys-clkctrl:0000:22",
|
||||
"emu_sys_cm:clk:0000:22",
|
||||
NULL,
|
||||
};
|
||||
|
||||
@@ -662,7 +662,7 @@ static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __init
|
||||
};
|
||||
|
||||
static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
|
||||
"emu-sys-clkctrl:0000:20",
|
||||
"emu_sys_cm:clk:0000:20",
|
||||
NULL,
|
||||
};
|
||||
|
||||
@@ -716,73 +716,73 @@ static struct ti_dt_clk omap44xx_clks[] = {
|
||||
* hwmod support. Once hwmod is removed, these can be removed
|
||||
* also.
|
||||
*/
|
||||
DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
|
||||
DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
|
||||
DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
|
||||
DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
|
||||
DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
|
||||
DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
|
||||
DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
|
||||
DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"),
|
||||
DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"),
|
||||
DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"),
|
||||
DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"),
|
||||
DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"),
|
||||
DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"),
|
||||
DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"),
|
||||
DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"),
|
||||
DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"),
|
||||
DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"),
|
||||
DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"),
|
||||
DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"),
|
||||
DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"),
|
||||
DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"),
|
||||
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
|
||||
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
|
||||
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
|
||||
DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
|
||||
DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
|
||||
DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
|
||||
DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
|
||||
DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
|
||||
DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),
|
||||
DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"),
|
||||
DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"),
|
||||
DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"),
|
||||
DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"),
|
||||
DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"),
|
||||
DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"),
|
||||
DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"),
|
||||
DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"),
|
||||
DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"),
|
||||
DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"),
|
||||
DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"),
|
||||
DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"),
|
||||
DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"),
|
||||
DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"),
|
||||
DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"),
|
||||
DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"),
|
||||
DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"),
|
||||
DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"),
|
||||
DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"),
|
||||
DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"),
|
||||
DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"),
|
||||
DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"),
|
||||
DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
|
||||
DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"),
|
||||
DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),
|
||||
DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"),
|
||||
DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"),
|
||||
DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"),
|
||||
DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"),
|
||||
DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"),
|
||||
DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"),
|
||||
DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"),
|
||||
DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"),
|
||||
DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"),
|
||||
DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"),
|
||||
DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"),
|
||||
DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"),
|
||||
DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"),
|
||||
DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"),
|
||||
DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"),
|
||||
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
|
||||
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
|
||||
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
|
||||
DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"),
|
||||
DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"),
|
||||
DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"),
|
||||
DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"),
|
||||
DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"),
|
||||
DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"),
|
||||
DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"),
|
||||
DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"),
|
||||
DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"),
|
||||
DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"),
|
||||
DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"),
|
||||
DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"),
|
||||
DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"),
|
||||
DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"),
|
||||
DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"),
|
||||
DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"),
|
||||
DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"),
|
||||
DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"),
|
||||
DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"),
|
||||
DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"),
|
||||
DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
|
||||
@@ -50,7 +50,7 @@ static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
|
||||
};
|
||||
|
||||
static const char * const omap5_dmic_gfclk_parents[] __initconst = {
|
||||
"abe-clkctrl:0018:26",
|
||||
"abe_cm:clk:0018:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
@@ -70,7 +70,7 @@ static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
|
||||
};
|
||||
|
||||
static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
|
||||
"abe-clkctrl:0028:26",
|
||||
"abe_cm:clk:0028:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
@@ -83,7 +83,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst =
|
||||
};
|
||||
|
||||
static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
|
||||
"abe-clkctrl:0030:26",
|
||||
"abe_cm:clk:0030:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
@@ -96,7 +96,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst =
|
||||
};
|
||||
|
||||
static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
|
||||
"abe-clkctrl:0038:26",
|
||||
"abe_cm:clk:0038:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
@@ -136,16 +136,16 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst =
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
|
||||
{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
|
||||
{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
|
||||
{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
|
||||
{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
|
||||
{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
|
||||
{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
|
||||
{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
|
||||
{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
|
||||
{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
|
||||
{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
|
||||
{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
|
||||
{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
|
||||
{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
|
||||
{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
|
||||
{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
|
||||
{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
|
||||
{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
|
||||
{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
|
||||
{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
@@ -266,12 +266,12 @@ static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
|
||||
{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
|
||||
{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
|
||||
{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
|
||||
{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
|
||||
{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" },
|
||||
{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
|
||||
{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
|
||||
{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
|
||||
{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
|
||||
{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
|
||||
{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
|
||||
{ OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
|
||||
{ OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
|
||||
{ OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
|
||||
@@ -343,7 +343,7 @@ static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
|
||||
{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
@@ -376,7 +376,7 @@ static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" },
|
||||
{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
@@ -387,7 +387,7 @@ static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
|
||||
};
|
||||
|
||||
static const char * const omap5_mmc1_fclk_parents[] __initconst = {
|
||||
"l3init-clkctrl:0008:24",
|
||||
"l3init_cm:clk:0008:24",
|
||||
NULL,
|
||||
};
|
||||
|
||||
@@ -403,7 +403,7 @@ static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
|
||||
};
|
||||
|
||||
static const char * const omap5_mmc2_fclk_parents[] __initconst = {
|
||||
"l3init-clkctrl:0010:24",
|
||||
"l3init_cm:clk:0010:24",
|
||||
NULL,
|
||||
};
|
||||
|
||||
@@ -428,12 +428,12 @@ static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initcons
|
||||
};
|
||||
|
||||
static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
|
||||
"l3init-clkctrl:0038:24",
|
||||
"l3init_cm:clk:0038:24",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
|
||||
"l3init-clkctrl:0038:25",
|
||||
"l3init_cm:clk:0038:25",
|
||||
NULL,
|
||||
};
|
||||
|
||||
@@ -492,8 +492,8 @@ static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initcons
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
|
||||
{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
|
||||
{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
|
||||
{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
|
||||
{ OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
|
||||
{ OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
|
||||
{ OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
@@ -517,7 +517,7 @@ static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initcon
|
||||
{ OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
|
||||
{ OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
|
||||
{ OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
|
||||
{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
|
||||
{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
|
||||
{ OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
|
||||
{ OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
|
||||
{ 0 },
|
||||
@@ -547,58 +547,58 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
|
||||
static struct ti_dt_clk omap54xx_clks[] = {
|
||||
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
|
||||
DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
|
||||
DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"),
|
||||
DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
|
||||
DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
|
||||
DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
|
||||
DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
|
||||
DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"),
|
||||
DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"),
|
||||
DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"),
|
||||
DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"),
|
||||
DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
|
||||
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
|
||||
DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
|
||||
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
|
||||
DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
|
||||
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
|
||||
DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"),
|
||||
DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"),
|
||||
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"),
|
||||
DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
|
||||
DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
|
||||
DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
|
||||
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
|
||||
DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"),
|
||||
DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"),
|
||||
DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"),
|
||||
DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"),
|
||||
DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"),
|
||||
DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"),
|
||||
DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"),
|
||||
DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"),
|
||||
DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"),
|
||||
DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"),
|
||||
DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"),
|
||||
DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
|
||||
DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
|
||||
DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
|
||||
DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
|
||||
DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
|
||||
DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
|
||||
DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
|
||||
DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
|
||||
DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
|
||||
DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
|
||||
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
|
||||
DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
|
||||
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
|
||||
DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
|
||||
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
|
||||
DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
|
||||
DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
|
||||
DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
|
||||
DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
|
||||
DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
|
||||
DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
|
||||
DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
|
||||
DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
|
||||
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
|
||||
DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
|
||||
DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
|
||||
DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
|
||||
DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
|
||||
DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
|
||||
DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
|
||||
DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
|
||||
DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
|
||||
DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
|
||||
DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
|
||||
DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
|
||||
@@ -511,6 +511,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
|
||||
char *c;
|
||||
u16 soc_mask = 0;
|
||||
|
||||
if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
|
||||
of_node_name_eq(node, "clk"))
|
||||
ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
|
||||
|
||||
addrp = of_get_address(node, 0, NULL, NULL);
|
||||
addr = (u32)of_translate_address(node, addrp);
|
||||
|
||||
|
||||
@@ -3020,9 +3020,10 @@ static int xilinx_dma_probe(struct platform_device *pdev)
|
||||
|
||||
/* Request and map I/O memory */
|
||||
xdev->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(xdev->regs))
|
||||
return PTR_ERR(xdev->regs);
|
||||
|
||||
if (IS_ERR(xdev->regs)) {
|
||||
err = PTR_ERR(xdev->regs);
|
||||
goto disable_clks;
|
||||
}
|
||||
/* Retrieve the DMA engine properties from the device tree */
|
||||
xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
|
||||
xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2;
|
||||
@@ -3050,7 +3051,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
|
||||
if (err < 0) {
|
||||
dev_err(xdev->dev,
|
||||
"missing xlnx,num-fstores property\n");
|
||||
return err;
|
||||
goto disable_clks;
|
||||
}
|
||||
|
||||
err = of_property_read_u32(node, "xlnx,flush-fsync",
|
||||
@@ -3070,7 +3071,11 @@ static int xilinx_dma_probe(struct platform_device *pdev)
|
||||
xdev->ext_addr = false;
|
||||
|
||||
/* Set the dma mask bits */
|
||||
dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
|
||||
err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
|
||||
if (err < 0) {
|
||||
dev_err(xdev->dev, "DMA mask error %d\n", err);
|
||||
goto disable_clks;
|
||||
}
|
||||
|
||||
/* Initialize the DMA engine */
|
||||
xdev->common.dev = &pdev->dev;
|
||||
@@ -3115,7 +3120,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
|
||||
for_each_child_of_node(node, child) {
|
||||
err = xilinx_dma_child_probe(xdev, child);
|
||||
if (err < 0)
|
||||
goto disable_clks;
|
||||
goto error;
|
||||
}
|
||||
|
||||
if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
|
||||
@@ -3150,12 +3155,12 @@ static int xilinx_dma_probe(struct platform_device *pdev)
|
||||
|
||||
return 0;
|
||||
|
||||
disable_clks:
|
||||
xdma_disable_allclks(xdev);
|
||||
error:
|
||||
for (i = 0; i < xdev->dma_config->max_channels; i++)
|
||||
if (xdev->chan[i])
|
||||
xilinx_dma_chan_remove(xdev->chan[i]);
|
||||
disable_clks:
|
||||
xdma_disable_allclks(xdev);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
@@ -112,9 +112,28 @@ static int scmi_pm_domain_probe(struct scmi_device *sdev)
|
||||
scmi_pd_data->domains = domains;
|
||||
scmi_pd_data->num_domains = num_domains;
|
||||
|
||||
dev_set_drvdata(dev, scmi_pd_data);
|
||||
|
||||
return of_genpd_add_provider_onecell(np, scmi_pd_data);
|
||||
}
|
||||
|
||||
static void scmi_pm_domain_remove(struct scmi_device *sdev)
|
||||
{
|
||||
int i;
|
||||
struct genpd_onecell_data *scmi_pd_data;
|
||||
struct device *dev = &sdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
|
||||
of_genpd_del_provider(np);
|
||||
|
||||
scmi_pd_data = dev_get_drvdata(dev);
|
||||
for (i = 0; i < scmi_pd_data->num_domains; i++) {
|
||||
if (!scmi_pd_data->domains[i])
|
||||
continue;
|
||||
pm_genpd_remove(scmi_pd_data->domains[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct scmi_device_id scmi_id_table[] = {
|
||||
{ SCMI_PROTOCOL_POWER, "genpd" },
|
||||
{ },
|
||||
@@ -124,6 +143,7 @@ MODULE_DEVICE_TABLE(scmi, scmi_id_table);
|
||||
static struct scmi_driver scmi_power_domain_driver = {
|
||||
.name = "scmi-power-domain",
|
||||
.probe = scmi_pm_domain_probe,
|
||||
.remove = scmi_pm_domain_remove,
|
||||
.id_table = scmi_id_table,
|
||||
};
|
||||
module_scmi_driver(scmi_power_domain_driver);
|
||||
|
||||
@@ -2047,7 +2047,8 @@ static void dce110_setup_audio_dto(
|
||||
continue;
|
||||
if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
|
||||
continue;
|
||||
if (pipe_ctx->stream_res.audio != NULL) {
|
||||
if (pipe_ctx->stream_res.audio != NULL &&
|
||||
pipe_ctx->stream_res.audio->enabled == false) {
|
||||
struct audio_output audio_output;
|
||||
|
||||
build_audio_output(context, pipe_ctx, &audio_output);
|
||||
@@ -2075,7 +2076,8 @@ static void dce110_setup_audio_dto(
|
||||
if (!dc_is_dp_signal(pipe_ctx->stream->signal))
|
||||
continue;
|
||||
|
||||
if (pipe_ctx->stream_res.audio != NULL) {
|
||||
if (pipe_ctx->stream_res.audio != NULL &&
|
||||
pipe_ctx->stream_res.audio->enabled == false) {
|
||||
struct audio_output audio_output;
|
||||
|
||||
build_audio_output(context, pipe_ctx, &audio_output);
|
||||
|
||||
@@ -1481,6 +1481,7 @@ static void dcn20_update_dchubp_dpp(
|
||||
/* Any updates are handled in dc interface, just need
|
||||
* to apply existing for plane enable / opp change */
|
||||
if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
|
||||
|| pipe_ctx->update_flags.bits.plane_changed
|
||||
|| pipe_ctx->stream->update_flags.bits.gamut_remap
|
||||
|| pipe_ctx->stream->update_flags.bits.out_csc) {
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
|
||||
|
||||
@@ -112,6 +112,8 @@ static const struct xpad_device {
|
||||
u8 xtype;
|
||||
} xpad_device[] = {
|
||||
{ 0x0079, 0x18d4, "GPD Win 2 X-Box Controller", 0, XTYPE_XBOX360 },
|
||||
{ 0x03eb, 0xff01, "Wooting One (Legacy)", 0, XTYPE_XBOX360 },
|
||||
{ 0x03eb, 0xff02, "Wooting Two (Legacy)", 0, XTYPE_XBOX360 },
|
||||
{ 0x044f, 0x0f00, "Thrustmaster Wheel", 0, XTYPE_XBOX },
|
||||
{ 0x044f, 0x0f03, "Thrustmaster Wheel", 0, XTYPE_XBOX },
|
||||
{ 0x044f, 0x0f07, "Thrustmaster, Inc. Controller", 0, XTYPE_XBOX },
|
||||
@@ -242,6 +244,7 @@ static const struct xpad_device {
|
||||
{ 0x0f0d, 0x0063, "Hori Real Arcade Pro Hayabusa (USA) Xbox One", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOXONE },
|
||||
{ 0x0f0d, 0x0067, "HORIPAD ONE", 0, XTYPE_XBOXONE },
|
||||
{ 0x0f0d, 0x0078, "Hori Real Arcade Pro V Kai Xbox One", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOXONE },
|
||||
{ 0x0f0d, 0x00c5, "Hori Fighting Commander ONE", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOXONE },
|
||||
{ 0x0f30, 0x010b, "Philips Recoil", 0, XTYPE_XBOX },
|
||||
{ 0x0f30, 0x0202, "Joytech Advanced Controller", 0, XTYPE_XBOX },
|
||||
{ 0x0f30, 0x8888, "BigBen XBMiniPad Controller", 0, XTYPE_XBOX },
|
||||
@@ -258,6 +261,7 @@ static const struct xpad_device {
|
||||
{ 0x1430, 0x8888, "TX6500+ Dance Pad (first generation)", MAP_DPAD_TO_BUTTONS, XTYPE_XBOX },
|
||||
{ 0x1430, 0xf801, "RedOctane Controller", 0, XTYPE_XBOX360 },
|
||||
{ 0x146b, 0x0601, "BigBen Interactive XBOX 360 Controller", 0, XTYPE_XBOX360 },
|
||||
{ 0x146b, 0x0604, "Bigben Interactive DAIJA Arcade Stick", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 },
|
||||
{ 0x1532, 0x0037, "Razer Sabertooth", 0, XTYPE_XBOX360 },
|
||||
{ 0x1532, 0x0a00, "Razer Atrox Arcade Stick", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOXONE },
|
||||
{ 0x1532, 0x0a03, "Razer Wildcat", 0, XTYPE_XBOXONE },
|
||||
@@ -322,6 +326,7 @@ static const struct xpad_device {
|
||||
{ 0x24c6, 0x5502, "Hori Fighting Stick VX Alt", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 },
|
||||
{ 0x24c6, 0x5503, "Hori Fighting Edge", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 },
|
||||
{ 0x24c6, 0x5506, "Hori SOULCALIBUR V Stick", 0, XTYPE_XBOX360 },
|
||||
{ 0x24c6, 0x5510, "Hori Fighting Commander ONE (Xbox 360/PC Mode)", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 },
|
||||
{ 0x24c6, 0x550d, "Hori GEM Xbox controller", 0, XTYPE_XBOX360 },
|
||||
{ 0x24c6, 0x550e, "Hori Real Arcade Pro V Kai 360", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 },
|
||||
{ 0x24c6, 0x551a, "PowerA FUSION Pro Controller", 0, XTYPE_XBOXONE },
|
||||
@@ -331,6 +336,14 @@ static const struct xpad_device {
|
||||
{ 0x24c6, 0x5b03, "Thrustmaster Ferrari 458 Racing Wheel", 0, XTYPE_XBOX360 },
|
||||
{ 0x24c6, 0x5d04, "Razer Sabertooth", 0, XTYPE_XBOX360 },
|
||||
{ 0x24c6, 0xfafe, "Rock Candy Gamepad for Xbox 360", 0, XTYPE_XBOX360 },
|
||||
{ 0x2563, 0x058d, "OneXPlayer Gamepad", 0, XTYPE_XBOX360 },
|
||||
{ 0x2dc8, 0x2000, "8BitDo Pro 2 Wired Controller fox Xbox", 0, XTYPE_XBOXONE },
|
||||
{ 0x31e3, 0x1100, "Wooting One", 0, XTYPE_XBOX360 },
|
||||
{ 0x31e3, 0x1200, "Wooting Two", 0, XTYPE_XBOX360 },
|
||||
{ 0x31e3, 0x1210, "Wooting Lekker", 0, XTYPE_XBOX360 },
|
||||
{ 0x31e3, 0x1220, "Wooting Two HE", 0, XTYPE_XBOX360 },
|
||||
{ 0x31e3, 0x1300, "Wooting 60HE (AVR)", 0, XTYPE_XBOX360 },
|
||||
{ 0x31e3, 0x1310, "Wooting 60HE (ARM)", 0, XTYPE_XBOX360 },
|
||||
{ 0x3285, 0x0607, "Nacon GC-100", 0, XTYPE_XBOX360 },
|
||||
{ 0x3767, 0x0101, "Fanatec Speedster 3 Forceshock Wheel", 0, XTYPE_XBOX },
|
||||
{ 0xffff, 0xffff, "Chinese-made Xbox Controller", 0, XTYPE_XBOX },
|
||||
@@ -416,6 +429,7 @@ static const signed short xpad_abs_triggers[] = {
|
||||
static const struct usb_device_id xpad_table[] = {
|
||||
{ USB_INTERFACE_INFO('X', 'B', 0) }, /* X-Box USB-IF not approved class */
|
||||
XPAD_XBOX360_VENDOR(0x0079), /* GPD Win 2 Controller */
|
||||
XPAD_XBOX360_VENDOR(0x03eb), /* Wooting Keyboards (Legacy) */
|
||||
XPAD_XBOX360_VENDOR(0x044f), /* Thrustmaster X-Box 360 controllers */
|
||||
XPAD_XBOX360_VENDOR(0x045e), /* Microsoft X-Box 360 controllers */
|
||||
XPAD_XBOXONE_VENDOR(0x045e), /* Microsoft X-Box One controllers */
|
||||
@@ -426,6 +440,7 @@ static const struct usb_device_id xpad_table[] = {
|
||||
{ USB_DEVICE(0x0738, 0x4540) }, /* Mad Catz Beat Pad */
|
||||
XPAD_XBOXONE_VENDOR(0x0738), /* Mad Catz FightStick TE 2 */
|
||||
XPAD_XBOX360_VENDOR(0x07ff), /* Mad Catz GamePad */
|
||||
XPAD_XBOX360_VENDOR(0x0c12), /* Zeroplus X-Box 360 controllers */
|
||||
XPAD_XBOX360_VENDOR(0x0e6f), /* 0x0e6f X-Box 360 controllers */
|
||||
XPAD_XBOXONE_VENDOR(0x0e6f), /* 0x0e6f X-Box One controllers */
|
||||
XPAD_XBOX360_VENDOR(0x0f0d), /* Hori Controllers */
|
||||
@@ -446,8 +461,12 @@ static const struct usb_device_id xpad_table[] = {
|
||||
XPAD_XBOXONE_VENDOR(0x20d6), /* PowerA Controllers */
|
||||
XPAD_XBOX360_VENDOR(0x24c6), /* PowerA Controllers */
|
||||
XPAD_XBOXONE_VENDOR(0x24c6), /* PowerA Controllers */
|
||||
XPAD_XBOX360_VENDOR(0x2563), /* OneXPlayer Gamepad */
|
||||
XPAD_XBOX360_VENDOR(0x260d), /* Dareu H101 */
|
||||
XPAD_XBOXONE_VENDOR(0x2dc8), /* 8BitDo Pro 2 Wired Controller for Xbox */
|
||||
XPAD_XBOXONE_VENDOR(0x2e24), /* Hyperkin Duke X-Box One pad */
|
||||
XPAD_XBOX360_VENDOR(0x2f24), /* GameSir Controllers */
|
||||
XPAD_XBOX360_VENDOR(0x31e3), /* Wooting Keyboards */
|
||||
XPAD_XBOX360_VENDOR(0x3285), /* Nacon GC-100 */
|
||||
{ }
|
||||
};
|
||||
@@ -1964,7 +1983,6 @@ static struct usb_driver xpad_driver = {
|
||||
.disconnect = xpad_disconnect,
|
||||
.suspend = xpad_suspend,
|
||||
.resume = xpad_resume,
|
||||
.reset_resume = xpad_resume,
|
||||
.id_table = xpad_table,
|
||||
};
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user