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qla3xxx: Add support for Qlogic 4032 chip.
Qlogic 4032 chip is an incremental change from the 4022. Signed-off-by: Ron Mercer <ron.mercer@qlogic.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Ron Mercer
Jeff Garzik
363
drivers/net/qla3xxx.c
Normal file → Executable file
363
drivers/net/qla3xxx.c
Normal file → Executable file
File diff suppressed because it is too large
Load Diff
88
drivers/net/qla3xxx.h
Normal file → Executable file
88
drivers/net/qla3xxx.h
Normal file → Executable file
@@ -21,7 +21,9 @@
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#define OPCODE_UPDATE_NCB_IOCB 0xF0
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#define OPCODE_IB_MAC_IOCB 0xF9
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#define OPCODE_IB_3032_MAC_IOCB 0x09
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#define OPCODE_IB_IP_IOCB 0xFA
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#define OPCODE_IB_3032_IP_IOCB 0x0A
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#define OPCODE_IB_TCP_IOCB 0xFB
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#define OPCODE_DUMP_PROTO_IOCB 0xFE
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#define OPCODE_BUFFER_ALERT_IOCB 0xFB
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@@ -37,18 +39,23 @@
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struct ob_mac_iocb_req {
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u8 opcode;
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u8 flags;
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#define OB_MAC_IOCB_REQ_MA 0xC0
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#define OB_MAC_IOCB_REQ_F 0x20
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#define OB_MAC_IOCB_REQ_X 0x10
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#define OB_MAC_IOCB_REQ_MA 0xe0
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#define OB_MAC_IOCB_REQ_F 0x10
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#define OB_MAC_IOCB_REQ_X 0x08
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#define OB_MAC_IOCB_REQ_D 0x02
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#define OB_MAC_IOCB_REQ_I 0x01
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__le16 reserved0;
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u8 flags1;
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#define OB_3032MAC_IOCB_REQ_IC 0x04
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#define OB_3032MAC_IOCB_REQ_TC 0x02
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#define OB_3032MAC_IOCB_REQ_UC 0x01
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u8 reserved0;
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__le32 transaction_id;
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__le16 data_len;
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__le16 reserved1;
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u8 ip_hdr_off;
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u8 ip_hdr_len;
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__le32 reserved1;
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__le32 reserved2;
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__le32 reserved3;
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__le32 buf_addr0_low;
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__le32 buf_addr0_high;
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__le32 buf_0_len;
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@@ -58,8 +65,8 @@ struct ob_mac_iocb_req {
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__le32 buf_addr2_low;
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__le32 buf_addr2_high;
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__le32 buf_2_len;
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__le32 reserved3;
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__le32 reserved4;
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__le32 reserved5;
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};
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/*
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* The following constants define control bits for buffer
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@@ -74,6 +81,7 @@ struct ob_mac_iocb_rsp {
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u8 opcode;
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u8 flags;
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#define OB_MAC_IOCB_RSP_P 0x08
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#define OB_MAC_IOCB_RSP_L 0x04
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#define OB_MAC_IOCB_RSP_S 0x02
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#define OB_MAC_IOCB_RSP_I 0x01
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@@ -85,6 +93,7 @@ struct ob_mac_iocb_rsp {
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struct ib_mac_iocb_rsp {
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u8 opcode;
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#define IB_MAC_IOCB_RSP_V 0x80
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u8 flags;
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#define IB_MAC_IOCB_RSP_S 0x80
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#define IB_MAC_IOCB_RSP_H1 0x40
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@@ -138,6 +147,7 @@ struct ob_ip_iocb_req {
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struct ob_ip_iocb_rsp {
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u8 opcode;
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u8 flags;
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#define OB_MAC_IOCB_RSP_H 0x10
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#define OB_MAC_IOCB_RSP_E 0x08
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#define OB_MAC_IOCB_RSP_L 0x04
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#define OB_MAC_IOCB_RSP_S 0x02
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@@ -220,6 +230,10 @@ struct ob_tcp_iocb_rsp {
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struct ib_ip_iocb_rsp {
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u8 opcode;
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#define IB_IP_IOCB_RSP_3032_V 0x80
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#define IB_IP_IOCB_RSP_3032_O 0x40
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#define IB_IP_IOCB_RSP_3032_I 0x20
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#define IB_IP_IOCB_RSP_3032_R 0x10
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u8 flags;
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#define IB_IP_IOCB_RSP_S 0x80
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#define IB_IP_IOCB_RSP_H1 0x40
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@@ -230,6 +244,12 @@ struct ib_ip_iocb_rsp {
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__le16 length;
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__le16 checksum;
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#define IB_IP_IOCB_RSP_3032_ICE 0x01
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#define IB_IP_IOCB_RSP_3032_CE 0x02
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#define IB_IP_IOCB_RSP_3032_NUC 0x04
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#define IB_IP_IOCB_RSP_3032_UDP 0x08
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#define IB_IP_IOCB_RSP_3032_TCP 0x10
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#define IB_IP_IOCB_RSP_3032_IPE 0x20
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__le16 reserved;
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#define IB_IP_IOCB_RSP_R 0x01
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__le32 ial_low;
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@@ -524,6 +544,21 @@ enum {
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IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
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IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
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IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
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IP_ADDR_INDEX_REG_6 = 0x0008,
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IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
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IP_ADDR_INDEX_REG_E = 0x0040,
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};
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enum {
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QL3032_PORT_CONTROL_DS = 0x0001,
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QL3032_PORT_CONTROL_HH = 0x0002,
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QL3032_PORT_CONTROL_EIv6 = 0x0004,
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QL3032_PORT_CONTROL_EIv4 = 0x0008,
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QL3032_PORT_CONTROL_ET = 0x0010,
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QL3032_PORT_CONTROL_EF = 0x0020,
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QL3032_PORT_CONTROL_DRM = 0x0040,
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QL3032_PORT_CONTROL_RLB = 0x0080,
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QL3032_PORT_CONTROL_RCB = 0x0100,
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QL3032_PORT_CONTROL_KIE = 0x0200,
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};
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enum {
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@@ -657,7 +692,8 @@ struct ql3xxx_port_registers {
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u32 internalRamWDataReg;
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u32 reclaimedBufferAddrRegLow;
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u32 reclaimedBufferAddrRegHigh;
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u32 reserved[2];
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u32 tcpConfiguration;
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u32 functionControl;
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u32 fpgaRevID;
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u32 localRamAddr;
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u32 localRamDataAutoIncr;
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@@ -963,6 +999,7 @@ struct eeprom_data {
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#define QL3XXX_VENDOR_ID 0x1077
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#define QL3022_DEVICE_ID 0x3022
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#define QL3032_DEVICE_ID 0x3032
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/* MTU & Frame Size stuff */
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#define NORMAL_MTU_SIZE ETH_DATA_LEN
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@@ -1038,11 +1075,41 @@ struct ql_rcv_buf_cb {
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int index;
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};
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/*
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* Original IOCB has 3 sg entries:
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* first points to skb-data area
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* second points to first frag
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* third points to next oal.
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* OAL has 5 entries:
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* 1 thru 4 point to frags
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* fifth points to next oal.
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*/
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#define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1)
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struct oal_entry {
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u32 dma_lo;
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u32 dma_hi;
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u32 len;
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#define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */
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#define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */
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u32 reserved;
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};
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struct oal {
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struct oal_entry oal_entry[5];
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};
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struct map_list {
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DECLARE_PCI_UNMAP_ADDR(mapaddr);
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DECLARE_PCI_UNMAP_LEN(maplen);
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};
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struct ql_tx_buf_cb {
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struct sk_buff *skb;
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struct ob_mac_iocb_req *queue_entry ;
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DECLARE_PCI_UNMAP_ADDR(mapaddr);
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DECLARE_PCI_UNMAP_LEN(maplen);
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int seg_count;
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struct oal *oal;
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struct map_list map[MAX_SKB_FRAGS+1];
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};
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/* definitions for type field */
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@@ -1189,6 +1256,7 @@ struct ql3_adapter {
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struct delayed_work reset_work;
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struct delayed_work tx_timeout_work;
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u32 max_frame_size;
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u32 device_id;
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};
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#endif /* _QLA3XXX_H_ */
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