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Staging: ipack: add support for IP-OCTAL mezzanine board

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IP-OCTAL is a 8-channels serial port device. There are several models one per
each standard: RS-232, RS-422, RS-485.

This driver can manage all of them.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Samuel Iglesias Gonsalvez
2012-05-09 15:27:21 +02:00
committed by Greg Kroah-Hartman
parent 0eeca14f5a
commit ba4dc61fe8
8 changed files with 1223 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/staging/ipack/Kconfig
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@@ -9,6 +9,8 @@ menuconfig IPACK_BUS
if IPACK_BUS
source "drivers/staging/ipack/devices/Kconfig"
source "drivers/staging/ipack/bridges/Kconfig"
endif # IPACK

1
drivers/staging/ipack/Makefile
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@@ -2,4 +2,5 @@
# Makefile for the IPACK bridge device drivers.
#
obj-$(CONFIG_IPACK_BUS) += ipack.o
obj-y += devices/
obj-y += bridges/

9
drivers/staging/ipack/TODO
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@@ -22,6 +22,15 @@ TPCI-200
* It has a linked list with the tpci200 devices it is managing. Get rid of it
and use driver_for_each_device() instead.
IP-OCTAL
--------
* It has a linked list which saves the devices it is currently
managing. It should use the driver_for_each_device() function. It is not there
due to the impossibility of using container_of macro to recover the
corresponding "struct ipoctal" because the attribute "struct ipack_device" is
a pointer. This code should be refactored.
Ipack
-----

7
drivers/staging/ipack/devices/Kconfig Normal file
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@@ -0,0 +1,7 @@
config SERIAL_IPOCTAL
tristate "IndustryPack IP-OCTAL uart support"
depends on IPACK_BUS
help
This driver supports the IPOCTAL serial port device for the IndustryPack bus.
default n

1
drivers/staging/ipack/devices/Makefile Normal file
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@@ -0,0 +1 @@
obj-$(CONFIG_SERIAL_IPOCTAL) += ipoctal.o

893
drivers/staging/ipack/devices/ipoctal.c Normal file
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File diff suppressed because it is too large Load Diff

81
drivers/staging/ipack/devices/ipoctal.h Normal file
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@@ -0,0 +1,81 @@
/**
* ipoctal.h
*
* driver for the IPOCTAL boards
* Copyright (c) 2009 Nicolas Serafini, EIC2 SA
* Copyright (c) 2010,2011 Samuel Iglesias Gonsalvez <siglesia@cern.ch>, CERN
* Copyright (c) 2012 Samuel Iglesias Gonsalvez <siglesias@igalia.com>, Igalia
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#ifndef _IPOCTAL_H
#define _IPOCTAL_H_
#define NR_CHANNELS 8
#define IPOCTAL_MAX_BOARDS 16
#define MAX_DEVICES (NR_CHANNELS * IPOCTAL_MAX_BOARDS)
#define RELEVANT_IFLAG(iflag) ((iflag) & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
/**
* enum uart_parity_e - UART supported parity.
*/
enum uart_parity_e {
UART_NONE = 0,
UART_ODD = 1,
UART_EVEN = 2,
};
/**
* enum uart_error - UART error type
*
*/
enum uart_error {
UART_NOERROR = 0, /* No error during transmission */
UART_TIMEOUT = 1 << 0, /* Timeout error */
UART_OVERRUN = 1 << 1, /* Overrun error */
UART_PARITY = 1 << 2, /* Parity error */
UART_FRAMING = 1 << 3, /* Framing error */
UART_BREAK = 1 << 4, /* Received break */
};
/**
* struct ipoctal_config - Serial configuration
*
* @baud: Baud rate
* @stop_bits: Stop bits (1 or 2)
* @bits_per_char: data size in bits
* @parity
* @flow_control: Flow control management (RTS/CTS) (0 disabled, 1 enabled)
*/
struct ipoctal_config {
unsigned int baud;
unsigned int stop_bits;
unsigned int bits_per_char;
unsigned short parity;
unsigned int flow_control;
};
/**
* struct ipoctal_stats -- Stats since last reset
*
* @tx: Number of transmitted bytes
* @rx: Number of received bytes
* @overrun: Number of overrun errors
* @parity_err: Number of parity errors
* @framing_err: Number of framing errors
* @rcv_break: Number of break received
*/
struct ipoctal_stats {
unsigned long tx;
unsigned long rx;
unsigned long overrun_err;
unsigned long parity_err;
unsigned long framing_err;
unsigned long rcv_break;
};
#endif /* _IPOCTAL_H_ */

229
drivers/staging/ipack/devices/scc2698.h Normal file
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@@ -0,0 +1,229 @@
/*
* scc2698.h
*
* driver for the IPOCTAL boards
* Copyright (c) 2009 Nicolas Serafini, EIC2 SA
* Copyright (c) 2010,2011 Samuel Iglesias Gonsalvez <siglesia@cern.ch>, CERN
* Copyright (c) 2012 Samuel Iglesias Gonsalvez <siglesias@igalia.com>, Igalia
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#ifndef SCC2698_H_
#define SCC2698_H_
/*
* struct scc2698_channel - Channel access to scc2698 IO
*
* dn value are only spacer.
*
*/
struct scc2698_channel {
union {
struct {
unsigned char d0, mr; /* Mode register 1/2*/
unsigned char d1, sr; /* Status register */
unsigned char d2, r1; /* reserved */
unsigned char d3, rhr; /* Receive holding register (R) */
unsigned char junk[8]; /* other crap for block control */
} r; /* Read access */
struct {
unsigned char d0, mr; /* Mode register 1/2 */
unsigned char d1, csr; /* Clock select register */
unsigned char d2, cr; /* Command register */
unsigned char d3, thr; /* Transmit holding register */
unsigned char junk[8]; /* other crap for block control */
} w; /* Write access */
} u;
};
/*
* struct scc2698_block - Block access to scc2698 IO
*
* The scc2698 contain 4 block.
* Each block containt two channel a and b.
* dn value are only spacer.
*
*/
struct scc2698_block {
union {
struct {
unsigned char d0, mra; /* Mode register 1/2 (a) */
unsigned char d1, sra; /* Status register (a) */
unsigned char d2, r1; /* reserved */
unsigned char d3, rhra; /* Receive holding register (a) */
unsigned char d4, ipcr; /* Input port change register of block */
unsigned char d5, isr; /* Interrupt status register of block */
unsigned char d6, ctur; /* Counter timer upper register of block */
unsigned char d7, ctlr; /* Counter timer lower register of block */
unsigned char d8, mrb; /* Mode register 1/2 (b) */
unsigned char d9, srb; /* Status register (b) */
unsigned char da, r2; /* reserved */
unsigned char db, rhrb; /* Receive holding register (b) */
unsigned char dc, r3; /* reserved */
unsigned char dd, ip; /* Input port register of block */
unsigned char de, ctg; /* Start counter timer of block */
unsigned char df, cts; /* Stop counter timer of block */
} r; /* Read access */
struct {
unsigned char d0, mra; /* Mode register 1/2 (a) */
unsigned char d1, csra; /* Clock select register (a) */
unsigned char d2, cra; /* Command register (a) */
unsigned char d3, thra; /* Transmit holding register (a) */
unsigned char d4, acr; /* Auxiliary control register of block */
unsigned char d5, imr; /* Interrupt mask register of block */
unsigned char d6, ctu; /* Counter timer upper register of block */
unsigned char d7, ctl; /* Counter timer lower register of block */
unsigned char d8, mrb; /* Mode register 1/2 (b) */
unsigned char d9, csrb; /* Clock select register (a) */
unsigned char da, crb; /* Command register (b) */
unsigned char db, thrb; /* Transmit holding register (b) */
unsigned char dc, r1; /* reserved */
unsigned char dd, opcr; /* Output port configuration register of block */
unsigned char de, r2; /* reserved */
unsigned char df, r3; /* reserved */
} w; /* Write access */
} u;
} ;
#define MR1_CHRL_5_BITS (0x0 << 0)
#define MR1_CHRL_6_BITS (0x1 << 0)
#define MR1_CHRL_7_BITS (0x2 << 0)
#define MR1_CHRL_8_BITS (0x3 << 0)
#define MR1_PARITY_EVEN (0x1 << 2)
#define MR1_PARITY_ODD (0x0 << 2)
#define MR1_PARITY_ON (0x0 << 3)
#define MR1_PARITY_FORCE (0x1 << 3)
#define MR1_PARITY_OFF (0x2 << 3)
#define MR1_PARITY_SPECIAL (0x3 << 3)
#define MR1_ERROR_CHAR (0x0 << 5)
#define MR1_ERROR_BLOCK (0x1 << 5)
#define MR1_RxINT_RxRDY (0x0 << 6)
#define MR1_RxINT_FFULL (0x1 << 6)
#define MR1_RxRTS_CONTROL_ON (0x1 << 7)
#define MR1_RxRTS_CONTROL_OFF (0x0 << 7)
#define MR2_STOP_BITS_LENGTH_1 (0x7 << 0)
#define MR2_STOP_BITS_LENGTH_2 (0xF << 0)
#define MR2_CTS_ENABLE_TX_ON (0x1 << 4)
#define MR2_CTS_ENABLE_TX_OFF (0x0 << 4)
#define MR2_TxRTS_CONTROL_ON (0x1 << 5)
#define MR2_TxRTS_CONTROL_OFF (0x0 << 5)
#define MR2_CH_MODE_NORMAL (0x0 << 6)
#define MR2_CH_MODE_ECHO (0x1 << 6)
#define MR2_CH_MODE_LOCAL (0x2 << 6)
#define MR2_CH_MODE_REMOTE (0x3 << 6)
#define CR_ENABLE_RX (0x1 << 0)
#define CR_DISABLE_RX (0x1 << 1)
#define CR_ENABLE_TX (0x1 << 2)
#define CR_DISABLE_TX (0x1 << 3)
#define CR_CMD_RESET_MR (0x1 << 4)
#define CR_CMD_RESET_RX (0x2 << 4)
#define CR_CMD_RESET_TX (0x3 << 4)
#define CR_CMD_RESET_ERR_STATUS (0x4 << 4)
#define CR_CMD_RESET_BREAK_CHANGE (0x5 << 4)
#define CR_CMD_START_BREAK (0x6 << 4)
#define CR_CMD_STOP_BREAK (0x7 << 4)
#define CR_CMD_ASSERT_RTSN (0x8 << 4)
#define CR_CMD_NEGATE_RTSN (0x9 << 4)
#define CR_CMD_SET_TIMEOUT_MODE (0xA << 4)
#define CR_CMD_DISABLE_TIMEOUT_MODE (0xC << 4)
#define SR_RX_READY (0x1 << 0)
#define SR_FIFO_FULL (0x1 << 1)
#define SR_TX_READY (0x1 << 2)
#define SR_TX_EMPTY (0x1 << 3)
#define SR_OVERRUN_ERROR (0x1 << 4)
#define SR_PARITY_ERROR (0x1 << 5)
#define SR_FRAMING_ERROR (0x1 << 6)
#define SR_RECEIVED_BREAK (0x1 << 7)
#define SR_ERROR (0xF0)
#define ACR_DELTA_IP0_IRQ_EN (0x1 << 0)
#define ACR_DELTA_IP1_IRQ_EN (0x1 << 1)
#define ACR_DELTA_IP2_IRQ_EN (0x1 << 2)
#define ACR_DELTA_IP3_IRQ_EN (0x1 << 3)
#define ACR_CT_Mask (0x7 << 4)
#define ACR_CExt (0x0 << 4)
#define ACR_CTxCA (0x1 << 4)
#define ACR_CTxCB (0x2 << 4)
#define ACR_CClk16 (0x3 << 4)
#define ACR_TExt (0x4 << 4)
#define ACR_TExt16 (0x5 << 4)
#define ACR_TClk (0x6 << 4)
#define ACR_TClk16 (0x7 << 4)
#define ACR_BRG_SET1 (0x0 << 7)
#define ACR_BRG_SET2 (0x1 << 7)
#define TX_CLK_75 (0x0 << 0)
#define TX_CLK_110 (0x1 << 0)
#define TX_CLK_38400 (0x2 << 0)
#define TX_CLK_150 (0x3 << 0)
#define TX_CLK_300 (0x4 << 0)
#define TX_CLK_600 (0x5 << 0)
#define TX_CLK_1200 (0x6 << 0)
#define TX_CLK_2000 (0x7 << 0)
#define TX_CLK_2400 (0x8 << 0)
#define TX_CLK_4800 (0x9 << 0)
#define TX_CLK_1800 (0xA << 0)
#define TX_CLK_9600 (0xB << 0)
#define TX_CLK_19200 (0xC << 0)
#define RX_CLK_75 (0x0 << 4)
#define RX_CLK_110 (0x1 << 4)
#define RX_CLK_38400 (0x2 << 4)
#define RX_CLK_150 (0x3 << 4)
#define RX_CLK_300 (0x4 << 4)
#define RX_CLK_600 (0x5 << 4)
#define RX_CLK_1200 (0x6 << 4)
#define RX_CLK_2000 (0x7 << 4)
#define RX_CLK_2400 (0x8 << 4)
#define RX_CLK_4800 (0x9 << 4)
#define RX_CLK_1800 (0xA << 4)
#define RX_CLK_9600 (0xB << 4)
#define RX_CLK_19200 (0xC << 4)
#define OPCR_MPOa_RTSN (0x0 << 0)
#define OPCR_MPOa_C_TO (0x1 << 0)
#define OPCR_MPOa_TxC1X (0x2 << 0)
#define OPCR_MPOa_TxC16X (0x3 << 0)
#define OPCR_MPOa_RxC1X (0x4 << 0)
#define OPCR_MPOa_RxC16X (0x5 << 0)
#define OPCR_MPOa_TxRDY (0x6 << 0)
#define OPCR_MPOa_RxRDY_FF (0x7 << 0)
#define OPCR_MPOb_RTSN (0x0 << 4)
#define OPCR_MPOb_C_TO (0x1 << 4)
#define OPCR_MPOb_TxC1X (0x2 << 4)
#define OPCR_MPOb_TxC16X (0x3 << 4)
#define OPCR_MPOb_RxC1X (0x4 << 4)
#define OPCR_MPOb_RxC16X (0x5 << 4)
#define OPCR_MPOb_TxRDY (0x6 << 4)
#define OPCR_MPOb_RxRDY_FF (0x7 << 4)
#define OPCR_MPP_INPUT (0x0 << 7)
#define OPCR_MPP_OUTPUT (0x1 << 7)
#define IMR_TxRDY_A (0x1 << 0)
#define IMR_RxRDY_FFULL_A (0x1 << 1)
#define IMR_DELTA_BREAK_A (0x1 << 2)
#define IMR_COUNTER_READY (0x1 << 3)
#define IMR_TxRDY_B (0x1 << 4)
#define IMR_RxRDY_FFULL_B (0x1 << 5)
#define IMR_DELTA_BREAK_B (0x1 << 6)
#define IMR_INPUT_PORT_CHANGE (0x1 << 7)
#define ISR_TxRDY_A (0x1 << 0)
#define ISR_RxRDY_FFULL_A (0x1 << 1)
#define ISR_DELTA_BREAK_A (0x1 << 2)
#define ISR_COUNTER_READY (0x1 << 3)
#define ISR_TxRDY_B (0x1 << 4)
#define ISR_RxRDY_FFULL_B (0x1 << 5)
#define ISR_DELTA_BREAK_B (0x1 << 6)
#define ISR_INPUT_PORT_CHANGE (0x1 << 7)
#endif /* SCC2698_H_ */