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net: mscc: ocelot: Add support for tcam
Add ACL support using the TCAM. Using ACL it is possible to create rules in hardware to filter/redirect frames. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Horatiu Vultur
committed by
David S. Miller
David S. Miller
parent
6345266a99
commit
b596229448
@@ -132,11 +132,12 @@
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<0x1270000 0x100>,
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<0x1280000 0x100>,
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<0x1800000 0x80000>,
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<0x1880000 0x10000>;
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<0x1880000 0x10000>,
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<0x1060000 0x10000>;
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reg-names = "sys", "rew", "qs", "port0", "port1",
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"port2", "port3", "port4", "port5", "port6",
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"port7", "port8", "port9", "port10", "qsys",
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"ana";
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"ana", "s2";
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interrupts = <21 22>;
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interrupt-names = "xtr", "inj";
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@@ -1,5 +1,5 @@
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# SPDX-License-Identifier: (GPL-2.0 OR MIT)
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obj-$(CONFIG_MSCC_OCELOT_SWITCH) += mscc_ocelot_common.o
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mscc_ocelot_common-y := ocelot.o ocelot_io.o
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mscc_ocelot_common-y += ocelot_regs.o ocelot_tc.o ocelot_police.o
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mscc_ocelot_common-y += ocelot_regs.o ocelot_tc.o ocelot_police.o ocelot_ace.o
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obj-$(CONFIG_MSCC_OCELOT_SWITCH_OCELOT) += ocelot_board.o
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@@ -22,6 +22,7 @@
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#include <net/switchdev.h>
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#include "ocelot.h"
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#include "ocelot_ace.h"
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#define TABLE_UPDATE_SLEEP_US 10
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#define TABLE_UPDATE_TIMEOUT_US 100000
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@@ -130,6 +131,13 @@ static void ocelot_mact_init(struct ocelot *ocelot)
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ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
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}
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static void ocelot_vcap_enable(struct ocelot *ocelot, struct ocelot_port *port)
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{
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ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
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ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
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ANA_PORT_VCAP_S2_CFG, port->chip_port);
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}
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static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
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{
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return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
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@@ -1662,6 +1670,9 @@ int ocelot_probe_port(struct ocelot *ocelot, u8 port,
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/* Basic L2 initialization */
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ocelot_vlan_port_apply(ocelot, ocelot_port);
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/* Enable vcap lookups */
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ocelot_vcap_enable(ocelot, ocelot_port);
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return 0;
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err_register_netdev:
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@@ -1696,6 +1707,7 @@ int ocelot_init(struct ocelot *ocelot)
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ocelot_mact_init(ocelot);
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ocelot_vlan_init(ocelot);
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ocelot_ace_init(ocelot);
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for (port = 0; port < ocelot->num_phys_ports; port++) {
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/* Clear all counters (5 groups) */
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@@ -1808,6 +1820,7 @@ void ocelot_deinit(struct ocelot *ocelot)
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{
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destroy_workqueue(ocelot->stats_queue);
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mutex_destroy(&ocelot->stats_lock);
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ocelot_ace_deinit();
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}
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EXPORT_SYMBOL(ocelot_deinit);
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@@ -69,6 +69,7 @@ enum ocelot_target {
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QSYS,
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REW,
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SYS,
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S2,
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HSIO,
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TARGET_MAX,
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};
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@@ -335,6 +336,13 @@ enum ocelot_reg {
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SYS_CM_DATA_RD,
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SYS_CM_OP,
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SYS_CM_DATA,
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S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
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S2_CORE_MV_CFG,
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S2_CACHE_ENTRY_DAT,
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S2_CACHE_MASK_DAT,
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S2_CACHE_ACTION_DAT,
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S2_CACHE_CNT_DAT,
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S2_CACHE_TG_DAT,
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};
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enum ocelot_regfield {
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777
drivers/net/ethernet/mscc/ocelot_ace.c
Normal file
777
drivers/net/ethernet/mscc/ocelot_ace.c
Normal file
File diff suppressed because it is too large
Load Diff
227
drivers/net/ethernet/mscc/ocelot_ace.h
Normal file
227
drivers/net/ethernet/mscc/ocelot_ace.h
Normal file
@@ -0,0 +1,227 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/* Microsemi Ocelot Switch driver
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* Copyright (c) 2019 Microsemi Corporation
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*/
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#ifndef _MSCC_OCELOT_ACE_H_
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#define _MSCC_OCELOT_ACE_H_
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#include "ocelot.h"
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#include <net/sch_generic.h>
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#include <net/pkt_cls.h>
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struct ocelot_ipv4 {
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u8 addr[4];
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};
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enum ocelot_vcap_bit {
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OCELOT_VCAP_BIT_ANY,
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OCELOT_VCAP_BIT_0,
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OCELOT_VCAP_BIT_1
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};
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struct ocelot_vcap_u8 {
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u8 value[1];
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u8 mask[1];
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};
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struct ocelot_vcap_u16 {
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u8 value[2];
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u8 mask[2];
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};
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struct ocelot_vcap_u24 {
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u8 value[3];
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u8 mask[3];
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};
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struct ocelot_vcap_u32 {
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u8 value[4];
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u8 mask[4];
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};
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struct ocelot_vcap_u40 {
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u8 value[5];
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u8 mask[5];
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};
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struct ocelot_vcap_u48 {
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u8 value[6];
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u8 mask[6];
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};
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struct ocelot_vcap_u64 {
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u8 value[8];
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u8 mask[8];
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};
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struct ocelot_vcap_u128 {
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u8 value[16];
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u8 mask[16];
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};
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struct ocelot_vcap_vid {
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u16 value;
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u16 mask;
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};
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struct ocelot_vcap_ipv4 {
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struct ocelot_ipv4 value;
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struct ocelot_ipv4 mask;
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};
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struct ocelot_vcap_udp_tcp {
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u16 value;
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u16 mask;
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};
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enum ocelot_ace_type {
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OCELOT_ACE_TYPE_ANY,
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OCELOT_ACE_TYPE_ETYPE,
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OCELOT_ACE_TYPE_LLC,
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OCELOT_ACE_TYPE_SNAP,
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OCELOT_ACE_TYPE_ARP,
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OCELOT_ACE_TYPE_IPV4,
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OCELOT_ACE_TYPE_IPV6
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};
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struct ocelot_ace_vlan {
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struct ocelot_vcap_vid vid; /* VLAN ID (12 bit) */
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struct ocelot_vcap_u8 pcp; /* PCP (3 bit) */
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enum ocelot_vcap_bit dei; /* DEI */
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enum ocelot_vcap_bit tagged; /* Tagged/untagged frame */
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};
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struct ocelot_ace_frame_etype {
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struct ocelot_vcap_u48 dmac;
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struct ocelot_vcap_u48 smac;
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struct ocelot_vcap_u16 etype;
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struct ocelot_vcap_u16 data; /* MAC data */
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};
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struct ocelot_ace_frame_llc {
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struct ocelot_vcap_u48 dmac;
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struct ocelot_vcap_u48 smac;
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/* LLC header: DSAP at byte 0, SSAP at byte 1, Control at byte 2 */
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struct ocelot_vcap_u32 llc;
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};
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struct ocelot_ace_frame_snap {
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struct ocelot_vcap_u48 dmac;
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struct ocelot_vcap_u48 smac;
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/* SNAP header: Organization Code at byte 0, Type at byte 3 */
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struct ocelot_vcap_u40 snap;
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};
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struct ocelot_ace_frame_arp {
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struct ocelot_vcap_u48 smac;
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enum ocelot_vcap_bit arp; /* Opcode ARP/RARP */
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enum ocelot_vcap_bit req; /* Opcode request/reply */
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enum ocelot_vcap_bit unknown; /* Opcode unknown */
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enum ocelot_vcap_bit smac_match; /* Sender MAC matches SMAC */
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enum ocelot_vcap_bit dmac_match; /* Target MAC matches DMAC */
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/**< Protocol addr. length 4, hardware length 6 */
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enum ocelot_vcap_bit length;
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enum ocelot_vcap_bit ip; /* Protocol address type IP */
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enum ocelot_vcap_bit ethernet; /* Hardware address type Ethernet */
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struct ocelot_vcap_ipv4 sip; /* Sender IP address */
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struct ocelot_vcap_ipv4 dip; /* Target IP address */
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};
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struct ocelot_ace_frame_ipv4 {
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enum ocelot_vcap_bit ttl; /* TTL zero */
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enum ocelot_vcap_bit fragment; /* Fragment */
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enum ocelot_vcap_bit options; /* Header options */
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struct ocelot_vcap_u8 ds;
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struct ocelot_vcap_u8 proto; /* Protocol */
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struct ocelot_vcap_ipv4 sip; /* Source IP address */
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struct ocelot_vcap_ipv4 dip; /* Destination IP address */
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struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */
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struct ocelot_vcap_udp_tcp sport; /* UDP/TCP: Source port */
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struct ocelot_vcap_udp_tcp dport; /* UDP/TCP: Destination port */
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enum ocelot_vcap_bit tcp_fin;
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enum ocelot_vcap_bit tcp_syn;
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enum ocelot_vcap_bit tcp_rst;
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enum ocelot_vcap_bit tcp_psh;
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enum ocelot_vcap_bit tcp_ack;
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enum ocelot_vcap_bit tcp_urg;
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enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */
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enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */
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enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */
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};
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struct ocelot_ace_frame_ipv6 {
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struct ocelot_vcap_u8 proto; /* IPv6 protocol */
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struct ocelot_vcap_u128 sip; /* IPv6 source (byte 0-7 ignored) */
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enum ocelot_vcap_bit ttl; /* TTL zero */
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struct ocelot_vcap_u8 ds;
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struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */
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struct ocelot_vcap_udp_tcp sport;
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struct ocelot_vcap_udp_tcp dport;
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enum ocelot_vcap_bit tcp_fin;
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enum ocelot_vcap_bit tcp_syn;
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enum ocelot_vcap_bit tcp_rst;
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enum ocelot_vcap_bit tcp_psh;
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enum ocelot_vcap_bit tcp_ack;
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enum ocelot_vcap_bit tcp_urg;
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enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */
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enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */
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enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */
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};
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enum ocelot_ace_action {
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OCELOT_ACL_ACTION_DROP,
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OCELOT_ACL_ACTION_TRAP,
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};
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struct ocelot_ace_stats {
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u64 bytes;
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u64 pkts;
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u64 used;
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};
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struct ocelot_ace_rule {
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struct list_head list;
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struct ocelot_port *port;
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u16 prio;
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u32 id;
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enum ocelot_ace_action action;
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struct ocelot_ace_stats stats;
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int chip_port;
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enum ocelot_vcap_bit dmac_mc;
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enum ocelot_vcap_bit dmac_bc;
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struct ocelot_ace_vlan vlan;
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enum ocelot_ace_type type;
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union {
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/* ocelot_ACE_TYPE_ANY: No specific fields */
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struct ocelot_ace_frame_etype etype;
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struct ocelot_ace_frame_llc llc;
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struct ocelot_ace_frame_snap snap;
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struct ocelot_ace_frame_arp arp;
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struct ocelot_ace_frame_ipv4 ipv4;
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struct ocelot_ace_frame_ipv6 ipv6;
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} frame;
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};
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struct ocelot_acl_block {
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struct list_head rules;
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struct ocelot *ocelot;
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int count;
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};
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int ocelot_ace_rule_offload_add(struct ocelot_ace_rule *rule);
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int ocelot_ace_rule_offload_del(struct ocelot_ace_rule *rule);
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int ocelot_ace_rule_stats_update(struct ocelot_ace_rule *rule);
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int ocelot_ace_init(struct ocelot *ocelot);
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void ocelot_ace_deinit(void);
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#endif /* _MSCC_OCELOT_ACE_H_ */
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@@ -188,6 +188,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
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{ QSYS, "qsys" },
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{ ANA, "ana" },
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{ QS, "qs" },
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{ S2, "s2" },
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};
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if (!np && !pdev->dev.platform_data)
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@@ -224,12 +224,23 @@ static const u32 ocelot_sys_regmap[] = {
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REG(SYS_PTP_CFG, 0x0006c4),
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};
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static const u32 ocelot_s2_regmap[] = {
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REG(S2_CORE_UPDATE_CTRL, 0x000000),
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REG(S2_CORE_MV_CFG, 0x000004),
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REG(S2_CACHE_ENTRY_DAT, 0x000008),
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REG(S2_CACHE_MASK_DAT, 0x000108),
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REG(S2_CACHE_ACTION_DAT, 0x000208),
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REG(S2_CACHE_CNT_DAT, 0x000308),
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REG(S2_CACHE_TG_DAT, 0x000388),
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};
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static const u32 *ocelot_regmap[] = {
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[ANA] = ocelot_ana_regmap,
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[QS] = ocelot_qs_regmap,
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[QSYS] = ocelot_qsys_regmap,
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[REW] = ocelot_rew_regmap,
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[SYS] = ocelot_sys_regmap,
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[S2] = ocelot_s2_regmap,
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};
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static const struct reg_field ocelot_regfields[] = {
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64
drivers/net/ethernet/mscc/ocelot_s2.h
Normal file
64
drivers/net/ethernet/mscc/ocelot_s2.h
Normal file
@@ -0,0 +1,64 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/* Microsemi Ocelot Switch driver
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#ifndef _OCELOT_S2_CORE_H_
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#define _OCELOT_S2_CORE_H_
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#define S2_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22))
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#define S2_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22)
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#define S2_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22)
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#define S2_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
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#define S2_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
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#define S2_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
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#define S2_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3))
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#define S2_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3)
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#define S2_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3)
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#define S2_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2)
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#define S2_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1)
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#define S2_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0)
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#define S2_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16))
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#define S2_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16)
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#define S2_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16)
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#define S2_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0))
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#define S2_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0)
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#define S2_CACHE_ENTRY_DAT_RSZ 0x4
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#define S2_CACHE_MASK_DAT_RSZ 0x4
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#define S2_CACHE_ACTION_DAT_RSZ 0x4
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#define S2_CACHE_CNT_DAT_RSZ 0x4
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#define S2_STICKY_VCAP_ROW_DELETED_STICKY BIT(0)
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#define S2_BIST_CTRL_TCAM_BIST BIT(1)
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#define S2_BIST_CTRL_TCAM_INIT BIT(0)
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#define S2_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8)
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#define S2_BIST_CFG_TCAM_HCG_DIS BIT(7)
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#define S2_BIST_CFG_TCAM_CG_DIS BIT(6)
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#define S2_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0))
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#define S2_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0)
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#define S2_BIST_STAT_BIST_RT_ERR BIT(15)
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#define S2_BIST_STAT_BIST_PENC_ERR BIT(14)
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#define S2_BIST_STAT_BIST_COMP_ERR BIT(13)
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#define S2_BIST_STAT_BIST_ADDR_ERR BIT(12)
|
||||
#define S2_BIST_STAT_BIST_BL1E_ERR BIT(11)
|
||||
#define S2_BIST_STAT_BIST_BL1_ERR BIT(10)
|
||||
#define S2_BIST_STAT_BIST_BL0E_ERR BIT(9)
|
||||
#define S2_BIST_STAT_BIST_BL0_ERR BIT(8)
|
||||
#define S2_BIST_STAT_BIST_PH1_ERR BIT(7)
|
||||
#define S2_BIST_STAT_BIST_PH0_ERR BIT(6)
|
||||
#define S2_BIST_STAT_BIST_PV1_ERR BIT(5)
|
||||
#define S2_BIST_STAT_BIST_PV0_ERR BIT(4)
|
||||
#define S2_BIST_STAT_BIST_RUN BIT(3)
|
||||
#define S2_BIST_STAT_BIST_ERR BIT(2)
|
||||
#define S2_BIST_STAT_BIST_BUSY BIT(1)
|
||||
#define S2_BIST_STAT_TCAM_RDY BIT(0)
|
||||
|
||||
#endif /* _OCELOT_S2_CORE_H_ */
|
||||
403
drivers/net/ethernet/mscc/ocelot_vcap.h
Normal file
403
drivers/net/ethernet/mscc/ocelot_vcap.h
Normal file
@@ -0,0 +1,403 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
* Microsemi Ocelot Switch driver
|
||||
* Copyright (c) 2019 Microsemi Corporation
|
||||
*/
|
||||
|
||||
#ifndef _OCELOT_VCAP_H_
|
||||
#define _OCELOT_VCAP_H_
|
||||
|
||||
/* =================================================================
|
||||
* VCAP Common
|
||||
* =================================================================
|
||||
*/
|
||||
|
||||
/* VCAP Type-Group values */
|
||||
#define VCAP_TG_NONE 0 /* Entry is invalid */
|
||||
#define VCAP_TG_FULL 1 /* Full entry */
|
||||
#define VCAP_TG_HALF 2 /* Half entry */
|
||||
#define VCAP_TG_QUARTER 3 /* Quarter entry */
|
||||
|
||||
/* =================================================================
|
||||
* VCAP IS2
|
||||
* =================================================================
|
||||
*/
|
||||
|
||||
#define VCAP_IS2_CNT 64
|
||||
#define VCAP_IS2_ENTRY_WIDTH 376
|
||||
#define VCAP_IS2_ACTION_WIDTH 99
|
||||
#define VCAP_PORT_CNT 11
|
||||
|
||||
/* IS2 half key types */
|
||||
#define IS2_TYPE_ETYPE 0
|
||||
#define IS2_TYPE_LLC 1
|
||||
#define IS2_TYPE_SNAP 2
|
||||
#define IS2_TYPE_ARP 3
|
||||
#define IS2_TYPE_IP_UDP_TCP 4
|
||||
#define IS2_TYPE_IP_OTHER 5
|
||||
#define IS2_TYPE_IPV6 6
|
||||
#define IS2_TYPE_OAM 7
|
||||
#define IS2_TYPE_SMAC_SIP6 8
|
||||
#define IS2_TYPE_ANY 100 /* Pseudo type */
|
||||
|
||||
/* IS2 half key type mask for matching any IP */
|
||||
#define IS2_TYPE_MASK_IP_ANY 0xe
|
||||
|
||||
/* IS2 action types */
|
||||
#define IS2_ACTION_TYPE_NORMAL 0
|
||||
#define IS2_ACTION_TYPE_SMAC_SIP 1
|
||||
|
||||
/* IS2 MASK_MODE values */
|
||||
#define IS2_ACT_MASK_MODE_NONE 0
|
||||
#define IS2_ACT_MASK_MODE_FILTER 1
|
||||
#define IS2_ACT_MASK_MODE_POLICY 2
|
||||
#define IS2_ACT_MASK_MODE_REDIR 3
|
||||
|
||||
/* IS2 REW_OP values */
|
||||
#define IS2_ACT_REW_OP_NONE 0
|
||||
#define IS2_ACT_REW_OP_PTP_ONE 2
|
||||
#define IS2_ACT_REW_OP_PTP_TWO 3
|
||||
#define IS2_ACT_REW_OP_SPECIAL 8
|
||||
#define IS2_ACT_REW_OP_PTP_ORG 9
|
||||
#define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3))
|
||||
#define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3))
|
||||
#define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5))
|
||||
#define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7)
|
||||
|
||||
#define VCAP_PORT_WIDTH 4
|
||||
|
||||
/* IS2 quarter key - SMAC_SIP4 */
|
||||
#define IS2_QKO_IGR_PORT 0
|
||||
#define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH
|
||||
#define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT)
|
||||
#define IS2_QKL_L2_SMAC 48
|
||||
#define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC)
|
||||
#define IS2_QKL_L3_IP4_SIP 32
|
||||
|
||||
/* IS2 half key - common */
|
||||
#define IS2_HKO_TYPE 0
|
||||
#define IS2_HKL_TYPE 4
|
||||
#define IS2_HKO_FIRST (IS2_HKO_TYPE + IS2_HKL_TYPE)
|
||||
#define IS2_HKL_FIRST 1
|
||||
#define IS2_HKO_PAG (IS2_HKO_FIRST + IS2_HKL_FIRST)
|
||||
#define IS2_HKL_PAG 8
|
||||
#define IS2_HKO_IGR_PORT_MASK (IS2_HKO_PAG + IS2_HKL_PAG)
|
||||
#define IS2_HKL_IGR_PORT_MASK (VCAP_PORT_CNT + 1)
|
||||
#define IS2_HKO_SERVICE_FRM (IS2_HKO_IGR_PORT_MASK + IS2_HKL_IGR_PORT_MASK)
|
||||
#define IS2_HKL_SERVICE_FRM 1
|
||||
#define IS2_HKO_HOST_MATCH (IS2_HKO_SERVICE_FRM + IS2_HKL_SERVICE_FRM)
|
||||
#define IS2_HKL_HOST_MATCH 1
|
||||
#define IS2_HKO_L2_MC (IS2_HKO_HOST_MATCH + IS2_HKL_HOST_MATCH)
|
||||
#define IS2_HKL_L2_MC 1
|
||||
#define IS2_HKO_L2_BC (IS2_HKO_L2_MC + IS2_HKL_L2_MC)
|
||||
#define IS2_HKL_L2_BC 1
|
||||
#define IS2_HKO_VLAN_TAGGED (IS2_HKO_L2_BC + IS2_HKL_L2_BC)
|
||||
#define IS2_HKL_VLAN_TAGGED 1
|
||||
#define IS2_HKO_VID (IS2_HKO_VLAN_TAGGED + IS2_HKL_VLAN_TAGGED)
|
||||
#define IS2_HKL_VID 12
|
||||
#define IS2_HKO_DEI (IS2_HKO_VID + IS2_HKL_VID)
|
||||
#define IS2_HKL_DEI 1
|
||||
#define IS2_HKO_PCP (IS2_HKO_DEI + IS2_HKL_DEI)
|
||||
#define IS2_HKL_PCP 3
|
||||
|
||||
/* IS2 half key - MAC_ETYPE/MAC_LLC/MAC_SNAP/OAM common */
|
||||
#define IS2_HKO_L2_DMAC (IS2_HKO_PCP + IS2_HKL_PCP)
|
||||
#define IS2_HKL_L2_DMAC 48
|
||||
#define IS2_HKO_L2_SMAC (IS2_HKO_L2_DMAC + IS2_HKL_L2_DMAC)
|
||||
#define IS2_HKL_L2_SMAC 48
|
||||
|
||||
/* IS2 half key - MAC_ETYPE */
|
||||
#define IS2_HKO_MAC_ETYPE_ETYPE (IS2_HKO_L2_SMAC + IS2_HKL_L2_SMAC)
|
||||
#define IS2_HKL_MAC_ETYPE_ETYPE 16
|
||||
#define IS2_HKO_MAC_ETYPE_L2_PAYLOAD \
|
||||
(IS2_HKO_MAC_ETYPE_ETYPE + IS2_HKL_MAC_ETYPE_ETYPE)
|
||||
#define IS2_HKL_MAC_ETYPE_L2_PAYLOAD 27
|
||||
|
||||
/* IS2 half key - MAC_LLC */
|
||||
#define IS2_HKO_MAC_LLC_L2_LLC IS2_HKO_MAC_ETYPE_ETYPE
|
||||
#define IS2_HKL_MAC_LLC_L2_LLC 40
|
||||
|
||||
/* IS2 half key - MAC_SNAP */
|
||||
#define IS2_HKO_MAC_SNAP_L2_SNAP IS2_HKO_MAC_ETYPE_ETYPE
|
||||
#define IS2_HKL_MAC_SNAP_L2_SNAP 40
|
||||
|
||||
/* IS2 half key - ARP */
|
||||
#define IS2_HKO_MAC_ARP_L2_SMAC IS2_HKO_L2_DMAC
|
||||
#define IS2_HKL_MAC_ARP_L2_SMAC 48
|
||||
#define IS2_HKO_MAC_ARP_ARP_ADDR_SPACE_OK \
|
||||
(IS2_HKO_MAC_ARP_L2_SMAC + IS2_HKL_MAC_ARP_L2_SMAC)
|
||||
#define IS2_HKL_MAC_ARP_ARP_ADDR_SPACE_OK 1
|
||||
#define IS2_HKO_MAC_ARP_ARP_PROTO_SPACE_OK \
|
||||
(IS2_HKO_MAC_ARP_ARP_ADDR_SPACE_OK + IS2_HKL_MAC_ARP_ARP_ADDR_SPACE_OK)
|
||||
#define IS2_HKL_MAC_ARP_ARP_PROTO_SPACE_OK 1
|
||||
#define IS2_HKO_MAC_ARP_ARP_LEN_OK \
|
||||
(IS2_HKO_MAC_ARP_ARP_PROTO_SPACE_OK + \
|
||||
IS2_HKL_MAC_ARP_ARP_PROTO_SPACE_OK)
|
||||
#define IS2_HKL_MAC_ARP_ARP_LEN_OK 1
|
||||
#define IS2_HKO_MAC_ARP_ARP_TGT_MATCH \
|
||||
(IS2_HKO_MAC_ARP_ARP_LEN_OK + IS2_HKL_MAC_ARP_ARP_LEN_OK)
|
||||
#define IS2_HKL_MAC_ARP_ARP_TGT_MATCH 1
|
||||
#define IS2_HKO_MAC_ARP_ARP_SENDER_MATCH \
|
||||
(IS2_HKO_MAC_ARP_ARP_TGT_MATCH + IS2_HKL_MAC_ARP_ARP_TGT_MATCH)
|
||||
#define IS2_HKL_MAC_ARP_ARP_SENDER_MATCH 1
|
||||
#define IS2_HKO_MAC_ARP_ARP_OPCODE_UNKNOWN \
|
||||
(IS2_HKO_MAC_ARP_ARP_SENDER_MATCH + IS2_HKL_MAC_ARP_ARP_SENDER_MATCH)
|
||||
#define IS2_HKL_MAC_ARP_ARP_OPCODE_UNKNOWN 1
|
||||
#define IS2_HKO_MAC_ARP_ARP_OPCODE \
|
||||
(IS2_HKO_MAC_ARP_ARP_OPCODE_UNKNOWN + \
|
||||
IS2_HKL_MAC_ARP_ARP_OPCODE_UNKNOWN)
|
||||
#define IS2_HKL_MAC_ARP_ARP_OPCODE 2
|
||||
#define IS2_HKO_MAC_ARP_L3_IP4_DIP \
|
||||
(IS2_HKO_MAC_ARP_ARP_OPCODE + IS2_HKL_MAC_ARP_ARP_OPCODE)
|
||||
#define IS2_HKL_MAC_ARP_L3_IP4_DIP 32
|
||||
#define IS2_HKO_MAC_ARP_L3_IP4_SIP \
|
||||
(IS2_HKO_MAC_ARP_L3_IP4_DIP + IS2_HKL_MAC_ARP_L3_IP4_DIP)
|
||||
#define IS2_HKL_MAC_ARP_L3_IP4_SIP 32
|
||||
#define IS2_HKO_MAC_ARP_DIP_EQ_SIP \
|
||||
(IS2_HKO_MAC_ARP_L3_IP4_SIP + IS2_HKL_MAC_ARP_L3_IP4_SIP)
|
||||
#define IS2_HKL_MAC_ARP_DIP_EQ_SIP 1
|
||||
|
||||
/* IS2 half key - IP4_TCP_UDP/IP4_OTHER common */
|
||||
#define IS2_HKO_IP4 IS2_HKO_L2_DMAC
|
||||
#define IS2_HKL_IP4 1
|
||||
#define IS2_HKO_L3_FRAGMENT (IS2_HKO_IP4 + IS2_HKL_IP4)
|
||||
#define IS2_HKL_L3_FRAGMENT 1
|
||||
#define IS2_HKO_L3_FRAG_OFS_GT0 (IS2_HKO_L3_FRAGMENT + IS2_HKL_L3_FRAGMENT)
|
||||
#define IS2_HKL_L3_FRAG_OFS_GT0 1
|
||||
#define IS2_HKO_L3_OPTIONS (IS2_HKO_L3_FRAG_OFS_GT0 + IS2_HKL_L3_FRAG_OFS_GT0)
|
||||
#define IS2_HKL_L3_OPTIONS 1
|
||||
#define IS2_HKO_L3_TTL_GT0 (IS2_HKO_L3_OPTIONS + IS2_HKL_L3_OPTIONS)
|
||||
#define IS2_HKL_L3_TTL_GT0 1
|
||||
#define IS2_HKO_L3_TOS (IS2_HKO_L3_TTL_GT0 + IS2_HKL_L3_TTL_GT0)
|
||||
#define IS2_HKL_L3_TOS 8
|
||||
#define IS2_HKO_L3_IP4_DIP (IS2_HKO_L3_TOS + IS2_HKL_L3_TOS)
|
||||
#define IS2_HKL_L3_IP4_DIP 32
|
||||
#define IS2_HKO_L3_IP4_SIP (IS2_HKO_L3_IP4_DIP + IS2_HKL_L3_IP4_DIP)
|
||||
#define IS2_HKL_L3_IP4_SIP 32
|
||||
#define IS2_HKO_DIP_EQ_SIP (IS2_HKO_L3_IP4_SIP + IS2_HKL_L3_IP4_SIP)
|
||||
#define IS2_HKL_DIP_EQ_SIP 1
|
||||
|
||||
/* IS2 half key - IP4_TCP_UDP */
|
||||
#define IS2_HKO_IP4_TCP_UDP_TCP (IS2_HKO_DIP_EQ_SIP + IS2_HKL_DIP_EQ_SIP)
|
||||
#define IS2_HKL_IP4_TCP_UDP_TCP 1
|
||||
#define IS2_HKO_IP4_TCP_UDP_L4_DPORT \
|
||||
(IS2_HKO_IP4_TCP_UDP_TCP + IS2_HKL_IP4_TCP_UDP_TCP)
|
||||
#define IS2_HKL_IP4_TCP_UDP_L4_DPORT 16
|
||||
#define IS2_HKO_IP4_TCP_UDP_L4_SPORT \
|
||||
(IS2_HKO_IP4_TCP_UDP_L4_DPORT + IS2_HKL_IP4_TCP_UDP_L4_DPORT)
|
||||
#define IS2_HKL_IP4_TCP_UDP_L4_SPORT 16
|
||||
#define IS2_HKO_IP4_TCP_UDP_L4_RNG \
|
||||
(IS2_HKO_IP4_TCP_UDP_L4_SPORT + IS2_HKL_IP4_TCP_UDP_L4_SPORT)
|
||||
#define IS2_HKL_IP4_TCP_UDP_L4_RNG 8
|
||||
#define IS2_HKO_IP4_TCP_UDP_SPORT_EQ_DPORT \
|
||||
(IS2_HKO_IP4_TCP_UDP_L4_RNG + IS2_HKL_IP4_TCP_UDP_L4_RNG)
|
||||
#define IS2_HKL_IP4_TCP_UDP_SPORT_EQ_DPORT 1
|
||||
#define IS2_HKO_IP4_TCP_UDP_SEQUENCE_EQ0 \
|
||||
(IS2_HKO_IP4_TCP_UDP_SPORT_EQ_DPORT + \
|
||||
IS2_HKL_IP4_TCP_UDP_SPORT_EQ_DPORT)
|
||||
#define IS2_HKL_IP4_TCP_UDP_SEQUENCE_EQ0 1
|
||||
#define IS2_HKO_IP4_TCP_UDP_L4_FIN \
|
||||
(IS2_HKO_IP4_TCP_UDP_SEQUENCE_EQ0 + IS2_HKL_IP4_TCP_UDP_SEQUENCE_EQ0)
|
||||
#define IS2_HKL_IP4_TCP_UDP_L4_FIN 1
|
||||
#define IS2_HKO_IP4_TCP_UDP_L4_SYN \
|
||||
(IS2_HKO_IP4_TCP_UDP_L4_FIN + IS2_HKL_IP4_TCP_UDP_L4_FIN)
|
||||
#define IS2_HKL_IP4_TCP_UDP_L4_SYN 1
|
||||
#define IS2_HKO_IP4_TCP_UDP_L4_RST \
|
||||
(IS2_HKO_IP4_TCP_UDP_L4_SYN + IS2_HKL_IP4_TCP_UDP_L4_SYN)
|
||||
#define IS2_HKL_IP4_TCP_UDP_L4_RST 1
|
||||
#define IS2_HKO_IP4_TCP_UDP_L4_PSH \
|
||||
(IS2_HKO_IP4_TCP_UDP_L4_RST + IS2_HKL_IP4_TCP_UDP_L4_RST)
|
||||
#define IS2_HKL_IP4_TCP_UDP_L4_PSH 1
|
||||
#define IS2_HKO_IP4_TCP_UDP_L4_ACK \
|
||||
(IS2_HKO_IP4_TCP_UDP_L4_PSH + IS2_HKL_IP4_TCP_UDP_L4_PSH)
|
||||
#define IS2_HKL_IP4_TCP_UDP_L4_ACK 1
|
||||
#define IS2_HKO_IP4_TCP_UDP_L4_URG \
|
||||
(IS2_HKO_IP4_TCP_UDP_L4_ACK + IS2_HKL_IP4_TCP_UDP_L4_ACK)
|
||||
#define IS2_HKL_IP4_TCP_UDP_L4_URG 1
|
||||
#define IS2_HKO_IP4_TCP_UDP_L4_1588_DOM \
|
||||
(IS2_HKO_IP4_TCP_UDP_L4_URG + IS2_HKL_IP4_TCP_UDP_L4_URG)
|
||||
#define IS2_HKL_IP4_TCP_UDP_L4_1588_DOM 8
|
||||
#define IS2_HKO_IP4_TCP_UDP_L4_1588_VER \
|
||||
(IS2_HKO_IP4_TCP_UDP_L4_1588_DOM + IS2_HKL_IP4_TCP_UDP_L4_1588_DOM)
|
||||
#define IS2_HKL_IP4_TCP_UDP_L4_1588_VER 4
|
||||
|
||||
/* IS2 half key - IP4_OTHER */
|
||||
#define IS2_HKO_IP4_OTHER_L3_PROTO IS2_HKO_IP4_TCP_UDP_TCP
|
||||
#define IS2_HKL_IP4_OTHER_L3_PROTO 8
|
||||
#define IS2_HKO_IP4_OTHER_L3_PAYLOAD \
|
||||
(IS2_HKO_IP4_OTHER_L3_PROTO + IS2_HKL_IP4_OTHER_L3_PROTO)
|
||||
#define IS2_HKL_IP4_OTHER_L3_PAYLOAD 56
|
||||
|
||||
/* IS2 half key - IP6_STD */
|
||||
#define IS2_HKO_IP6_STD_L3_TTL_GT0 IS2_HKO_L2_DMAC
|
||||
#define IS2_HKL_IP6_STD_L3_TTL_GT0 1
|
||||
#define IS2_HKO_IP6_STD_L3_IP6_SIP \
|
||||
(IS2_HKO_IP6_STD_L3_TTL_GT0 + IS2_HKL_IP6_STD_L3_TTL_GT0)
|
||||
#define IS2_HKL_IP6_STD_L3_IP6_SIP 128
|
||||
#define IS2_HKO_IP6_STD_L3_PROTO \
|
||||
(IS2_HKO_IP6_STD_L3_IP6_SIP + IS2_HKL_IP6_STD_L3_IP6_SIP)
|
||||
#define IS2_HKL_IP6_STD_L3_PROTO 8
|
||||
|
||||
/* IS2 half key - OAM */
|
||||
#define IS2_HKO_OAM_OAM_MEL_FLAGS IS2_HKO_MAC_ETYPE_ETYPE
|
||||
#define IS2_HKL_OAM_OAM_MEL_FLAGS 7
|
||||
#define IS2_HKO_OAM_OAM_VER \
|
||||
(IS2_HKO_OAM_OAM_MEL_FLAGS + IS2_HKL_OAM_OAM_MEL_FLAGS)
|
||||
#define IS2_HKL_OAM_OAM_VER 5
|
||||
#define IS2_HKO_OAM_OAM_OPCODE (IS2_HKO_OAM_OAM_VER + IS2_HKL_OAM_OAM_VER)
|
||||
#define IS2_HKL_OAM_OAM_OPCODE 8
|
||||
#define IS2_HKO_OAM_OAM_FLAGS (IS2_HKO_OAM_OAM_OPCODE + IS2_HKL_OAM_OAM_OPCODE)
|
||||
#define IS2_HKL_OAM_OAM_FLAGS 8
|
||||
#define IS2_HKO_OAM_OAM_MEPID (IS2_HKO_OAM_OAM_FLAGS + IS2_HKL_OAM_OAM_FLAGS)
|
||||
#define IS2_HKL_OAM_OAM_MEPID 16
|
||||
#define IS2_HKO_OAM_OAM_CCM_CNTS_EQ0 \
|
||||
(IS2_HKO_OAM_OAM_MEPID + IS2_HKL_OAM_OAM_MEPID)
|
||||
#define IS2_HKL_OAM_OAM_CCM_CNTS_EQ0 1
|
||||
|
||||
/* IS2 half key - SMAC_SIP6 */
|
||||
#define IS2_HKO_SMAC_SIP6_IGR_PORT IS2_HKL_TYPE
|
||||
#define IS2_HKL_SMAC_SIP6_IGR_PORT VCAP_PORT_WIDTH
|
||||
#define IS2_HKO_SMAC_SIP6_L2_SMAC \
|
||||
(IS2_HKO_SMAC_SIP6_IGR_PORT + IS2_HKL_SMAC_SIP6_IGR_PORT)
|
||||
#define IS2_HKL_SMAC_SIP6_L2_SMAC 48
|
||||
#define IS2_HKO_SMAC_SIP6_L3_IP6_SIP \
|
||||
(IS2_HKO_SMAC_SIP6_L2_SMAC + IS2_HKL_SMAC_SIP6_L2_SMAC)
|
||||
#define IS2_HKL_SMAC_SIP6_L3_IP6_SIP 128
|
||||
|
||||
/* IS2 full key - common */
|
||||
#define IS2_FKO_TYPE 0
|
||||
#define IS2_FKL_TYPE 2
|
||||
#define IS2_FKO_FIRST (IS2_FKO_TYPE + IS2_FKL_TYPE)
|
||||
#define IS2_FKL_FIRST 1
|
||||
#define IS2_FKO_PAG (IS2_FKO_FIRST + IS2_FKL_FIRST)
|
||||
#define IS2_FKL_PAG 8
|
||||
#define IS2_FKO_IGR_PORT_MASK (IS2_FKO_PAG + IS2_FKL_PAG)
|
||||
#define IS2_FKL_IGR_PORT_MASK (VCAP_PORT_CNT + 1)
|
||||
#define IS2_FKO_SERVICE_FRM (IS2_FKO_IGR_PORT_MASK + IS2_FKL_IGR_PORT_MASK)
|
||||
#define IS2_FKL_SERVICE_FRM 1
|
||||
#define IS2_FKO_HOST_MATCH (IS2_FKO_SERVICE_FRM + IS2_FKL_SERVICE_FRM)
|
||||
#define IS2_FKL_HOST_MATCH 1
|
||||
#define IS2_FKO_L2_MC (IS2_FKO_HOST_MATCH + IS2_FKL_HOST_MATCH)
|
||||
#define IS2_FKL_L2_MC 1
|
||||
#define IS2_FKO_L2_BC (IS2_FKO_L2_MC + IS2_FKL_L2_MC)
|
||||
#define IS2_FKL_L2_BC 1
|
||||
#define IS2_FKO_VLAN_TAGGED (IS2_FKO_L2_BC + IS2_FKL_L2_BC)
|
||||
#define IS2_FKL_VLAN_TAGGED 1
|
||||
#define IS2_FKO_VID (IS2_FKO_VLAN_TAGGED + IS2_FKL_VLAN_TAGGED)
|
||||
#define IS2_FKL_VID 12
|
||||
#define IS2_FKO_DEI (IS2_FKO_VID + IS2_FKL_VID)
|
||||
#define IS2_FKL_DEI 1
|
||||
#define IS2_FKO_PCP (IS2_FKO_DEI + IS2_FKL_DEI)
|
||||
#define IS2_FKL_PCP 3
|
||||
|
||||
/* IS2 full key - IP6_TCP_UDP/IP6_OTHER common */
|
||||
#define IS2_FKO_L3_TTL_GT0 (IS2_FKO_PCP + IS2_FKL_PCP)
|
||||
#define IS2_FKL_L3_TTL_GT0 1
|
||||
#define IS2_FKO_L3_TOS (IS2_FKO_L3_TTL_GT0 + IS2_FKL_L3_TTL_GT0)
|
||||
#define IS2_FKL_L3_TOS 8
|
||||
#define IS2_FKO_L3_IP6_DIP (IS2_FKO_L3_TOS + IS2_FKL_L3_TOS)
|
||||
#define IS2_FKL_L3_IP6_DIP 128
|
||||
#define IS2_FKO_L3_IP6_SIP (IS2_FKO_L3_IP6_DIP + IS2_FKL_L3_IP6_DIP)
|
||||
#define IS2_FKL_L3_IP6_SIP 128
|
||||
#define IS2_FKO_DIP_EQ_SIP (IS2_FKO_L3_IP6_SIP + IS2_FKL_L3_IP6_SIP)
|
||||
#define IS2_FKL_DIP_EQ_SIP 1
|
||||
|
||||
/* IS2 full key - IP6_TCP_UDP */
|
||||
#define IS2_FKO_IP6_TCP_UDP_TCP (IS2_FKO_DIP_EQ_SIP + IS2_FKL_DIP_EQ_SIP)
|
||||
#define IS2_FKL_IP6_TCP_UDP_TCP 1
|
||||
#define IS2_FKO_IP6_TCP_UDP_L4_DPORT \
|
||||
(IS2_FKO_IP6_TCP_UDP_TCP + IS2_FKL_IP6_TCP_UDP_TCP)
|
||||
#define IS2_FKL_IP6_TCP_UDP_L4_DPORT 16
|
||||
#define IS2_FKO_IP6_TCP_UDP_L4_SPORT \
|
||||
(IS2_FKO_IP6_TCP_UDP_L4_DPORT + IS2_FKL_IP6_TCP_UDP_L4_DPORT)
|
||||
#define IS2_FKL_IP6_TCP_UDP_L4_SPORT 16
|
||||
#define IS2_FKO_IP6_TCP_UDP_L4_RNG \
|
||||
(IS2_FKO_IP6_TCP_UDP_L4_SPORT + IS2_FKL_IP6_TCP_UDP_L4_SPORT)
|
||||
#define IS2_FKL_IP6_TCP_UDP_L4_RNG 8
|
||||
#define IS2_FKO_IP6_TCP_UDP_SPORT_EQ_DPORT \
|
||||
(IS2_FKO_IP6_TCP_UDP_L4_RNG + IS2_FKL_IP6_TCP_UDP_L4_RNG)
|
||||
#define IS2_FKL_IP6_TCP_UDP_SPORT_EQ_DPORT 1
|
||||
#define IS2_FKO_IP6_TCP_UDP_SEQUENCE_EQ0 \
|
||||
(IS2_FKO_IP6_TCP_UDP_SPORT_EQ_DPORT + \
|
||||
IS2_FKL_IP6_TCP_UDP_SPORT_EQ_DPORT)
|
||||
#define IS2_FKL_IP6_TCP_UDP_SEQUENCE_EQ0 1
|
||||
#define IS2_FKO_IP6_TCP_UDP_L4_FIN \
|
||||
(IS2_FKO_IP6_TCP_UDP_SEQUENCE_EQ0 + IS2_FKL_IP6_TCP_UDP_SEQUENCE_EQ0)
|
||||
#define IS2_FKL_IP6_TCP_UDP_L4_FIN 1
|
||||
#define IS2_FKO_IP6_TCP_UDP_L4_SYN \
|
||||
(IS2_FKO_IP6_TCP_UDP_L4_FIN + IS2_FKL_IP6_TCP_UDP_L4_FIN)
|
||||
#define IS2_FKL_IP6_TCP_UDP_L4_SYN 1
|
||||
#define IS2_FKO_IP6_TCP_UDP_L4_RST \
|
||||
(IS2_FKO_IP6_TCP_UDP_L4_SYN + IS2_FKL_IP6_TCP_UDP_L4_SYN)
|
||||
#define IS2_FKL_IP6_TCP_UDP_L4_RST 1
|
||||
#define IS2_FKO_IP6_TCP_UDP_L4_PSH \
|
||||
(IS2_FKO_IP6_TCP_UDP_L4_RST + IS2_FKL_IP6_TCP_UDP_L4_RST)
|
||||
#define IS2_FKL_IP6_TCP_UDP_L4_PSH 1
|
||||
#define IS2_FKO_IP6_TCP_UDP_L4_ACK \
|
||||
(IS2_FKO_IP6_TCP_UDP_L4_PSH + IS2_FKL_IP6_TCP_UDP_L4_PSH)
|
||||
#define IS2_FKL_IP6_TCP_UDP_L4_ACK 1
|
||||
#define IS2_FKO_IP6_TCP_UDP_L4_URG \
|
||||
(IS2_FKO_IP6_TCP_UDP_L4_ACK + IS2_FKL_IP6_TCP_UDP_L4_ACK)
|
||||
#define IS2_FKL_IP6_TCP_UDP_L4_URG 1
|
||||
#define IS2_FKO_IP6_TCP_UDP_L4_1588_DOM \
|
||||
(IS2_FKO_IP6_TCP_UDP_L4_URG + IS2_FKL_IP6_TCP_UDP_L4_URG)
|
||||
#define IS2_FKL_IP6_TCP_UDP_L4_1588_DOM 8
|
||||
#define IS2_FKO_IP6_TCP_UDP_L4_1588_VER \
|
||||
(IS2_FKO_IP6_TCP_UDP_L4_1588_DOM + IS2_FKL_IP6_TCP_UDP_L4_1588_DOM)
|
||||
#define IS2_FKL_IP6_TCP_UDP_L4_1588_VER 4
|
||||
|
||||
/* IS2 full key - IP6_OTHER */
|
||||
#define IS2_FKO_IP6_OTHER_L3_PROTO IS2_FKO_IP6_TCP_UDP_TCP
|
||||
#define IS2_FKL_IP6_OTHER_L3_PROTO 8
|
||||
#define IS2_FKO_IP6_OTHER_L3_PAYLOAD \
|
||||
(IS2_FKO_IP6_OTHER_L3_PROTO + IS2_FKL_IP6_OTHER_L3_PROTO)
|
||||
#define IS2_FKL_IP6_OTHER_L3_PAYLOAD 56
|
||||
|
||||
/* IS2 full key - CUSTOM */
|
||||
#define IS2_FKO_CUSTOM_CUSTOM_TYPE IS2_FKO_L3_TTL_GT0
|
||||
#define IS2_FKL_CUSTOM_CUSTOM_TYPE 1
|
||||
#define IS2_FKO_CUSTOM_CUSTOM \
|
||||
(IS2_FKO_CUSTOM_CUSTOM_TYPE + IS2_FKL_CUSTOM_CUSTOM_TYPE)
|
||||
#define IS2_FKL_CUSTOM_CUSTOM 320
|
||||
|
||||
/* IS2 action - BASE_TYPE */
|
||||
#define IS2_AO_HIT_ME_ONCE 0
|
||||
#define IS2_AL_HIT_ME_ONCE 1
|
||||
#define IS2_AO_CPU_COPY_ENA (IS2_AO_HIT_ME_ONCE + IS2_AL_HIT_ME_ONCE)
|
||||
#define IS2_AL_CPU_COPY_ENA 1
|
||||
#define IS2_AO_CPU_QU_NUM (IS2_AO_CPU_COPY_ENA + IS2_AL_CPU_COPY_ENA)
|
||||
#define IS2_AL_CPU_QU_NUM 3
|
||||
#define IS2_AO_MASK_MODE (IS2_AO_CPU_QU_NUM + IS2_AL_CPU_QU_NUM)
|
||||
#define IS2_AL_MASK_MODE 2
|
||||
#define IS2_AO_MIRROR_ENA (IS2_AO_MASK_MODE + IS2_AL_MASK_MODE)
|
||||
#define IS2_AL_MIRROR_ENA 1
|
||||
#define IS2_AO_LRN_DIS (IS2_AO_MIRROR_ENA + IS2_AL_MIRROR_ENA)
|
||||
#define IS2_AL_LRN_DIS 1
|
||||
#define IS2_AO_POLICE_ENA (IS2_AO_LRN_DIS + IS2_AL_LRN_DIS)
|
||||
#define IS2_AL_POLICE_ENA 1
|
||||
#define IS2_AO_POLICE_IDX (IS2_AO_POLICE_ENA + IS2_AL_POLICE_ENA)
|
||||
#define IS2_AL_POLICE_IDX 9
|
||||
#define IS2_AO_POLICE_VCAP_ONLY (IS2_AO_POLICE_IDX + IS2_AL_POLICE_IDX)
|
||||
#define IS2_AL_POLICE_VCAP_ONLY 1
|
||||
#define IS2_AO_PORT_MASK (IS2_AO_POLICE_VCAP_ONLY + IS2_AL_POLICE_VCAP_ONLY)
|
||||
#define IS2_AL_PORT_MASK VCAP_PORT_CNT
|
||||
#define IS2_AO_REW_OP (IS2_AO_PORT_MASK + IS2_AL_PORT_MASK)
|
||||
#define IS2_AL_REW_OP 9
|
||||
#define IS2_AO_LM_CNT_DIS (IS2_AO_REW_OP + IS2_AL_REW_OP)
|
||||
#define IS2_AL_LM_CNT_DIS 1
|
||||
#define IS2_AO_ISDX_ENA \
|
||||
(IS2_AO_LM_CNT_DIS + IS2_AL_LM_CNT_DIS + 1) /* Reserved bit */
|
||||
#define IS2_AL_ISDX_ENA 1
|
||||
#define IS2_AO_ACL_ID (IS2_AO_ISDX_ENA + IS2_AL_ISDX_ENA)
|
||||
#define IS2_AL_ACL_ID 6
|
||||
|
||||
/* IS2 action - SMAC_SIP */
|
||||
#define IS2_AO_SMAC_SIP_CPU_COPY_ENA 0
|
||||
#define IS2_AL_SMAC_SIP_CPU_COPY_ENA 1
|
||||
#define IS2_AO_SMAC_SIP_CPU_QU_NUM 1
|
||||
#define IS2_AL_SMAC_SIP_CPU_QU_NUM 3
|
||||
#define IS2_AO_SMAC_SIP_FWD_KILL_ENA 4
|
||||
#define IS2_AL_SMAC_SIP_FWD_KILL_ENA 1
|
||||
#define IS2_AO_SMAC_SIP_HOST_MATCH 5
|
||||
#define IS2_AL_SMAC_SIP_HOST_MATCH 1
|
||||
|
||||
#endif /* _OCELOT_VCAP_H_ */
|
||||
Reference in New Issue
Block a user