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net-next/hinic: Add wq

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Create work queues for being used by the queue pairs.

Signed-off-by: Aviad Krawczyk <aviad.krawczyk@huawei.com>
Signed-off-by: Zhao Chen <zhaochen6@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Aviad Krawczyk
2017-08-21 23:55:57 +08:00
committed by David S. Miller
parent c3e79baf1b
commit b15a9f37be
8 changed files with 968 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/ethernet/huawei/hinic/Makefile
View File

@@ -1,5 +1,5 @@
obj-$(CONFIG_HINIC) += hinic.o
hinic-y := hinic_main.o hinic_tx.o hinic_rx.o hinic_port.o hinic_hw_dev.o \
hinic_hw_io.o hinic_hw_mgmt.o hinic_hw_api_cmd.o hinic_hw_eqs.o \
hinic_hw_if.o
hinic_hw_io.o hinic_hw_wq.o hinic_hw_mgmt.o hinic_hw_api_cmd.o \
hinic_hw_eqs.o hinic_hw_if.o

25
drivers/net/ethernet/huawei/hinic/hinic_common.h Normal file
View File

@@ -0,0 +1,25 @@
/*
* Huawei HiNIC PCI Express Linux driver
* Copyright(c) 2017 Huawei Technologies Co., Ltd
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
*/
#ifndef HINIC_COMMON_H
#define HINIC_COMMON_H
struct hinic_sge {
u32 hi_addr;
u32 lo_addr;
u32 len;
};
#endif

69
drivers/net/ethernet/huawei/hinic/hinic_hw_io.c
View File

@@ -20,6 +20,8 @@
#include <linux/slab.h>
#include "hinic_hw_if.h"
#include "hinic_hw_wqe.h"
#include "hinic_hw_wq.h"
#include "hinic_hw_qp.h"
#include "hinic_hw_io.h"
@@ -38,8 +40,33 @@ static int init_qp(struct hinic_func_to_io *func_to_io,
struct msix_entry *sq_msix_entry,
struct msix_entry *rq_msix_entry)
{
/* should be implemented */
struct hinic_hwif *hwif = func_to_io->hwif;
struct pci_dev *pdev = hwif->pdev;
int err;
qp->q_id = q_id;
err = hinic_wq_allocate(&func_to_io->wqs, &func_to_io->sq_wq[q_id],
HINIC_SQ_WQEBB_SIZE, HINIC_SQ_PAGE_SIZE,
HINIC_SQ_DEPTH, HINIC_SQ_WQE_MAX_SIZE);
if (err) {
dev_err(&pdev->dev, "Failed to allocate WQ for SQ\n");
return err;
}
err = hinic_wq_allocate(&func_to_io->wqs, &func_to_io->rq_wq[q_id],
HINIC_RQ_WQEBB_SIZE, HINIC_RQ_PAGE_SIZE,
HINIC_RQ_DEPTH, HINIC_RQ_WQE_SIZE);
if (err) {
dev_err(&pdev->dev, "Failed to allocate WQ for RQ\n");
goto err_rq_alloc;
}
return 0;
err_rq_alloc:
hinic_wq_free(&func_to_io->wqs, &func_to_io->sq_wq[q_id]);
return err;
}
/**
@@ -50,7 +77,10 @@ static int init_qp(struct hinic_func_to_io *func_to_io,
static void destroy_qp(struct hinic_func_to_io *func_to_io,
struct hinic_qp *qp)
{
/* should be implemented */
int q_id = qp->q_id;
hinic_wq_free(&func_to_io->wqs, &func_to_io->rq_wq[q_id]);
hinic_wq_free(&func_to_io->wqs, &func_to_io->sq_wq[q_id]);
}
/**
@@ -70,7 +100,7 @@ int hinic_io_create_qps(struct hinic_func_to_io *func_to_io,
{
struct hinic_hwif *hwif = func_to_io->hwif;
struct pci_dev *pdev = hwif->pdev;
size_t qps_size;
size_t qps_size, wq_size;
int i, j, err;
qps_size = num_qps * sizeof(*func_to_io->qps);
@@ -78,6 +108,20 @@ int hinic_io_create_qps(struct hinic_func_to_io *func_to_io,
if (!func_to_io->qps)
return -ENOMEM;
wq_size = num_qps * sizeof(*func_to_io->sq_wq);
func_to_io->sq_wq = devm_kzalloc(&pdev->dev, wq_size, GFP_KERNEL);
if (!func_to_io->sq_wq) {
err = -ENOMEM;
goto err_sq_wq;
}
wq_size = num_qps * sizeof(*func_to_io->rq_wq);
func_to_io->rq_wq = devm_kzalloc(&pdev->dev, wq_size, GFP_KERNEL);
if (!func_to_io->rq_wq) {
err = -ENOMEM;
goto err_rq_wq;
}
for (i = 0; i < num_qps; i++) {
err = init_qp(func_to_io, &func_to_io->qps[i], i,
&sq_msix_entries[i], &rq_msix_entries[i]);
@@ -93,6 +137,12 @@ err_init_qp:
for (j = 0; j < i; j++)
destroy_qp(func_to_io, &func_to_io->qps[j]);
devm_kfree(&pdev->dev, func_to_io->rq_wq);
err_rq_wq:
devm_kfree(&pdev->dev, func_to_io->sq_wq);
err_sq_wq:
devm_kfree(&pdev->dev, func_to_io->qps);
return err;
}
@@ -111,6 +161,9 @@ void hinic_io_destroy_qps(struct hinic_func_to_io *func_to_io, int num_qps)
for (i = 0; i < num_qps; i++)
destroy_qp(func_to_io, &func_to_io->qps[i]);
devm_kfree(&pdev->dev, func_to_io->rq_wq);
devm_kfree(&pdev->dev, func_to_io->sq_wq);
devm_kfree(&pdev->dev, func_to_io->qps);
}
@@ -128,10 +181,19 @@ int hinic_io_init(struct hinic_func_to_io *func_to_io,
struct hinic_hwif *hwif, u16 max_qps, int num_ceqs,
struct msix_entry *ceq_msix_entries)
{
struct pci_dev *pdev = hwif->pdev;
int err;
func_to_io->hwif = hwif;
func_to_io->qps = NULL;
func_to_io->max_qps = max_qps;
err = hinic_wqs_alloc(&func_to_io->wqs, 2 * max_qps, hwif);
if (err) {
dev_err(&pdev->dev, "Failed to allocate WQS for IO\n");
return err;
}
return 0;
}
@@ -141,4 +203,5 @@ int hinic_io_init(struct hinic_func_to_io *func_to_io,
**/
void hinic_io_free(struct hinic_func_to_io *func_to_io)
{
hinic_wqs_free(&func_to_io->wqs);
}

6
drivers/net/ethernet/huawei/hinic/hinic_hw_io.h
View File

@@ -20,11 +20,17 @@
#include <linux/pci.h>
#include "hinic_hw_if.h"
#include "hinic_hw_wq.h"
#include "hinic_hw_qp.h"
struct hinic_func_to_io {
struct hinic_hwif *hwif;
struct hinic_wqs wqs;
struct hinic_wq *sq_wq;
struct hinic_wq *rq_wq;
struct hinic_qp *qps;
u16 max_qps;
};

14
drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h
View File

@@ -16,6 +16,18 @@
#ifndef HINIC_HW_QP_H
#define HINIC_HW_QP_H
#include <linux/types.h>
#include <linux/sizes.h>
#define HINIC_SQ_WQEBB_SIZE 64
#define HINIC_RQ_WQEBB_SIZE 32
#define HINIC_SQ_PAGE_SIZE SZ_4K
#define HINIC_RQ_PAGE_SIZE SZ_4K
#define HINIC_SQ_DEPTH SZ_4K
#define HINIC_RQ_DEPTH SZ_4K
struct hinic_sq {
/* should be implemented */
};
@@ -27,6 +39,8 @@ struct hinic_rq {
struct hinic_qp {
struct hinic_sq sq;
struct hinic_rq rq;
u16 q_id;
};
#endif

516
drivers/net/ethernet/huawei/hinic/hinic_hw_wq.c Normal file
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File diff suppressed because it is too large Load Diff

86
drivers/net/ethernet/huawei/hinic/hinic_hw_wq.h Normal file
View File

@@ -0,0 +1,86 @@
/*
* Huawei HiNIC PCI Express Linux driver
* Copyright(c) 2017 Huawei Technologies Co., Ltd
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
*/
#ifndef HINIC_HW_WQ_H
#define HINIC_HW_WQ_H
#include <linux/types.h>
#include <linux/semaphore.h>
#include <linux/atomic.h>
#include "hinic_hw_if.h"
struct hinic_free_block {
int page_idx;
int block_idx;
};
struct hinic_wq {
struct hinic_hwif *hwif;
int page_idx;
int block_idx;
u16 wqebb_size;
u16 wq_page_size;
u16 q_depth;
u16 max_wqe_size;
u16 num_wqebbs_per_page;
/* The addresses are 64 bit in the HW */
u64 block_paddr;
void **shadow_block_vaddr;
u64 *block_vaddr;
int num_q_pages;
u8 *shadow_wqe;
u16 *shadow_idx;
atomic_t cons_idx;
atomic_t prod_idx;
atomic_t delta;
u16 mask;
};
struct hinic_wqs {
struct hinic_hwif *hwif;
int num_pages;
/* The addresses are 64 bit in the HW */
u64 *page_paddr;
u64 **page_vaddr;
void ***shadow_page_vaddr;
struct hinic_free_block *free_blocks;
int alloc_blk_pos;
int return_blk_pos;
int num_free_blks;
/* Lock for getting a free block from the WQ set */
struct semaphore alloc_blocks_lock;
};
int hinic_wqs_alloc(struct hinic_wqs *wqs, int num_wqs,
struct hinic_hwif *hwif);
void hinic_wqs_free(struct hinic_wqs *wqs);
int hinic_wq_allocate(struct hinic_wqs *wqs, struct hinic_wq *wq,
u16 wqebb_size, u16 wq_page_size, u16 q_depth,
u16 max_wqe_size);
void hinic_wq_free(struct hinic_wqs *wqs, struct hinic_wq *wq);
#endif

253
drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h Normal file
View File

@@ -0,0 +1,253 @@
/*
* Huawei HiNIC PCI Express Linux driver
* Copyright(c) 2017 Huawei Technologies Co., Ltd
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
*/
#ifndef HINIC_HW_WQE_H
#define HINIC_HW_WQE_H
#include "hinic_common.h"
#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0
#define HINIC_SQ_CTRL_TASKSECT_LEN_SHIFT 16
#define HINIC_SQ_CTRL_DATA_FORMAT_SHIFT 22
#define HINIC_SQ_CTRL_LEN_SHIFT 29
#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF
#define HINIC_SQ_CTRL_TASKSECT_LEN_MASK 0x1F
#define HINIC_SQ_CTRL_DATA_FORMAT_MASK 0x1
#define HINIC_SQ_CTRL_LEN_MASK 0x3
#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_SHIFT 13
#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK 0x3FFF
#define HINIC_SQ_CTRL_SET(val, member) \
(((u32)(val) & HINIC_SQ_CTRL_##member##_MASK) \
<< HINIC_SQ_CTRL_##member##_SHIFT)
#define HINIC_SQ_CTRL_GET(val, member) \
(((val) >> HINIC_SQ_CTRL_##member##_SHIFT) \
& HINIC_SQ_CTRL_##member##_MASK)
#define HINIC_SQ_TASK_INFO0_L2HDR_LEN_SHIFT 0
#define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_SHIFT 8
#define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_SHIFT 10
#define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT 12
#define HINIC_SQ_TASK_INFO0_PARSE_FLAG_SHIFT 13
/* 1 bit reserved */
#define HINIC_SQ_TASK_INFO0_TSO_FLAG_SHIFT 15
#define HINIC_SQ_TASK_INFO0_VLAN_TAG_SHIFT 16
#define HINIC_SQ_TASK_INFO0_L2HDR_LEN_MASK 0xFF
#define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_MASK 0x3
#define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_MASK 0x3
#define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_MASK 0x1
#define HINIC_SQ_TASK_INFO0_PARSE_FLAG_MASK 0x1
/* 1 bit reserved */
#define HINIC_SQ_TASK_INFO0_TSO_FLAG_MASK 0x1
#define HINIC_SQ_TASK_INFO0_VLAN_TAG_MASK 0xFFFF
#define HINIC_SQ_TASK_INFO0_SET(val, member) \
(((u32)(val) & HINIC_SQ_TASK_INFO0_##member##_MASK) << \
HINIC_SQ_TASK_INFO0_##member##_SHIFT)
/* 8 bits reserved */
#define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_SHIFT 8
#define HINIC_SQ_TASK_INFO1_INNER_L4_LEN_SHIFT 16
#define HINIC_SQ_TASK_INFO1_INNER_L3_LEN_SHIFT 24
/* 8 bits reserved */
#define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_MASK 0xFF
#define HINIC_SQ_TASK_INFO1_INNER_L4_LEN_MASK 0xFF
#define HINIC_SQ_TASK_INFO1_INNER_L3_LEN_MASK 0xFF
#define HINIC_SQ_TASK_INFO1_SET(val, member) \
(((u32)(val) & HINIC_SQ_TASK_INFO1_##member##_MASK) << \
HINIC_SQ_TASK_INFO1_##member##_SHIFT)
#define HINIC_SQ_TASK_INFO2_TUNNEL_L4_LEN_SHIFT 0
#define HINIC_SQ_TASK_INFO2_OUTER_L3_LEN_SHIFT 12
#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT 19
/* 1 bit reserved */
#define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT 22
/* 8 bits reserved */
#define HINIC_SQ_TASK_INFO2_TUNNEL_L4_LEN_MASK 0xFFF
#define HINIC_SQ_TASK_INFO2_OUTER_L3_LEN_MASK 0x7F
#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK 0x3
/* 1 bit reserved */
#define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_MASK 0x3
/* 8 bits reserved */
#define HINIC_SQ_TASK_INFO2_SET(val, member) \
(((u32)(val) & HINIC_SQ_TASK_INFO2_##member##_MASK) << \
HINIC_SQ_TASK_INFO2_##member##_SHIFT)
/* 31 bits reserved */
#define HINIC_SQ_TASK_INFO4_L2TYPE_SHIFT 31
/* 31 bits reserved */
#define HINIC_SQ_TASK_INFO4_L2TYPE_MASK 0x1
#define HINIC_SQ_TASK_INFO4_SET(val, member) \
(((u32)(val) & HINIC_SQ_TASK_INFO4_##member##_MASK) << \
HINIC_SQ_TASK_INFO4_##member##_SHIFT)
#define HINIC_RQ_CQE_STATUS_RXDONE_SHIFT 31
#define HINIC_RQ_CQE_STATUS_RXDONE_MASK 0x1
#define HINIC_RQ_CQE_STATUS_GET(val, member) \
(((val) >> HINIC_RQ_CQE_STATUS_##member##_SHIFT) & \
HINIC_RQ_CQE_STATUS_##member##_MASK)
#define HINIC_RQ_CQE_STATUS_CLEAR(val, member) \
((val) & (~(HINIC_RQ_CQE_STATUS_##member##_MASK << \
HINIC_RQ_CQE_STATUS_##member##_SHIFT)))
#define HINIC_RQ_CQE_SGE_LEN_SHIFT 16
#define HINIC_RQ_CQE_SGE_LEN_MASK 0xFFFF
#define HINIC_RQ_CQE_SGE_GET(val, member) \
(((val) >> HINIC_RQ_CQE_SGE_##member##_SHIFT) & \
HINIC_RQ_CQE_SGE_##member##_MASK)
#define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0
#define HINIC_RQ_CTRL_COMPLETE_FORMAT_SHIFT 15
#define HINIC_RQ_CTRL_COMPLETE_LEN_SHIFT 27
#define HINIC_RQ_CTRL_LEN_SHIFT 29
#define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF
#define HINIC_RQ_CTRL_COMPLETE_FORMAT_MASK 0x1
#define HINIC_RQ_CTRL_COMPLETE_LEN_MASK 0x3
#define HINIC_RQ_CTRL_LEN_MASK 0x3
#define HINIC_RQ_CTRL_SET(val, member) \
(((u32)(val) & HINIC_RQ_CTRL_##member##_MASK) << \
HINIC_RQ_CTRL_##member##_SHIFT)
#define HINIC_SQ_WQE_SIZE(nr_sges) \
(sizeof(struct hinic_sq_ctrl) + \
sizeof(struct hinic_sq_task) + \
(nr_sges) * sizeof(struct hinic_sq_bufdesc))
#define HINIC_MAX_SQ_BUFDESCS 17
#define HINIC_SQ_WQE_MAX_SIZE 320
#define HINIC_RQ_WQE_SIZE 32
enum hinic_l4offload_type {
HINIC_L4_OFF_DISABLE = 0,
HINIC_TCP_OFFLOAD_ENABLE = 1,
HINIC_SCTP_OFFLOAD_ENABLE = 2,
HINIC_UDP_OFFLOAD_ENABLE = 3,
};
enum hinic_vlan_offload {
HINIC_VLAN_OFF_DISABLE = 0,
HINIC_VLAN_OFF_ENABLE = 1,
};
enum hinic_pkt_parsed {
HINIC_PKT_NOT_PARSED = 0,
HINIC_PKT_PARSED = 1,
};
enum hinic_outer_l3type {
HINIC_OUTER_L3TYPE_UNKNOWN = 0,
HINIC_OUTER_L3TYPE_IPV6 = 1,
HINIC_OUTER_L3TYPE_IPV4_NO_CHKSUM = 2,
HINIC_OUTER_L3TYPE_IPV4_CHKSUM = 3,
};
enum hinic_media_type {
HINIC_MEDIA_UNKNOWN = 0,
};
enum hinic_l2type {
HINIC_L2TYPE_ETH = 0,
};
enum hinc_tunnel_l4type {
HINIC_TUNNEL_L4TYPE_UNKNOWN = 0,
};
struct hinic_sq_ctrl {
u32 ctrl_info;
u32 queue_info;
};
struct hinic_sq_task {
u32 pkt_info0;
u32 pkt_info1;
u32 pkt_info2;
u32 ufo_v6_identify;
u32 pkt_info4;
u32 zero_pad;
};
struct hinic_sq_bufdesc {
struct hinic_sge sge;
u32 rsvd;
};
struct hinic_sq_wqe {
struct hinic_sq_ctrl ctrl;
struct hinic_sq_task task;
struct hinic_sq_bufdesc buf_descs[HINIC_MAX_SQ_BUFDESCS];
};
struct hinic_rq_cqe {
u32 status;
u32 len;
u32 rsvd2;
u32 rsvd3;
u32 rsvd4;
u32 rsvd5;
u32 rsvd6;
u32 rsvd7;
};
struct hinic_rq_ctrl {
u32 ctrl_info;
};
struct hinic_rq_cqe_sect {
struct hinic_sge sge;
u32 rsvd;
};
struct hinic_rq_bufdesc {
u32 hi_addr;
u32 lo_addr;
};
struct hinic_rq_wqe {
struct hinic_rq_ctrl ctrl;
u32 rsvd;
struct hinic_rq_cqe_sect cqe_sect;
struct hinic_rq_bufdesc buf_desc;
};
struct hinic_hw_wqe {
/* HW Format */
union {
struct hinic_sq_wqe sq_wqe;
struct hinic_rq_wqe rq_wqe;
};
};
#endif