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igb: PCI-Express 82575 Gigabit Ethernet driver
We are pleased to announce a new Gigabit Ethernet product and its driver to the linux community. This product is the Intel(R) 82575 Gigabit Ethernet adapter family. Physical adapters will be available to the public soon. These adapters come in 2- and 4-port versions (copper PHY) currently. Other variants will be available later. The 82575 chipset supports significantly different features that warrant a new driver. The descriptor format is (just like the ixgbe driver) different. The device can use multiple MSI-X vectors and multiple queues for both send and receive. This allows us to optimize some of the driver code specifically as well compared to the e1000-supported devices. This version of the igb driver no lnger uses fake netdevices and incorporates napi_struct members for each ring to do the multi- queue polling. multi-queue is enabled by default and the driver supports NAPI mode only. All the namespace collisions should be gone in this version too. The register macro's have been condensed to improve readability. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Auke Kok
committed by
David S. Miller
David S. Miller
parent
b491edd581
commit
9d5c824399
@@ -2019,6 +2019,28 @@ config IP1000
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To compile this driver as a module, choose M here: the module
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will be called ipg. This is recommended.
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config IGB
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tristate "Intel(R) 82575 PCI-Express Gigabit Ethernet support"
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depends on PCI
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---help---
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This driver supports Intel(R) 82575 gigabit ethernet family of
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adapters. For more information on how to identify your adapter, go
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to the Adapter & Driver ID Guide at:
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<http://support.intel.com/support/network/adapter/pro100/21397.htm>
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For general information and support, go to the Intel support
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website at:
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<http://support.intel.com>
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More specific information on configuring the driver is in
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<file:Documentation/networking/e1000.txt>.
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To compile this driver as a module, choose M here and read
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<file:Documentation/networking/net-modules.txt>. The module
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will be called igb.
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source "drivers/net/ixp2000/Kconfig"
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config MYRI_SBUS
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@@ -6,6 +6,7 @@ obj-$(CONFIG_E1000) += e1000/
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obj-$(CONFIG_E1000E) += e1000e/
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obj-$(CONFIG_IBM_EMAC) += ibm_emac/
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obj-$(CONFIG_IBM_NEW_EMAC) += ibm_newemac/
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obj-$(CONFIG_IGB) += igb/
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obj-$(CONFIG_IXGBE) += ixgbe/
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obj-$(CONFIG_IXGB) += ixgb/
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obj-$(CONFIG_IP1000) += ipg.o
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37
drivers/net/igb/Makefile
Normal file
37
drivers/net/igb/Makefile
Normal file
@@ -0,0 +1,37 @@
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################################################################################
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#
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# Intel 82575 PCI-Express Ethernet Linux driver
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# Copyright(c) 1999 - 2007 Intel Corporation.
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# this program; if not, write to the Free Software Foundation, Inc.,
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# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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#
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# The full GNU General Public License is included in this distribution in
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# the file called "COPYING".
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#
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# Contact Information:
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# Linux NICS <linux.nics@intel.com>
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# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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#
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################################################################################
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#
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# Makefile for the Intel(R) 82575 PCI-Express ethernet driver
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#
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obj-$(CONFIG_IGB) += igb.o
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igb-objs := igb_main.o igb_ethtool.o e1000_82575.o \
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e1000_mac.o e1000_nvm.o e1000_phy.o
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1269
drivers/net/igb/e1000_82575.c
Normal file
1269
drivers/net/igb/e1000_82575.c
Normal file
File diff suppressed because it is too large
Load Diff
150
drivers/net/igb/e1000_82575.h
Normal file
150
drivers/net/igb/e1000_82575.h
Normal file
@@ -0,0 +1,150 @@
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/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _E1000_82575_H_
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#define _E1000_82575_H_
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#define E1000_RAR_ENTRIES_82575 16
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/* SRRCTL bit definitions */
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#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
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#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
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#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
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#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
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#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
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#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
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#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
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#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
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#define E1000_EICR_TX_QUEUE ( \
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E1000_EICR_TX_QUEUE0 | \
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E1000_EICR_TX_QUEUE1 | \
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E1000_EICR_TX_QUEUE2 | \
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E1000_EICR_TX_QUEUE3)
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#define E1000_EICR_RX_QUEUE ( \
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E1000_EICR_RX_QUEUE0 | \
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E1000_EICR_RX_QUEUE1 | \
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E1000_EICR_RX_QUEUE2 | \
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E1000_EICR_RX_QUEUE3)
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#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
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#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
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/* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */
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/* Receive Descriptor - Advanced */
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union e1000_adv_rx_desc {
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struct {
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u64 pkt_addr; /* Packet buffer address */
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u64 hdr_addr; /* Header buffer address */
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} read;
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struct {
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struct {
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struct {
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u16 pkt_info; /* RSS type, Packet type */
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u16 hdr_info; /* Split Header,
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* header buffer length */
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} lo_dword;
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union {
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u32 rss; /* RSS Hash */
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struct {
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u16 ip_id; /* IP id */
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u16 csum; /* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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u32 status_error; /* ext status/error */
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u16 length; /* Packet length */
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u16 vlan; /* VLAN tag */
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} upper;
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} wb; /* writeback */
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};
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#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
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#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
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/* RSS Hash results */
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/* RSS Packet Types as indicated in the receive descriptor */
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/* Transmit Descriptor - Advanced */
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union e1000_adv_tx_desc {
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struct {
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u64 buffer_addr; /* Address of descriptor's data buf */
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u32 cmd_type_len;
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u32 olinfo_status;
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} read;
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struct {
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u64 rsvd; /* Reserved */
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u32 nxtseq_seed;
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u32 status;
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} wb;
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};
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/* Adv Transmit Descriptor Config Masks */
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#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
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#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
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#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
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#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
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#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
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#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
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#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
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/* Context descriptors */
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struct e1000_adv_tx_context_desc {
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u32 vlan_macip_lens;
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u32 seqnum_seed;
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u32 type_tucmd_mlhl;
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u32 mss_l4len_idx;
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};
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#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
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#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
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#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
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/* IPSec Encrypt Enable for ESP */
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#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
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#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
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/* Adv ctxt IPSec SA IDX mask */
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/* Adv ctxt IPSec ESP len mask */
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/* Additional Transmit Descriptor Control definitions */
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#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
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/* Tx Queue Arbitration Priority 0=low, 1=high */
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/* Additional Receive Descriptor Control definitions */
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#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
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/* Direct Cache Access (DCA) definitions */
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#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* TX Desc writeback RO bit */
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#endif
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772
drivers/net/igb/e1000_defines.h
Normal file
772
drivers/net/igb/e1000_defines.h
Normal file
File diff suppressed because it is too large
Load Diff
599
drivers/net/igb/e1000_hw.h
Normal file
599
drivers/net/igb/e1000_hw.h
Normal file
File diff suppressed because it is too large
Load Diff
1505
drivers/net/igb/e1000_mac.c
Normal file
1505
drivers/net/igb/e1000_mac.c
Normal file
File diff suppressed because it is too large
Load Diff
98
drivers/net/igb/e1000_mac.h
Normal file
98
drivers/net/igb/e1000_mac.h
Normal file
@@ -0,0 +1,98 @@
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/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
|
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
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|
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You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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||||
|
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _E1000_MAC_H_
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#define _E1000_MAC_H_
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#include "e1000_hw.h"
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#include "e1000_phy.h"
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#include "e1000_nvm.h"
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#include "e1000_defines.h"
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/*
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* Functions that should not be called directly from drivers but can be used
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* by other files in this 'shared code'
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*/
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s32 igb_blink_led(struct e1000_hw *hw);
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s32 igb_check_for_copper_link(struct e1000_hw *hw);
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s32 igb_cleanup_led(struct e1000_hw *hw);
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s32 igb_config_fc_after_link_up(struct e1000_hw *hw);
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s32 igb_disable_pcie_master(struct e1000_hw *hw);
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s32 igb_force_mac_fc(struct e1000_hw *hw);
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s32 igb_get_auto_rd_done(struct e1000_hw *hw);
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s32 igb_get_bus_info_pcie(struct e1000_hw *hw);
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s32 igb_get_hw_semaphore(struct e1000_hw *hw);
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s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
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u16 *duplex);
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s32 igb_id_led_init(struct e1000_hw *hw);
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s32 igb_led_off(struct e1000_hw *hw);
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void igb_update_mc_addr_list(struct e1000_hw *hw,
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u8 *mc_addr_list, u32 mc_addr_count,
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u32 rar_used_count, u32 rar_count);
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s32 igb_setup_link(struct e1000_hw *hw);
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s32 igb_validate_mdi_setting(struct e1000_hw *hw);
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s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
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u32 offset, u8 data);
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void igb_clear_hw_cntrs_base(struct e1000_hw *hw);
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void igb_clear_vfta(struct e1000_hw *hw);
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void igb_config_collision_dist(struct e1000_hw *hw);
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void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
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void igb_put_hw_semaphore(struct e1000_hw *hw);
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void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
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s32 igb_check_alt_mac_addr(struct e1000_hw *hw);
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void igb_remove_device(struct e1000_hw *hw);
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void igb_reset_adaptive(struct e1000_hw *hw);
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void igb_update_adaptive(struct e1000_hw *hw);
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void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
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bool igb_enable_mng_pass_thru(struct e1000_hw *hw);
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enum e1000_mng_mode {
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e1000_mng_mode_none = 0,
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e1000_mng_mode_asf,
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e1000_mng_mode_pt,
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e1000_mng_mode_ipmi,
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e1000_mng_mode_host_if_only
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};
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#define E1000_FACTPS_MNGCG 0x20000000
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#define E1000_FWSM_MODE_MASK 0xE
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#define E1000_FWSM_MODE_SHIFT 1
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#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
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#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
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#define E1000_HICR_EN 0x01 /* Enable bit - RO */
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/* Driver sets this bit when done to put command in RAM */
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#define E1000_HICR_C 0x02
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extern void e1000_init_function_pointers_82575(struct e1000_hw *hw);
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#endif
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605
drivers/net/igb/e1000_nvm.c
Normal file
605
drivers/net/igb/e1000_nvm.c
Normal file
File diff suppressed because it is too large
Load Diff
40
drivers/net/igb/e1000_nvm.h
Normal file
40
drivers/net/igb/e1000_nvm.h
Normal file
@@ -0,0 +1,40 @@
|
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/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
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|
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#ifndef _E1000_NVM_H_
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#define _E1000_NVM_H_
|
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|
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s32 igb_acquire_nvm(struct e1000_hw *hw);
|
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void igb_release_nvm(struct e1000_hw *hw);
|
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s32 igb_read_mac_addr(struct e1000_hw *hw);
|
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s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num);
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s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
|
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s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
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s32 igb_validate_nvm_checksum(struct e1000_hw *hw);
|
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s32 igb_update_nvm_checksum(struct e1000_hw *hw);
|
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|
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#endif
|
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1807
drivers/net/igb/e1000_phy.c
Normal file
1807
drivers/net/igb/e1000_phy.c
Normal file
File diff suppressed because it is too large
Load Diff
98
drivers/net/igb/e1000_phy.h
Normal file
98
drivers/net/igb/e1000_phy.h
Normal file
@@ -0,0 +1,98 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _E1000_PHY_H_
|
||||
#define _E1000_PHY_H_
|
||||
|
||||
enum e1000_ms_type {
|
||||
e1000_ms_hw_default = 0,
|
||||
e1000_ms_force_master,
|
||||
e1000_ms_force_slave,
|
||||
e1000_ms_auto
|
||||
};
|
||||
|
||||
enum e1000_smart_speed {
|
||||
e1000_smart_speed_default = 0,
|
||||
e1000_smart_speed_on,
|
||||
e1000_smart_speed_off
|
||||
};
|
||||
|
||||
s32 igb_check_downshift(struct e1000_hw *hw);
|
||||
s32 igb_check_reset_block(struct e1000_hw *hw);
|
||||
s32 igb_copper_link_autoneg(struct e1000_hw *hw);
|
||||
s32 igb_phy_force_speed_duplex(struct e1000_hw *hw);
|
||||
s32 igb_copper_link_setup_igp(struct e1000_hw *hw);
|
||||
s32 igb_copper_link_setup_m88(struct e1000_hw *hw);
|
||||
s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
|
||||
s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
|
||||
s32 igb_get_cable_length_m88(struct e1000_hw *hw);
|
||||
s32 igb_get_cable_length_igp_2(struct e1000_hw *hw);
|
||||
s32 igb_get_phy_id(struct e1000_hw *hw);
|
||||
s32 igb_get_phy_info_igp(struct e1000_hw *hw);
|
||||
s32 igb_get_phy_info_m88(struct e1000_hw *hw);
|
||||
s32 igb_phy_sw_reset(struct e1000_hw *hw);
|
||||
s32 igb_phy_hw_reset(struct e1000_hw *hw);
|
||||
s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
|
||||
s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
|
||||
u32 usec_interval, bool *success);
|
||||
s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
|
||||
|
||||
/* IGP01E1000 Specific Registers */
|
||||
#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
|
||||
#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
|
||||
#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
|
||||
#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
|
||||
#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
|
||||
#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
|
||||
#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
|
||||
#define IGP01E1000_PHY_POLARITY_MASK 0x0078
|
||||
#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
|
||||
#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
|
||||
#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
|
||||
|
||||
/* Enable flexible speed on link-up */
|
||||
#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
|
||||
#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
|
||||
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
|
||||
#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
|
||||
#define IGP01E1000_PSSR_MDIX 0x0008
|
||||
#define IGP01E1000_PSSR_SPEED_MASK 0xC000
|
||||
#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
|
||||
#define IGP02E1000_PHY_CHANNEL_NUM 4
|
||||
#define IGP02E1000_PHY_AGC_A 0x11B1
|
||||
#define IGP02E1000_PHY_AGC_B 0x12B1
|
||||
#define IGP02E1000_PHY_AGC_C 0x14B1
|
||||
#define IGP02E1000_PHY_AGC_D 0x18B1
|
||||
#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
|
||||
#define IGP02E1000_AGC_LENGTH_MASK 0x7F
|
||||
#define IGP02E1000_AGC_RANGE 15
|
||||
|
||||
#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
|
||||
|
||||
#endif
|
||||
270
drivers/net/igb/e1000_regs.h
Normal file
270
drivers/net/igb/e1000_regs.h
Normal file
@@ -0,0 +1,270 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _E1000_REGS_H_
|
||||
#define _E1000_REGS_H_
|
||||
|
||||
#define E1000_CTRL 0x00000 /* Device Control - RW */
|
||||
#define E1000_STATUS 0x00008 /* Device Status - RO */
|
||||
#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
|
||||
#define E1000_EERD 0x00014 /* EEPROM Read - RW */
|
||||
#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
|
||||
#define E1000_MDIC 0x00020 /* MDI Control - RW */
|
||||
#define E1000_SCTL 0x00024 /* SerDes Control - RW */
|
||||
#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
|
||||
#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
|
||||
#define E1000_FCT 0x00030 /* Flow Control Type - RW */
|
||||
#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
|
||||
#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
|
||||
#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
|
||||
#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
|
||||
#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
|
||||
#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
|
||||
#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
|
||||
#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
|
||||
#define E1000_RCTL 0x00100 /* RX Control - RW */
|
||||
#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
|
||||
#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
|
||||
#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
|
||||
#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
|
||||
#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
|
||||
#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
|
||||
#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
|
||||
#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
|
||||
#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
|
||||
#define E1000_TCTL 0x00400 /* TX Control - RW */
|
||||
#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
|
||||
#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
|
||||
#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
|
||||
#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
|
||||
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
|
||||
#define E1000_PBS 0x01008 /* Packet Buffer Size */
|
||||
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
|
||||
#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
|
||||
#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
|
||||
#define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
|
||||
#define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */
|
||||
#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
|
||||
#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
|
||||
#define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n)))
|
||||
#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
|
||||
/* Split and Replication RX Control - RW */
|
||||
/*
|
||||
* Convenience macros
|
||||
*
|
||||
* Note: "_n" is the queue number of the register to be written to.
|
||||
*
|
||||
* Example usage:
|
||||
* E1000_RDBAL_REG(current_rx_queue)
|
||||
*/
|
||||
#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) \
|
||||
: (0x0C000 + ((_n) * 0x40)))
|
||||
#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) \
|
||||
: (0x0C004 + ((_n) * 0x40)))
|
||||
#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) \
|
||||
: (0x0C008 + ((_n) * 0x40)))
|
||||
#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) \
|
||||
: (0x0C00C + ((_n) * 0x40)))
|
||||
#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) \
|
||||
: (0x0C010 + ((_n) * 0x40)))
|
||||
#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) \
|
||||
: (0x0C018 + ((_n) * 0x40)))
|
||||
#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) \
|
||||
: (0x0C028 + ((_n) * 0x40)))
|
||||
#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) \
|
||||
: (0x0E000 + ((_n) * 0x40)))
|
||||
#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) \
|
||||
: (0x0E004 + ((_n) * 0x40)))
|
||||
#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) \
|
||||
: (0x0E008 + ((_n) * 0x40)))
|
||||
#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) \
|
||||
: (0x0E010 + ((_n) * 0x40)))
|
||||
#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) \
|
||||
: (0x0E018 + ((_n) * 0x40)))
|
||||
#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \
|
||||
: (0x0E028 + ((_n) * 0x40)))
|
||||
#define E1000_TARC(_n) (0x03840 + (_n << 8))
|
||||
#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
|
||||
#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
|
||||
#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \
|
||||
: (0x0E038 + ((_n) * 0x40)))
|
||||
#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) \
|
||||
: (0x0E03C + ((_n) * 0x40)))
|
||||
#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
|
||||
#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
|
||||
#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
|
||||
#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
|
||||
#define E1000_DTXCTL 0x03590 /* DMA TX Control - RW */
|
||||
#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
|
||||
#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
|
||||
#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
|
||||
#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
|
||||
#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
|
||||
#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
|
||||
#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
|
||||
#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
|
||||
#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
|
||||
#define E1000_COLC 0x04028 /* Collision Count - R/clr */
|
||||
#define E1000_DC 0x04030 /* Defer Count - R/clr */
|
||||
#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
|
||||
#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
|
||||
#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
|
||||
#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
|
||||
#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
|
||||
#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
|
||||
#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
|
||||
#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
|
||||
#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
|
||||
#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
|
||||
#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
|
||||
#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
|
||||
#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
|
||||
#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
|
||||
#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
|
||||
#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
|
||||
#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
|
||||
#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
|
||||
#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
|
||||
#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
|
||||
#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
|
||||
#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
|
||||
#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
|
||||
#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
|
||||
#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
|
||||
#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
|
||||
#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
|
||||
#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
|
||||
#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
|
||||
#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
|
||||
#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
|
||||
#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
|
||||
#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
|
||||
#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
|
||||
#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
|
||||
#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
|
||||
#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
|
||||
#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
|
||||
#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
|
||||
#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
|
||||
#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
|
||||
#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
|
||||
#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
|
||||
#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
|
||||
#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
|
||||
#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
|
||||
#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
|
||||
#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
|
||||
/* Interrupt Cause Rx Packet Timer Expire Count */
|
||||
#define E1000_ICRXPTC 0x04104
|
||||
/* Interrupt Cause Rx Absolute Timer Expire Count */
|
||||
#define E1000_ICRXATC 0x04108
|
||||
/* Interrupt Cause Tx Packet Timer Expire Count */
|
||||
#define E1000_ICTXPTC 0x0410C
|
||||
/* Interrupt Cause Tx Absolute Timer Expire Count */
|
||||
#define E1000_ICTXATC 0x04110
|
||||
/* Interrupt Cause Tx Queue Empty Count */
|
||||
#define E1000_ICTXQEC 0x04118
|
||||
/* Interrupt Cause Tx Queue Minimum Threshold Count */
|
||||
#define E1000_ICTXQMTC 0x0411C
|
||||
/* Interrupt Cause Rx Descriptor Minimum Threshold Count */
|
||||
#define E1000_ICRXDMTC 0x04120
|
||||
#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
|
||||
#define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */
|
||||
#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
|
||||
#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
|
||||
#define E1000_CBTMPC 0x0402C /* Circuit Breaker TX Packet Count */
|
||||
#define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */
|
||||
#define E1000_CBRMPC 0x040FC /* Circuit Breaker RX Packet Count */
|
||||
#define E1000_RPTHC 0x04104 /* Rx Packets To Host */
|
||||
#define E1000_HGPTC 0x04118 /* Host Good Packets TX Count */
|
||||
#define E1000_HTCBDPC 0x04124 /* Host TX Circuit Breaker Dropped Count */
|
||||
#define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */
|
||||
#define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */
|
||||
#define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */
|
||||
#define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */
|
||||
#define E1000_LENERRS 0x04138 /* Length Errors Count */
|
||||
#define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */
|
||||
#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
|
||||
#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
|
||||
#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
|
||||
#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */
|
||||
#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
|
||||
#define E1000_RLPML 0x05004 /* RX Long Packet Max Length */
|
||||
#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
|
||||
#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
|
||||
#define E1000_RA 0x05400 /* Receive Address - RW Array */
|
||||
#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
|
||||
#define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */
|
||||
#define E1000_WUC 0x05800 /* Wakeup Control - RW */
|
||||
#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
|
||||
#define E1000_WUS 0x05810 /* Wakeup Status - RO */
|
||||
#define E1000_MANC 0x05820 /* Management Control - RW */
|
||||
#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
|
||||
#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
|
||||
#define E1000_HOST_IF 0x08800 /* Host Interface */
|
||||
|
||||
#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
|
||||
#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
|
||||
#define E1000_CCMCTL 0x05B48 /* CCM Control Register */
|
||||
#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
|
||||
#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */
|
||||
#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
|
||||
#define E1000_SWSM 0x05B50 /* SW Semaphore */
|
||||
#define E1000_FWSM 0x05B54 /* FW Semaphore */
|
||||
#define E1000_HICR 0x08F00 /* Host Inteface Control */
|
||||
|
||||
/* RSS registers */
|
||||
#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
|
||||
#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */
|
||||
#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/
|
||||
#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */
|
||||
/* MSI-X Allocation Register (_i) - RW */
|
||||
#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4))
|
||||
/* MSI-X Table entry addr low reg 0 - RW */
|
||||
#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10))
|
||||
/* MSI-X Table entry addr upper reg 0 - RW */
|
||||
#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10))
|
||||
/* MSI-X Table entry message reg 0 - RW */
|
||||
#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10))
|
||||
/* MSI-X Table entry vector ctrl reg 0 - RW */
|
||||
#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10))
|
||||
/* Redirection Table - RW Array */
|
||||
#define E1000_RETA(_i) (0x05C00 + ((_i) * 4))
|
||||
#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
|
||||
|
||||
#define E1000_REGISTER(a, reg) reg
|
||||
|
||||
#define wr32(reg, value) (writel(value, hw->hw_addr + reg))
|
||||
#define rd32(reg) (readl(hw->hw_addr + reg))
|
||||
#define wrfl() ((void)rd32(E1000_STATUS))
|
||||
|
||||
#define array_wr32(reg, offset, value) \
|
||||
(writel(value, hw->hw_addr + reg + ((offset) << 2)))
|
||||
#define array_rd32(reg, offset) \
|
||||
(readl(hw->hw_addr + reg + ((offset) << 2)))
|
||||
|
||||
#endif
|
||||
300
drivers/net/igb/igb.h
Normal file
300
drivers/net/igb/igb.h
Normal file
@@ -0,0 +1,300 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* Linux PRO/1000 Ethernet Driver main header file */
|
||||
|
||||
#ifndef _IGB_H_
|
||||
#define _IGB_H_
|
||||
|
||||
#include "e1000_mac.h"
|
||||
#include "e1000_82575.h"
|
||||
|
||||
struct igb_adapter;
|
||||
|
||||
/* Interrupt defines */
|
||||
#define IGB_MAX_TX_CLEAN 72
|
||||
|
||||
#define IGB_MIN_DYN_ITR 3000
|
||||
#define IGB_MAX_DYN_ITR 96000
|
||||
#define IGB_START_ITR 6000
|
||||
|
||||
#define IGB_DYN_ITR_PACKET_THRESHOLD 2
|
||||
#define IGB_DYN_ITR_LENGTH_LOW 200
|
||||
#define IGB_DYN_ITR_LENGTH_HIGH 1000
|
||||
|
||||
/* TX/RX descriptor defines */
|
||||
#define IGB_DEFAULT_TXD 256
|
||||
#define IGB_MIN_TXD 80
|
||||
#define IGB_MAX_TXD 4096
|
||||
|
||||
#define IGB_DEFAULT_RXD 256
|
||||
#define IGB_MIN_RXD 80
|
||||
#define IGB_MAX_RXD 4096
|
||||
|
||||
#define IGB_DEFAULT_ITR 3 /* dynamic */
|
||||
#define IGB_MAX_ITR_USECS 10000
|
||||
#define IGB_MIN_ITR_USECS 10
|
||||
|
||||
/* Transmit and receive queues */
|
||||
#define IGB_MAX_RX_QUEUES 4
|
||||
|
||||
/* RX descriptor control thresholds.
|
||||
* PTHRESH - MAC will consider prefetch if it has fewer than this number of
|
||||
* descriptors available in its onboard memory.
|
||||
* Setting this to 0 disables RX descriptor prefetch.
|
||||
* HTHRESH - MAC will only prefetch if there are at least this many descriptors
|
||||
* available in host memory.
|
||||
* If PTHRESH is 0, this should also be 0.
|
||||
* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
|
||||
* descriptors until either it has this many to write back, or the
|
||||
* ITR timer expires.
|
||||
*/
|
||||
#define IGB_RX_PTHRESH 16
|
||||
#define IGB_RX_HTHRESH 8
|
||||
#define IGB_RX_WTHRESH 1
|
||||
|
||||
/* this is the size past which hardware will drop packets when setting LPE=0 */
|
||||
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
|
||||
|
||||
/* Supported Rx Buffer Sizes */
|
||||
#define IGB_RXBUFFER_128 128 /* Used for packet split */
|
||||
#define IGB_RXBUFFER_256 256 /* Used for packet split */
|
||||
#define IGB_RXBUFFER_512 512
|
||||
#define IGB_RXBUFFER_1024 1024
|
||||
#define IGB_RXBUFFER_2048 2048
|
||||
#define IGB_RXBUFFER_4096 4096
|
||||
#define IGB_RXBUFFER_8192 8192
|
||||
#define IGB_RXBUFFER_16384 16384
|
||||
|
||||
/* Packet Buffer allocations */
|
||||
|
||||
|
||||
/* How many Tx Descriptors do we need to call netif_wake_queue ? */
|
||||
#define IGB_TX_QUEUE_WAKE 16
|
||||
/* How many Rx Buffers do we bundle into one write to the hardware ? */
|
||||
#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
|
||||
|
||||
#define AUTO_ALL_MODES 0
|
||||
#define IGB_EEPROM_APME 0x0400
|
||||
|
||||
#ifndef IGB_MASTER_SLAVE
|
||||
/* Switch to override PHY master/slave setting */
|
||||
#define IGB_MASTER_SLAVE e1000_ms_hw_default
|
||||
#endif
|
||||
|
||||
#define IGB_MNG_VLAN_NONE -1
|
||||
|
||||
/* wrapper around a pointer to a socket buffer,
|
||||
* so a DMA handle can be stored along with the buffer */
|
||||
struct igb_buffer {
|
||||
struct sk_buff *skb;
|
||||
dma_addr_t dma;
|
||||
union {
|
||||
/* TX */
|
||||
struct {
|
||||
unsigned long time_stamp;
|
||||
u32 length;
|
||||
};
|
||||
/* RX */
|
||||
struct {
|
||||
struct page *page;
|
||||
u64 page_dma;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
struct igb_queue_stats {
|
||||
u64 packets;
|
||||
u64 bytes;
|
||||
};
|
||||
|
||||
struct igb_ring {
|
||||
struct igb_adapter *adapter; /* backlink */
|
||||
void *desc; /* descriptor ring memory */
|
||||
dma_addr_t dma; /* phys address of the ring */
|
||||
unsigned int size; /* length of desc. ring in bytes */
|
||||
unsigned int count; /* number of desc. in the ring */
|
||||
u16 next_to_use;
|
||||
u16 next_to_clean;
|
||||
u16 head;
|
||||
u16 tail;
|
||||
struct igb_buffer *buffer_info; /* array of buffer info structs */
|
||||
|
||||
u32 eims_value;
|
||||
u32 itr_val;
|
||||
u16 itr_register;
|
||||
u16 cpu;
|
||||
|
||||
unsigned int total_bytes;
|
||||
unsigned int total_packets;
|
||||
|
||||
union {
|
||||
/* TX */
|
||||
struct {
|
||||
spinlock_t tx_clean_lock;
|
||||
spinlock_t tx_lock;
|
||||
bool detect_tx_hung;
|
||||
};
|
||||
/* RX */
|
||||
struct {
|
||||
/* arrays of page information for packet split */
|
||||
struct sk_buff *pending_skb;
|
||||
int pending_skb_page;
|
||||
int no_itr_adjust;
|
||||
struct igb_queue_stats rx_stats;
|
||||
struct napi_struct napi;
|
||||
};
|
||||
};
|
||||
|
||||
char name[IFNAMSIZ + 5];
|
||||
};
|
||||
|
||||
#define IGB_DESC_UNUSED(R) \
|
||||
((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
|
||||
(R)->next_to_clean - (R)->next_to_use - 1)
|
||||
|
||||
#define E1000_RX_DESC_ADV(R, i) \
|
||||
(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
|
||||
#define E1000_TX_DESC_ADV(R, i) \
|
||||
(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
|
||||
#define E1000_TX_CTXTDESC_ADV(R, i) \
|
||||
(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
|
||||
#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
|
||||
#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
|
||||
#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
|
||||
|
||||
/* board specific private data structure */
|
||||
|
||||
struct igb_adapter {
|
||||
struct timer_list watchdog_timer;
|
||||
struct timer_list phy_info_timer;
|
||||
struct vlan_group *vlgrp;
|
||||
u16 mng_vlan_id;
|
||||
u32 bd_number;
|
||||
u32 rx_buffer_len;
|
||||
u32 wol;
|
||||
u32 en_mng_pt;
|
||||
u16 link_speed;
|
||||
u16 link_duplex;
|
||||
unsigned int total_tx_bytes;
|
||||
unsigned int total_tx_packets;
|
||||
unsigned int total_rx_bytes;
|
||||
unsigned int total_rx_packets;
|
||||
/* Interrupt Throttle Rate */
|
||||
u32 itr;
|
||||
u32 itr_setting;
|
||||
u16 tx_itr;
|
||||
u16 rx_itr;
|
||||
int set_itr;
|
||||
|
||||
struct work_struct reset_task;
|
||||
struct work_struct watchdog_task;
|
||||
bool fc_autoneg;
|
||||
u8 tx_timeout_factor;
|
||||
struct timer_list blink_timer;
|
||||
unsigned long led_status;
|
||||
|
||||
/* TX */
|
||||
struct igb_ring *tx_ring; /* One per active queue */
|
||||
unsigned int restart_queue;
|
||||
unsigned long tx_queue_len;
|
||||
u32 txd_cmd;
|
||||
u32 gotc;
|
||||
u64 gotc_old;
|
||||
u64 tpt_old;
|
||||
u64 colc_old;
|
||||
u32 tx_timeout_count;
|
||||
|
||||
/* RX */
|
||||
struct igb_ring *rx_ring; /* One per active queue */
|
||||
int num_tx_queues;
|
||||
int num_rx_queues;
|
||||
|
||||
u64 hw_csum_err;
|
||||
u64 hw_csum_good;
|
||||
u64 rx_hdr_split;
|
||||
u32 alloc_rx_buff_failed;
|
||||
bool rx_csum;
|
||||
u32 gorc;
|
||||
u64 gorc_old;
|
||||
u16 rx_ps_hdr_size;
|
||||
u32 max_frame_size;
|
||||
u32 min_frame_size;
|
||||
|
||||
/* OS defined structs */
|
||||
struct net_device *netdev;
|
||||
struct napi_struct napi;
|
||||
struct pci_dev *pdev;
|
||||
struct net_device_stats net_stats;
|
||||
|
||||
/* structs defined in e1000_hw.h */
|
||||
struct e1000_hw hw;
|
||||
struct e1000_hw_stats stats;
|
||||
struct e1000_phy_info phy_info;
|
||||
struct e1000_phy_stats phy_stats;
|
||||
|
||||
u32 test_icr;
|
||||
struct igb_ring test_tx_ring;
|
||||
struct igb_ring test_rx_ring;
|
||||
|
||||
int msg_enable;
|
||||
struct msix_entry *msix_entries;
|
||||
u32 eims_enable_mask;
|
||||
|
||||
/* to not mess up cache alignment, always add to the bottom */
|
||||
unsigned long state;
|
||||
unsigned int msi_enabled;
|
||||
|
||||
u32 eeprom_wol;
|
||||
};
|
||||
|
||||
enum e1000_state_t {
|
||||
__IGB_TESTING,
|
||||
__IGB_RESETTING,
|
||||
__IGB_DOWN
|
||||
};
|
||||
|
||||
enum igb_boards {
|
||||
board_82575,
|
||||
};
|
||||
|
||||
extern char igb_driver_name[];
|
||||
extern char igb_driver_version[];
|
||||
|
||||
extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
|
||||
extern int igb_up(struct igb_adapter *);
|
||||
extern void igb_down(struct igb_adapter *);
|
||||
extern void igb_reinit_locked(struct igb_adapter *);
|
||||
extern void igb_reset(struct igb_adapter *);
|
||||
extern int igb_set_spd_dplx(struct igb_adapter *, u16);
|
||||
extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
|
||||
extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
|
||||
extern void igb_update_stats(struct igb_adapter *);
|
||||
extern void igb_set_ethtool_ops(struct net_device *);
|
||||
|
||||
#endif /* _IGB_H_ */
|
||||
1927
drivers/net/igb/igb_ethtool.c
Normal file
1927
drivers/net/igb/igb_ethtool.c
Normal file
File diff suppressed because it is too large
Load Diff
4138
drivers/net/igb/igb_main.c
Normal file
4138
drivers/net/igb/igb_main.c
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user