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Merge tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
"Not a major amount of change, the i915 trees got split into display
and gt trees to better facilitate higher level review, and there's a
major refactoring of i915 GEM locking to use more core kernel concepts
(like ww-mutexes). msm gets per-process pagetables, older AMD SI cards
get DC support, nouveau got a bump in displayport support with common
code extraction from i915.
Outside of drm this contains a couple of patches for hexint
moduleparams which you've acked, and a virtio common code tree that
you should also get via it's regular path.
New driver:
- Cadence MHDP8546 DisplayPort bridge driver
core:
- cross-driver scatterlist cleanups
- devm_drm conversions
- remove drm_dev_init
- devm_drm_dev_alloc conversion
ttm:
- lots of refactoring and cleanups
bridges:
- chained bridge support in more drivers
panel:
- misc new panels
scheduler:
- cleanup priority levels
displayport:
- refactor i915 code into helpers for nouveau
i915:
- split into display and GT trees
- WW locking refactoring in GEM
- execbuf2 extension mechanism
- syncobj timeline support
- GEN 12 HOBL display powersaving
- Rocket Lake display additions
- Disable FBC on Tigerlake
- Tigerlake Type-C + DP improvements
- Hotplug interrupt refactoring
amdgpu:
- Sienna Cichlid updates
- Navy Flounder updates
- DCE6 (SI) support for DC
- Plane rotation enabled
- TMZ state info ioctl
- PCIe DPC recovery support
- DC interrupt handling refactor
- OLED panel fixes
amdkfd:
- add SMI events for thermal throttling
- SMI interface events ioctl update
- process eviction counters
radeon:
- move to dma_ for allocations
- expose sclk via sysfs
msm:
- DSI support for sm8150/sm8250
- per-process GPU pagetable support
- Displayport support
mediatek:
- move HDMI phy driver to PHY
- convert mtk-dpi to bridge API
- disable mt2701 tmds
tegra:
- bridge support
exynos:
- misc cleanups
vc4:
- dual display cleanups
ast:
- cleanups
gma500:
- conversion to GPIOd API
hisilicon:
- misc reworks
ingenic:
- clock handling and format improvements
mcde:
- DSI support
mgag200:
- desktop g200 support
mxsfb:
- i.MX7 + i.MX8M
- alpha plane support
panfrost:
- devfreq support
- amlogic SoC support
ps8640:
- EDID from eDP retrieval
tidss:
- AM65xx YUV workaround
virtio:
- virtio-gpu exported resources
rcar-du:
- R8A7742, R8A774E1 and R8A77961 support
- YUV planar format fixes
- non-visible plane handling
- VSP device reference count fix
- Kconfig fix to avoid displaying disabled options in .config"
* tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm: (1494 commits)
drm/ingenic: Fix bad revert
drm/amdgpu: Fix invalid number of character '{' in amdgpu_acpi_init
drm/amdgpu: Remove warning for virtual_display
drm/amdgpu: kfd_initialized can be static
drm/amd/pm: setup APU dpm clock table in SMU HW initialization
drm/amdgpu: prevent spurious warning
drm/amdgpu/swsmu: fix ARC build errors
drm/amd/display: Fix OPTC_DATA_FORMAT programming
drm/amd/display: Don't allow pstate if no support in blank
drm/panfrost: increase readl_relaxed_poll_timeout values
MAINTAINERS: Update entry for st7703 driver after the rename
Revert "gpu/drm: ingenic: Add option to mmap GEM buffers cached"
drm/amd/display: HDMI remote sink need mode validation for Linux
drm/amd/display: Change to correct unit on audio rate
drm/amd/display: Avoid set zero in the requested clk
drm/amdgpu: align frag_end to covered address space
drm/amdgpu: fix NULL pointer dereference for Renoir
drm/vmwgfx: fix regression in thp code due to ttm init refactor.
drm/amdgpu/swsmu: add interrupt work handler for smu11 parts
drm/amdgpu/swsmu: add interrupt work function
...
This commit is contained in:
Linus Torvalds
117
Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
Normal file
117
Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
Normal file
@@ -0,0 +1,117 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM2711 HDMI Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Eric Anholt <eric@anholt.net>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,bcm2711-hdmi0
|
||||
- brcm,bcm2711-hdmi1
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||||
|
||||
reg:
|
||||
items:
|
||||
- description: HDMI controller register range
|
||||
- description: DVP register range
|
||||
- description: HDMI PHY register range
|
||||
- description: Rate Manager register range
|
||||
- description: Packet RAM register range
|
||||
- description: Metadata RAM register range
|
||||
- description: CSC register range
|
||||
- description: CEC register range
|
||||
- description: HD register range
|
||||
|
||||
reg-names:
|
||||
items:
|
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- const: hdmi
|
||||
- const: dvp
|
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- const: phy
|
||||
- const: rm
|
||||
- const: packet
|
||||
- const: metadata
|
||||
- const: csc
|
||||
- const: cec
|
||||
- const: hd
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: The HDMI state machine clock
|
||||
- description: The Pixel BVB clock
|
||||
- description: The HDMI Audio parent clock
|
||||
- description: The HDMI CEC parent clock
|
||||
|
||||
clock-names:
|
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items:
|
||||
- const: hdmi
|
||||
- const: bvb
|
||||
- const: audio
|
||||
- const: cec
|
||||
|
||||
ddc:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: >
|
||||
Phandle of the I2C controller used for DDC EDID probing
|
||||
|
||||
hpd-gpios:
|
||||
description: >
|
||||
The GPIO pin for the HDMI hotplug detect (if it doesn't appear
|
||||
as an interrupt/status bit in the HDMI controller itself)
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
description: >
|
||||
Should contain one entry pointing to the DMA channel used to
|
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transfer audio data.
|
||||
|
||||
dma-names:
|
||||
const: audio-rx
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- resets
|
||||
- ddc
|
||||
|
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additionalProperties: false
|
||||
|
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examples:
|
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- |
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hdmi0: hdmi@7ef00700 {
|
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compatible = "brcm,bcm2711-hdmi0";
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reg = <0x7ef00700 0x300>,
|
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<0x7ef00300 0x200>,
|
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<0x7ef00f00 0x80>,
|
||||
<0x7ef00f80 0x80>,
|
||||
<0x7ef01b00 0x200>,
|
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<0x7ef01f00 0x400>,
|
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<0x7ef00200 0x80>,
|
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<0x7ef04300 0x100>,
|
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<0x7ef20000 0x100>;
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reg-names = "hdmi",
|
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"dvp",
|
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"phy",
|
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"rm",
|
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"packet",
|
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"metadata",
|
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"csc",
|
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"cec",
|
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"hd";
|
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clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
|
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clock-names = "hdmi", "bvb", "audio", "cec";
|
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resets = <&dvp 0>;
|
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ddc = <&ddc0>;
|
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};
|
||||
|
||||
...
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@@ -11,7 +11,9 @@ maintainers:
|
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|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,bcm2835-hvs
|
||||
enum:
|
||||
- brcm,bcm2711-hvs
|
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- brcm,bcm2835-hvs
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -19,6 +21,10 @@ properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: Core Clock
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@@ -26,6 +32,16 @@ required:
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,bcm2711-hvs"
|
||||
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
hvs@7e400000 {
|
||||
|
||||
@@ -15,6 +15,11 @@ properties:
|
||||
- brcm,bcm2835-pixelvalve0
|
||||
- brcm,bcm2835-pixelvalve1
|
||||
- brcm,bcm2835-pixelvalve2
|
||||
- brcm,bcm2711-pixelvalve0
|
||||
- brcm,bcm2711-pixelvalve1
|
||||
- brcm,bcm2711-pixelvalve2
|
||||
- brcm,bcm2711-pixelvalve3
|
||||
- brcm,bcm2711-pixelvalve4
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -17,6 +17,7 @@ description: >
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,bcm2711-vc5
|
||||
- brcm,bcm2835-vc4
|
||||
- brcm,cygnus-vc4
|
||||
|
||||
|
||||
@@ -0,0 +1,169 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Cadence MHDP8546 bridge
|
||||
|
||||
maintainers:
|
||||
- Swapnil Jakhade <sjakhade@cadence.com>
|
||||
- Yuti Amonkar <yamonkar@cadence.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- cdns,mhdp8546
|
||||
- ti,j721e-mhdp8546
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- description:
|
||||
Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
|
||||
The AUX and PMA registers are not part of this range, they are instead
|
||||
included in the associated PHY.
|
||||
- description:
|
||||
Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: mhdptx
|
||||
- const: j721e-intg
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description:
|
||||
DP bridge clock, used by the IP to know how to translate a number of
|
||||
clock cycles into a time (which is used to comply with DP standard timings
|
||||
and delays).
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
description:
|
||||
phandle to the DisplayPort PHY.
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: dpphy
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
type: object
|
||||
description:
|
||||
Ports as described in Documentation/devicetree/bindings/graph.txt.
|
||||
|
||||
properties:
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
port@0:
|
||||
type: object
|
||||
description:
|
||||
First input port representing the DP bridge input.
|
||||
|
||||
port@1:
|
||||
type: object
|
||||
description:
|
||||
Second input port representing the DP bridge input.
|
||||
|
||||
port@2:
|
||||
type: object
|
||||
description:
|
||||
Third input port representing the DP bridge input.
|
||||
|
||||
port@3:
|
||||
type: object
|
||||
description:
|
||||
Fourth input port representing the DP bridge input.
|
||||
|
||||
port@4:
|
||||
type: object
|
||||
description:
|
||||
Output port representing the DP bridge output.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@4
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,j721e-mhdp8546
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
reg-names:
|
||||
minItems: 2
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
reg-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- reg
|
||||
- reg-names
|
||||
- phys
|
||||
- phy-names
|
||||
- interrupts
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
mhdp: dp-bridge@f0fb000000 {
|
||||
compatible = "cdns,mhdp8546";
|
||||
reg = <0xf0 0xfb000000 0x0 0x1000000>;
|
||||
reg-names = "mhdptx";
|
||||
clocks = <&mhdp_clock>;
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dpphy";
|
||||
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dp_bridge_input: endpoint {
|
||||
remote-endpoint = <&xxx_dpi_output>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
dp_bridge_output: endpoint {
|
||||
remote-endpoint = <&xxx_dp_connector_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,176 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/lontium,lt9611.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Lontium LT9611 2 Port MIPI to HDMI Bridge
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description: |
|
||||
The LT9611 is a bridge device which converts DSI to HDMI
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- lontium,lt9611
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#sound-dai-cells":
|
||||
const: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO connected to active high RESET pin.
|
||||
|
||||
vdd-supply:
|
||||
description: Regulator for 1.8V MIPI phy power.
|
||||
|
||||
vcc-supply:
|
||||
description: Regulator for 3.3V IO power.
|
||||
|
||||
ports:
|
||||
type: object
|
||||
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
port@0:
|
||||
type: object
|
||||
description: |
|
||||
Primary MIPI port-1 for MIPI input
|
||||
|
||||
properties:
|
||||
reg:
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^endpoint(@[0-9])$":
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
remote-endpoint:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
port@1:
|
||||
type: object
|
||||
description: |
|
||||
Additional MIPI port-2 for MIPI input, used in combination
|
||||
with primary MIPI port-1 to drive higher resolution displays
|
||||
|
||||
properties:
|
||||
reg:
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^endpoint(@[0-9])$":
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
remote-endpoint:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
port@2:
|
||||
type: object
|
||||
description: |
|
||||
HDMI port for HDMI output
|
||||
|
||||
properties:
|
||||
reg:
|
||||
const: 2
|
||||
|
||||
patternProperties:
|
||||
"^endpoint(@[0-9])$":
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
remote-endpoint:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
required:
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- port@0
|
||||
- port@2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- vdd-supply
|
||||
- vcc-supply
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c10 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hdmi-bridge@3b {
|
||||
compatible = "lontium,lt9611";
|
||||
reg = <0x3b>;
|
||||
|
||||
reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
|
||||
interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
vdd-supply = <<9611_1v8>;
|
||||
vcc-supply = <<9611_3v3>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
lt9611_a: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lt9611_b: endpoint {
|
||||
remote-endpoint = <&dsi1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
lt9611_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -79,6 +79,9 @@ properties:
|
||||
The GPIO used to control the power down line of this device.
|
||||
maxItems: 1
|
||||
|
||||
power-supply:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- ports
|
||||
|
||||
@@ -14,8 +14,10 @@ Required properties:
|
||||
- compatible : Shall contain one or more of
|
||||
- "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
|
||||
- "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
|
||||
- "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
|
||||
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
|
||||
- "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
|
||||
- "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
|
||||
- "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
|
||||
- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
|
||||
HDMI TX
|
||||
@@ -42,7 +44,7 @@ Optional properties:
|
||||
Example:
|
||||
|
||||
hdmi0: hdmi@fead0000 {
|
||||
compatible = "renesas,r8a7795-dw-hdmi";
|
||||
compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
|
||||
reg = <0 0xfead0000 0 0x10000>;
|
||||
interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
|
||||
|
||||
@@ -16,11 +16,13 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
|
||||
- renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
|
||||
- renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
|
||||
- renesas,r8a774a1-lvds # for RZ/G2M compatible LVDS encoders
|
||||
- renesas,r8a774b1-lvds # for RZ/G2N compatible LVDS encoders
|
||||
- renesas,r8a774c0-lvds # for RZ/G2E compatible LVDS encoders
|
||||
- renesas,r8a774e1-lvds # for RZ/G2H compatible LVDS encoders
|
||||
- renesas,r8a7790-lvds # for R-Car H2 compatible LVDS encoders
|
||||
- renesas,r8a7791-lvds # for R-Car M2-W compatible LVDS encoders
|
||||
- renesas,r8a7793-lvds # for R-Car M2-N compatible LVDS encoders
|
||||
|
||||
@@ -0,0 +1,127 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358762.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Toshiba TC358762 MIPI DSI to MIPI DPI bridge
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
|
||||
description: |
|
||||
The TC358762 is bridge device which converts MIPI DSI to MIPI DPI.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- toshiba,tc358762
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: virtual channel number of a DSI peripheral
|
||||
|
||||
vddc-supply:
|
||||
description: Regulator for 1.2V internal core power.
|
||||
|
||||
ports:
|
||||
type: object
|
||||
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
port@0:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
description: |
|
||||
Video port for MIPI DSI input
|
||||
|
||||
properties:
|
||||
reg:
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
endpoint:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
remote-endpoint: true
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
port@1:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
description: |
|
||||
Video port for MIPI DPI output (panel or connector).
|
||||
|
||||
properties:
|
||||
reg:
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
endpoint:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
remote-endpoint: true
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
required:
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- vddc-supply
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
bridge@0 {
|
||||
reg = <0>;
|
||||
compatible = "toshiba,tc358762";
|
||||
vddc-supply = <&vcc_1v2_reg>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
bridge_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
bridge_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -0,0 +1,215 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358775.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Toshiba TC358775 DSI to LVDS bridge bindings
|
||||
|
||||
maintainers:
|
||||
- Vinay Simha BN <simhavcs@gmail.com>
|
||||
|
||||
description: |
|
||||
This binding supports DSI to LVDS bridge TC358775
|
||||
|
||||
MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
|
||||
Video frame size:
|
||||
Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
|
||||
limited by 135 MHz LVDS speed
|
||||
Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
|
||||
panel, limited by 270 MHz LVDS speed.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: toshiba,tc358775
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: i2c address of the bridge, 0x0f
|
||||
|
||||
vdd-supply:
|
||||
maxItems: 1
|
||||
description: 1.2V LVDS Power Supply
|
||||
|
||||
vddio-supply:
|
||||
maxItems: 1
|
||||
description: 1.8V IO Power Supply
|
||||
|
||||
stby-gpios:
|
||||
maxItems: 1
|
||||
description: Standby pin, Low active
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: Hardware reset, Low active
|
||||
|
||||
ports:
|
||||
type: object
|
||||
description:
|
||||
A node containing input and output port nodes with endpoint definitions
|
||||
as documented in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
port@0:
|
||||
type: object
|
||||
description: |
|
||||
DSI Input. The remote endpoint phandle should be a
|
||||
reference to a valid mipi_dsi_host device node.
|
||||
|
||||
port@1:
|
||||
type: object
|
||||
description: |
|
||||
Video port for LVDS output (panel or connector).
|
||||
|
||||
port@2:
|
||||
type: object
|
||||
description: |
|
||||
Video port for Dual link LVDS output (panel or connector).
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- vdd-supply
|
||||
- vddio-supply
|
||||
- stby-gpios
|
||||
- reset-gpios
|
||||
- ports
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/* For single-link LVDS display panel */
|
||||
|
||||
i2c@78b8000 {
|
||||
/* On High speed expansion */
|
||||
label = "HS-I2C2";
|
||||
reg = <0x078b8000 0x500>;
|
||||
clock-frequency = <400000>; /* fastmode operation */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tc_bridge: bridge@f {
|
||||
compatible = "toshiba,tc358775";
|
||||
reg = <0x0f>;
|
||||
|
||||
vdd-supply = <&pm8916_l2>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
|
||||
stby-gpios = <&msmgpio 99 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&msmgpio 72 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
d2l_in_test: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@1a98000 {
|
||||
reg = <0x1a98000 0x25c>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&d2l_in_test>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
/* For dual-link LVDS display panel */
|
||||
|
||||
i2c@78b8000 {
|
||||
/* On High speed expansion */
|
||||
label = "HS-I2C2";
|
||||
reg = <0x078b8000 0x500>;
|
||||
clock-frequency = <400000>; /* fastmode operation */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tc_bridge_dual: bridge@f {
|
||||
compatible = "toshiba,tc358775";
|
||||
reg = <0x0f>;
|
||||
|
||||
vdd-supply = <&pm8916_l2>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
|
||||
stby-gpios = <&msmgpio 99 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&msmgpio 72 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
d2l_in_dual: endpoint {
|
||||
remote-endpoint = <&dsi0_out_dual>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
lvds1_out: endpoint {
|
||||
remote-endpoint = <&panel_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@1a98000 {
|
||||
reg = <0x1a98000 0x25c>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out_dual: endpoint {
|
||||
remote-endpoint = <&d2l_in_dual>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,108 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright 2019 NXP
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: iMX8MQ Display Controller Subsystem (DCSS)
|
||||
|
||||
maintainers:
|
||||
- Laurentiu Palcu <laurentiu.palcu@nxp.com>
|
||||
|
||||
description:
|
||||
|
||||
The DCSS (display controller sub system) is used to source up to three
|
||||
display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
|
||||
2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
|
||||
image processing capabilities are included to provide a solution capable of
|
||||
driving next generation high dynamic range displays.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nxp,imx8mq-dcss
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: DCSS base address and size, up to IRQ steer start
|
||||
- description: DCSS BLKCTL base address and size
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: Context loader completion and error interrupt
|
||||
- description: DTG interrupt used to signal context loader trigger time
|
||||
- description: DTG interrupt for Vblank
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: ctxld
|
||||
- const: ctxld_kick
|
||||
- const: vblank
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display APB clock for all peripheral PIO access interfaces
|
||||
- description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
|
||||
- description: RTRAM clock
|
||||
- description: Pixel clock, can be driven either by HDMI phy clock or MIPI
|
||||
- description: DTRC clock, needed by video decompressor
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb
|
||||
- const: axi
|
||||
- const: rtrm
|
||||
- const: pix
|
||||
- const: dtrc
|
||||
|
||||
assigned-clocks:
|
||||
items:
|
||||
- description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
|
||||
- description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
|
||||
- description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or
|
||||
IMX8MQ_VIDEO_PLL1_REF_SEL
|
||||
|
||||
assigned-clock-parents:
|
||||
items:
|
||||
- description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
|
||||
- description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
|
||||
- description: Phandle and clock specifier of IMX8MQ_CLK_27M
|
||||
|
||||
assigned-clock-rates:
|
||||
items:
|
||||
- description: Must be 800 MHz
|
||||
- description: Must be 400 MHz
|
||||
|
||||
port:
|
||||
type: object
|
||||
description:
|
||||
A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx8mq-clock.h>
|
||||
dcss: display-controller@32e00000 {
|
||||
compatible = "nxp,imx8mq-dcss";
|
||||
reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
|
||||
interrupts = <6>, <8>, <9>;
|
||||
interrupt-names = "ctxld", "ctxld_kick", "vblank";
|
||||
interrupt-parent = <&irqsteer>;
|
||||
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
|
||||
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
|
||||
<&clk IMX8MQ_CLK_DISP_DTRC>;
|
||||
clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
|
||||
<&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
|
||||
<&clk IMX8MQ_CLK_27M>;
|
||||
assigned-clock-rates = <800000000>,
|
||||
<400000000>;
|
||||
port {
|
||||
dcss_out: endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -43,7 +43,7 @@ Required properties (all function blocks):
|
||||
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
|
||||
"mediatek,<chip>-disp-mutex" - display mutex
|
||||
"mediatek,<chip>-disp-od" - overdrive
|
||||
the supported chips are mt2701, mt2712 and mt8173.
|
||||
the supported chips are mt2701, mt7623, mt2712 and mt8173.
|
||||
- reg: Physical base address and length of the function block register space
|
||||
- interrupts: The interrupt signal from the function block (required, except for
|
||||
merge and split function blocks).
|
||||
|
||||
@@ -7,7 +7,7 @@ output bus.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-dpi"
|
||||
the supported chips are mt2701 , mt8173 and mt8183.
|
||||
the supported chips are mt2701, mt7623, mt8173 and mt8183.
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
|
||||
@@ -7,7 +7,7 @@ channel output.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-dsi"
|
||||
the supported chips are mt2701, mt8173 and mt8183.
|
||||
- the supported chips are mt2701, mt7623, mt8173 and mt8183.
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-mipi-tx"
|
||||
the supported chips are mt2701, mt8173 and mt8183.
|
||||
- the supported chips are mt2701, 7623, mt8173 and mt8183.
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- clocks: PLL reference clock
|
||||
- clock-output-names: name of the output clock line to the DSI encoder
|
||||
|
||||
@@ -6,6 +6,7 @@ its parallel input.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-hdmi".
|
||||
- the supported chips are mt2701, mt7623 and mt8173
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
@@ -32,6 +33,7 @@ The HDMI CEC controller handles hotplug detection and CEC communication.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-cec"
|
||||
- the supported chips are mt7623 and mt8173
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clock
|
||||
@@ -44,6 +46,7 @@ The Mediatek's I2C controller is used to interface with I2C devices.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-hdmi-ddc"
|
||||
- the supported chips are mt7623 and mt8173
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- clocks: device clock
|
||||
- clock-names: Should be "ddc-i2c".
|
||||
@@ -56,6 +59,7 @@ output and drives the HDMI pads.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-hdmi-phy"
|
||||
- the supported chips are mt2701, mt7623 and mt8173
|
||||
- reg: Physical base address and length of the module's registers
|
||||
- clocks: PLL reference clock
|
||||
- clock-names: must contain "pll_ref"
|
||||
|
||||
@@ -90,6 +90,8 @@ Required properties:
|
||||
* "qcom,dsi-phy-14nm-660"
|
||||
* "qcom,dsi-phy-10nm"
|
||||
* "qcom,dsi-phy-10nm-8998"
|
||||
* "qcom,dsi-phy-7nm"
|
||||
* "qcom,dsi-phy-7nm-8150"
|
||||
- reg: Physical base address and length of the registers of PLL, PHY. Some
|
||||
revisions require the PHY regulator base address, whereas others require the
|
||||
PHY lane base address. See below for each PHY revision.
|
||||
@@ -98,7 +100,7 @@ Required properties:
|
||||
* "dsi_pll"
|
||||
* "dsi_phy"
|
||||
* "dsi_phy_regulator"
|
||||
For DSI 14nm and 10nm PHYs:
|
||||
For DSI 14nm, 10nm and 7nm PHYs:
|
||||
* "dsi_pll"
|
||||
* "dsi_phy"
|
||||
* "dsi_phy_lane"
|
||||
@@ -116,7 +118,7 @@ Required properties:
|
||||
- vcca-supply: phandle to vcca regulator device node
|
||||
For 14nm PHY:
|
||||
- vcca-supply: phandle to vcca regulator device node
|
||||
For 10nm PHY:
|
||||
For 10nm and 7nm PHY:
|
||||
- vdds-supply: phandle to vdds regulator device node
|
||||
|
||||
Optional properties:
|
||||
|
||||
@@ -13,7 +13,9 @@ properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- bananapi,lhr050h41
|
||||
- bananapi,lhr050h41
|
||||
- feixin,k101-im2byl02
|
||||
|
||||
- const: ilitek,ili9881c
|
||||
|
||||
backlight: true
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/mantix,mlaf057we51-x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mantix MLAF057WE51-X 5.7" 720x1440 TFT LCD panel
|
||||
|
||||
maintainers:
|
||||
- Guido Günther <agx@sigxcpu.org>
|
||||
|
||||
description:
|
||||
Mantix MLAF057WE51 X is a 720x1440 TFT LCD panel connected using
|
||||
a MIPI-DSI video interface.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mantix,mlaf057we51-x
|
||||
|
||||
port: true
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: DSI virtual channel
|
||||
|
||||
avdd-supply:
|
||||
description: Positive analog power supply
|
||||
|
||||
avee-supply:
|
||||
description: Negative analog power supply
|
||||
|
||||
vddi-supply:
|
||||
description: 1.8V I/O voltage supply
|
||||
|
||||
reset-gpios: true
|
||||
|
||||
backlight: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- avdd-supply
|
||||
- avee-supply
|
||||
- vddi-supply
|
||||
- reset-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
panel@0 {
|
||||
compatible = "mantix,mlaf057we51-x";
|
||||
reg = <0>;
|
||||
avdd-supply = <®_avdd>;
|
||||
avee-supply = <®_avee>;
|
||||
vddi-supply = <®_1v8_p>;
|
||||
reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
|
||||
backlight = <&backlight>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -29,6 +29,8 @@ properties:
|
||||
# compatible must be listed in alphabetical order, ordered by compatible.
|
||||
# The description in the comment is mandatory for each compatible.
|
||||
|
||||
# Ampire AM-1280800N3TZQW-T00H 10.1" WQVGA TFT LCD panel
|
||||
- ampire,am-1280800n3tzqw-t00h
|
||||
# Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel
|
||||
- ampire,am-480272h3tmqw-t01h
|
||||
# Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel
|
||||
@@ -87,6 +89,8 @@ properties:
|
||||
- cdtech,s070swv29hg-dc44
|
||||
# CDTech(H.K.) Electronics Limited 7" 800x480 color TFT-LCD panel
|
||||
- cdtech,s070wv95-ct16
|
||||
# Chefree CH101OLHLWH-002 10.1" (1280x800) color TFT LCD panel
|
||||
- chefree,ch101olhlwh-002
|
||||
# Chunghwa Picture Tubes Ltd. 7" WXGA TFT LCD panel
|
||||
- chunghwa,claa070wp03xg
|
||||
# Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
|
||||
@@ -159,6 +163,8 @@ properties:
|
||||
- innolux,n156bge-l21
|
||||
# Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel
|
||||
- innolux,zj070na-01p
|
||||
# King & Display KD116N21-30NV-A010 eDP TFT LCD panel
|
||||
- kingdisplay,kd116n21-30nv-a010
|
||||
# Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel
|
||||
- koe,tx14d24vm1bpa
|
||||
# Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel
|
||||
@@ -219,6 +225,8 @@ properties:
|
||||
- osddisplays,osd070t1718-19ts
|
||||
# One Stop Displays OSD101T2045-53TS 10.1" 1920x1200 panel
|
||||
- osddisplays,osd101t2045-53ts
|
||||
# POWERTIP PH800480T013-IDF2 7.0" WVGA TFT LCD panel
|
||||
- powertip,ph800480t013-idf02
|
||||
# QiaoDian XianShi Corporation 4"3 TFT LCD panel
|
||||
- qiaodian,qd43003c0-40
|
||||
# Rocktech Displays Ltd. RK101II01D-CT 10.1" TFT 1280x800
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user