From 732061bcf925289cb9b7f981e39f02dad3adca09 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Mon, 27 Nov 2023 16:55:22 +0800 Subject: [PATCH] pwm: rockchip: support pwm version 4 Change-Id: I64e270c49e51244a9437f40cdc9e0df5aff1576d Signed-off-by: Damon Ding --- drivers/pwm/pwm-rockchip-irq-callbacks.h | 36 + drivers/pwm/pwm-rockchip.c | 878 ++++++++++++++++++++++- include/linux/pwm-rockchip.h | 2 +- 3 files changed, 889 insertions(+), 27 deletions(-) diff --git a/drivers/pwm/pwm-rockchip-irq-callbacks.h b/drivers/pwm/pwm-rockchip-irq-callbacks.h index fe238d87e63c..191c62e96821 100644 --- a/drivers/pwm/pwm-rockchip-irq-callbacks.h +++ b/drivers/pwm/pwm-rockchip-irq-callbacks.h @@ -25,4 +25,40 @@ static void rockchip_pwm_oneshot_callback(struct pwm_device *pwm, struct pwm_sta */ } +static void rockchip_pwm_wave_middle_callback(struct pwm_device *pwm) +{ + /* + * If you want to update the configuration of wave table, set + * struct rockchip_pwm_wave_table and call rockchip_pwm_set_wave(). + * + * struct rockchip_pwm_wave_config wave_config; + * struct rockchip_pwm_wave_table duty_table; + * + * //fill the duty table + * ...... + * wave_config.duty_table = &duty_table; + * wave_config.enable = true; + * rockchip_pwm_set_wave(pwm, &wave_config); + * + */ +} + +static void rockchip_pwm_wave_max_callback(struct pwm_device *pwm) +{ + /* + * If you want to update the configuration of wave table, set + * struct rockchip_pwm_wave_table and call rockchip_pwm_set_wave(). + * + * struct rockchip_pwm_wave_config wave_config; + * struct rockchip_pwm_wave_table duty_table; + * + * //fill the duty table + * ...... + * wave_config.duty_table = &duty_table; + * wave_config.enable = true; + * rockchip_pwm_set_wave(pwm, &wave_config); + * + */ +} + #endif diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index 4dd469f146ae..98d5f21c67a9 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -22,8 +22,11 @@ #include #include "pwm-rockchip-irq-callbacks.h" -#define PWM_MAX_CHANNEL_NUM 4 +#define PWM_MAX_CHANNEL_NUM 8 +/* + * regs for pwm v1-v3 + */ #define PWM_CTRL_TIMER_EN (1 << 0) #define PWM_CTRL_OUTPUT_EN (1 << 3) @@ -59,12 +62,163 @@ #define PWM_CH_INT(n) BIT(n) +/* + * regs for pwm v4 + */ +#define HIWORD_UPDATE(v, l, h) (((v) << (l)) | (GENMASK(h, l) << 16)) + +/* VERSION_ID */ +#define CHANNEL_NUM_SUPPORT_SHIFT 0 +#define CHANNEL_NUM_SUPPORT_MASK (0xf << CHANNEL_NUM_SUPPORT_SHIFT) +#define CHANNLE_INDEX_SHIFT 4 +#define CHANNLE_INDEX_MASK (0xf << CHANNLE_INDEX_SHIFT) +#define IR_TRANS_SUPPORT BIT(8) +#define POWER_KEY_SUPPORT BIT(9) +#define FREQ_METER_SUPPORT BIT(10) +#define COUNTER_SUPPORT BIT(11) +#define WAVE_SUPPORT BIT(12) +#define FILTER_SUPPORT BIT(13) +#define MINOR_VERSION_SHIFT 16 +#define MINOR_VERSION_MASK (0xff << MINOR_VERSION_SHIFT) +#define MAIN_VERSION_SHIFT 24 +#define MAIN_VERSION_MASK (0xff << MAIN_VERSION_SHIFT) +/* PWM_ENABLE */ +#define PWM_ENABLE_V4 (0x3 << 0) +#define PWM_CLK_EN(v) HIWORD_UPDATE(v, 0, 0) +#define PWM_EN(v) HIWORD_UPDATE(v, 1, 1) +#define PWM_CTRL_UPDATE_EN(v) HIWORD_UPDATE(v, 2, 2) +#define PWM_GLOBAL_JOIN_EN(v) HIWORD_UPDATE(v, 4, 4) +/* PWM_CLK_CTRL */ +#define CLK_PRESCALE(v) HIWORD_UPDATE(v, 0, 2) +#define CLK_SCALE(v) HIWORD_UPDATE(v, 4, 12) +#define CLK_SRC_SEL(v) HIWORD_UPDATE(v, 13, 14) +#define CLK_GLOBAL_SEL(v) HIWORD_UPDATE(v, 15, 15) +/* PWM_CTRL */ +#define PWM_MODE(v) HIWORD_UPDATE(v, 0, 1) +#define ONESHOT_MODE 0 +#define CONTINUOUS_MODE 1 +#define CAPTURE_MODE 2 +#define PWM_POLARITY(v) HIWORD_UPDATE(v, 2, 3) +#define DUTY_NEGATIVE (0 << 0) +#define DUTY_POSITIVE (1 << 0) +#define INACTIVE_NEGATIVE (0 << 1) +#define INACTIVE_POSITIVE (1 << 1) +#define PWM_ALIGNED_INVALID(v) HIWORD_UPDATE(v, 5, 5) +#define PWM_IN_SEL(v) HIWORD_UPDATE(v, 6, 8) +/* PWM_RPT */ +#define FIRST_DIMENSIONAL_SHIFT 0 +#define SECOND_DIMENSINAL_SHIFT 16 +/* INTSTS*/ +#define CAP_LPR_INTSTS_SHIFT 0 +#define CAP_HPR_INTSTS_SHIFT 1 +#define ONESHOT_END_INTSTS_SHIFT 2 +#define RELOAD_INTSTS_SHIFT 3 +#define FREQ_INTSTS_SHIFT 4 +#define PWR_INTSTS_SHIFT 5 +#define IR_TRANS_END_INTSTS_SHIFT 6 +#define WAVE_MAX_INT_SHIFT 7 +#define WAVE_MIDDLE_INT_SHIFT 8 +#define CAP_LPR_INT BIT(CAP_LPR_INTSTS_SHIFT) +#define CAP_HPR_INT BIT(CAP_HPR_INTSTS_SHIFT) +#define ONESHOT_END_INT BIT(ONESHOT_END_INTSTS_SHIFT) +#define RELOAD_INT BIT(RELOAD_INTSTS_SHIFT) +#define FREQ_INT BIT(FREQ_INTSTS_SHIFT) +#define PWR_INT BIT(PWR_INTSTS_SHIFT) +#define IR_TRANS_END_INT BIT(IR_TRANS_END_INTSTS_SHIFT) +#define WAVE_MAX_INT BIT(WAVE_MAX_INT_SHIFT) +#define WAVE_MIDDLE_INT BIT(WAVE_MIDDLE_INT_SHIFT) +/* INT_EN */ +#define CAP_LPR_INT_EN(v) HIWORD_UPDATE(v, 0, 0) +#define CAP_HPR_INT_EN(v) HIWORD_UPDATE(v, 1, 1) +#define ONESHOT_END_INT_EN(v) HIWORD_UPDATE(v, 2, 2) +#define RELOAD_INT_EN(v) HIWORD_UPDATE(v, 3, 3) +#define FREQ_INT_EN(v) HIWORD_UPDATE(v, 4, 4) +#define PWR_INT_EN(v) HIWORD_UPDATE(v, 5, 5) +#define IR_TRANS_END_INT_EN(v) HIWORD_UPDATE(v, 6, 6) +#define WAVE_MAX_INT_EN(v) HIWORD_UPDATE(v, 7, 7) +#define WAVE_MIDDLE_INT_EN(v) HIWORD_UPDATE(v, 8, 8) +/* WAVE_MEM_ARBITER */ +#define WAVE_MEM_ARBITER 0x80 +#define WAVE_MEM_GRANT_SHIFT 0 +#define WAVE_MEM_READ_LOCK_SHIFT 16 +/* WAVE_MEM_STATUS */ +#define WAVE_MEM_STATUS 0x84 +#define WAVE_MEM_STATUS_SHIFT 0 +/* WAVE_CTRL */ +#define WAVE_CTRL 0x88 +#define WAVE_DUTY_EN(v) HIWORD_UPDATE(v, 0, 0) +#define WAVE_PERIOD_EN(v) HIWORD_UPDATE(v, 1, 1) +#define WAVE_WIDTH_MODE(v) HIWORD_UPDATE(v, 2, 2) +#define WAVE_UPDATE_MODE(v) HIWORD_UPDATE(v, 3, 3) +#define WAVE_MEM_CLK_SEL(v) HIWORD_UPDATE(v, 4, 5) +#define WAVE_DUTY_AMPLIFY(v) HIWORD_UPDATE(v, 6, 10) +#define WAVE_PERIOD_AMPLIFY(v) HIWORD_UPDATE(v, 11, 15) +/* WAVE_MAX */ +#define WAVE_MAX 0x8c +#define WAVE_DUTY_MAX_SHIFT 0 +#define WAVE_PERIOD_MAX_SHIFT 16 +/* WAVE_MIN */ +#define WAVE_MIN 0x90 +#define WAVE_DUTY_MIN_SHIFT 0 +#define WAVE_PERIOD_MIN_SHIFT 16 +/* WAVE_OFFSET */ +#define WAVE_OFFSET 0x94 +#define WAVE_OFFSET_SHIFT 0 +/* WAVE_MIDDLE */ +#define WAVE_MIDDLE 0x98 +#define WAVE_MIDDLE_SHIFT 0 +/* WAVE_HOLD */ +#define WAVE_HOLD 0x9c +#define MAX_HOLD_SHIFT 0 +#define MIN_HOLD_SHIFT 8 +#define MIDDLE_HOLD_SHIFT 16 +/* GLOBAL_ARBITER */ +#define GLOBAL_ARBITER 0xc0 +#define GLOBAL_GRANT_SHIFT 0 +#define GLOBAL_READ_LOCK_SHIFT 16 +/* GLOBAL_CTRL */ +#define GLOBAL_CTRL 0xc4 +#define GLOBAL_PWM_EN(v) HIWORD_UPDATE(v, 0, 0) +#define GLOBAL_PWM_UPDATE_EN(v) HIWORD_UPDATE(v, 1, 1) +/* FREQ_ARBITER */ +#define FREQ_ARBITER 0x1c0 +#define FREQ_GRANT_SHIFT 0 +#define FREQ_READ_LOCK_SHIFT 16 +/* FREQ_CTRL */ +#define FREQ_CTRL 0x1c4 +#define FREQ_EN(v) HIWORD_UPDATE(v, 0, 0) +#define FREQ_CLK_SEL(v) HIWORD_UPDATE(v, 1, 2) +#define FREQ_CHANNEL_SEL(v) HIWORD_UPDATE(v, 3, 5) +#define FREQ_CLK_SWITCH_MODE(v) HIWORD_UPDATE(v, 6, 6) +#define FREQ_TIMIER_CLK_SEL(v) HIWORD_UPDATE(v, 7, 7) +/* FREQ_TIMER_VALUE */ +#define FREQ_TIMER_VALUE 0x1c8 +/* FREQ_RESULT_VALUE */ +#define FREQ_RESULT_VALUE 0x1cc +/* COUNTER_ARBITER */ +#define COUNTER_ARBITER 0x200 +#define COUNTER_GRANT_SHIFT 0 +#define COUNTER_READ_LOCK_SHIFT 16 +/* COUNTER_CTRL */ +#define COUNTER_CTRL 0x204 +#define COUNTER_EN(v) HIWORD_UPDATE(v, 0, 0) +#define COUNTER_CLK_SEL(v) HIWORD_UPDATE(v, 1, 2) +#define COUNTER_CHANNEL_SEL(v) HIWORD_UPDATE(v, 3, 5) +#define COUNTER_CLR(v) HIWORD_UPDATE(v, 6, 6) +/* COUNTER_LOW */ +#define COUNTER_LOW 0x208 +/* COUNTER_HIGH */ +#define COUNTER_HIGH 0x20c +/* WAVE_MEM */ +#define WAVE_MEM 0x400 + struct rockchip_pwm_chip { struct pwm_chip chip; struct clk *clk; struct clk *pclk; struct pinctrl *pinctrl; struct pinctrl_state *active_state; + struct delayed_work pwm_work; const struct rockchip_pwm_data *data; struct resource *res; struct dentry *debugfs; @@ -73,11 +227,14 @@ struct rockchip_pwm_chip { bool vop_pwm_en; /* indicate voppwm mirror register state */ bool center_aligned; bool oneshot_en; + bool wave_en; + bool global_ctrl_grant; bool freq_meter_support; bool counter_support; bool wave_support; int channel_id; int irq; + u8 main_version; u8 capture_cnt; }; @@ -87,6 +244,16 @@ struct rockchip_pwm_regs { unsigned long cntr; unsigned long ctrl; unsigned long version; + + unsigned long enable; + unsigned long clk_ctrl; + unsigned long offset; + unsigned long rpt; + unsigned long hpr; + unsigned long lpr; + unsigned long intsts; + unsigned long int_en; + unsigned long int_mask; }; struct rockchip_pwm_funcs { @@ -120,6 +287,7 @@ struct rockchip_pwm_data { bool supports_polarity; bool supports_lock; bool vop_pwm; + u8 main_version; u32 enable_conf; u32 enable_conf_mask; u32 oneshot_cnt_max; @@ -149,7 +317,8 @@ static void rockchip_pwm_get_state(struct pwm_chip *chip, return; } - dclk_div = pc->oneshot_en ? 2 : 1; + if (pc->main_version < 4) + dclk_div = pc->oneshot_en ? 2 : 1; tmp = readl_relaxed(pc->base + pc->data->regs.period); tmp *= dclk_div * pc->data->prescaler * NSEC_PER_SEC; @@ -159,9 +328,13 @@ static void rockchip_pwm_get_state(struct pwm_chip *chip, tmp *= dclk_div * pc->data->prescaler * NSEC_PER_SEC; state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate); - val = readl_relaxed(pc->base + pc->data->regs.ctrl); - if (pc->oneshot_en) - enable_conf &= ~PWM_CONTINUOUS; + if (pc->main_version >= 4) { + val = readl_relaxed(pc->base + pc->data->regs.enable); + } else { + val = readl_relaxed(pc->base + pc->data->regs.ctrl); + if (pc->oneshot_en) + enable_conf &= ~PWM_CONTINUOUS; + } state->enabled = (val & enable_conf) == enable_conf; if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE)) @@ -367,6 +540,177 @@ static int rockchip_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm, return 0; } +static irqreturn_t rockchip_pwm_irq_v4(int irq, void *data) +{ + struct rockchip_pwm_chip *pc = data; + int val; + irqreturn_t ret = IRQ_NONE; + + val = readl_relaxed(pc->base + pc->data->regs.intsts); +#ifdef CONFIG_PWM_ROCKCHIP_ONESHOT + if (val & ONESHOT_END_INT) { + struct pwm_state state; + + writel_relaxed(ONESHOT_END_INT, pc->base + pc->data->regs.intsts); + + /* + * Set pwm state to disabled when the oneshot mode finished. + */ + pwm_get_state(&pc->chip.pwms[0], &state); + state.enabled = false; + state.oneshot_count = 0; + state.oneshot_repeat = 0; + pwm_apply_state(&pc->chip.pwms[0], &state); + + rockchip_pwm_oneshot_callback(&pc->chip.pwms[0], &state); + + ret = IRQ_HANDLED; + } +#endif + if (val & CAP_LPR_INT) { + writel_relaxed(CAP_LPR_INT, pc->base + pc->data->regs.intsts); + pc->capture_cnt++; + + ret = IRQ_HANDLED; + } else if (val & CAP_HPR_INT) { + writel_relaxed(CAP_HPR_INT, pc->base + pc->data->regs.intsts); + pc->capture_cnt++; + + ret = IRQ_HANDLED; + } + + /* + * Capture input waveform: + * _______ _______ + * | | | | + * __| |_______________| |________ + * ^0 ^1 ^2 + * + * At position 0, the LPR interrupt comes, and PERIOD_LPR reg shows + * the low polarity cycles which should be ignored. The effective + * high and low polarity cycles will be calculated in position 1 and + * position 2, where the HPR and LPR interrupts come again. + */ + if (pc->capture_cnt > 3) { + writel_relaxed(CAP_LPR_INT | CAP_HPR_INT, pc->base + pc->data->regs.intsts); + writel_relaxed(CAP_LPR_INT_EN(false) | CAP_HPR_INT_EN(false), + pc->base + pc->data->regs.int_en); + } + + if (val & WAVE_MIDDLE_INT) { + writel_relaxed(WAVE_MIDDLE_INT, pc->base + pc->data->regs.intsts); + + rockchip_pwm_wave_middle_callback(&pc->chip.pwms[0]); + + ret = IRQ_HANDLED; + } + + if (val & WAVE_MAX_INT) { + writel_relaxed(WAVE_MAX_INT, pc->base + pc->data->regs.intsts); + + rockchip_pwm_wave_max_callback(&pc->chip.pwms[0]); + + ret = IRQ_HANDLED; + } + + return ret; +} + +static void rockchip_pwm_config_v4(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + unsigned long period, duty; + u64 div = 0; + u32 rpt = 0; + u32 offset = 0; + + /* + * Since period and duty cycle registers have a width of 32 + * bits, every possible input period can be obtained using the + * default prescaler value for all practical clock rate values. + */ + div = (u64)pc->clk_rate * state->period; + period = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); + + div = (u64)pc->clk_rate * state->duty_cycle; + duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); + + writel_relaxed(period, pc->base + pc->data->regs.period); + writel_relaxed(duty, pc->base + pc->data->regs.duty); + + if (pc->data->supports_polarity) { + if (state->polarity == PWM_POLARITY_INVERSED) + writel_relaxed(PWM_POLARITY(DUTY_NEGATIVE | INACTIVE_POSITIVE), + pc->base + pc->data->regs.ctrl); + else + writel_relaxed(PWM_POLARITY(DUTY_POSITIVE | INACTIVE_NEGATIVE), + pc->base + pc->data->regs.ctrl); + } + +#ifdef CONFIG_PWM_ROCKCHIP_ONESHOT + if ((state->oneshot_count > 0 && state->oneshot_count <= pc->data->oneshot_cnt_max) && + (state->oneshot_repeat <= pc->data->oneshot_rpt_max)) { + rpt |= (state->oneshot_count - 1) << FIRST_DIMENSIONAL_SHIFT; + if (state->oneshot_repeat) + rpt |= (state->oneshot_repeat - 1) << SECOND_DIMENSINAL_SHIFT; + + if (state->duty_offset > 0 && + state->duty_offset <= (state->period - state->duty_cycle)) { + div = (u64)pc->clk_rate * state->duty_offset; + offset = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); + } else if (state->duty_offset > (state->period - state->duty_cycle)) { + dev_err(chip->dev, "Duty_offset must be between %lld and %lld.\n", + state->duty_cycle, state->period); + } + + pc->oneshot_en = true; + } else { + if (state->oneshot_count) + dev_err(chip->dev, "Oneshot_count must be between 1 and %d.\n", + pc->data->oneshot_cnt_max); + + pc->oneshot_en = false; + } +#endif + + if (pc->oneshot_en) { + writel_relaxed(PWM_MODE(ONESHOT_MODE) | PWM_ALIGNED_INVALID(true), + pc->base + pc->data->regs.ctrl); + writel_relaxed(offset, pc->base + pc->data->regs.offset); + writel_relaxed(rpt, pc->base + pc->data->regs.rpt); + writel_relaxed(ONESHOT_END_INT_EN(true), pc->base + pc->data->regs.int_en); + } else { + writel_relaxed(PWM_MODE(CONTINUOUS_MODE) | PWM_ALIGNED_INVALID(false), + pc->base + pc->data->regs.ctrl); + writel_relaxed(0, pc->base + pc->data->regs.offset); + if (!pc->wave_en) + writel_relaxed(0, pc->base + pc->data->regs.rpt); + writel_relaxed(ONESHOT_END_INT_EN(false), pc->base + pc->data->regs.int_en); + } + + writel_relaxed(PWM_CTRL_UPDATE_EN(true), pc->base + pc->data->regs.enable); +} + +static int rockchip_pwm_enable_v4(struct pwm_chip *chip, struct pwm_device *pwm, bool enable) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + int ret; + + if (enable) { + ret = clk_enable(pc->clk); + if (ret) + return ret; + } + + writel_relaxed(PWM_EN(enable) | PWM_CLK_EN(enable), pc->base + pc->data->regs.enable); + + if (!enable) + clk_disable(pc->clk); + + return 0; +} + static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state) { @@ -423,6 +767,129 @@ out: return ret; } +static void rockchip_pwm_set_capture_v4(struct pwm_chip *chip, struct pwm_device *pwm, + bool enable) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u32 channel_sel = 0; + + if (enable) + channel_sel = pc->channel_id; + + pc->capture_cnt = 0; + + writel_relaxed(enable ? PWM_MODE(CAPTURE_MODE) : PWM_MODE(CONTINUOUS_MODE), + pc->base + pc->data->regs.ctrl); + writel_relaxed(CAP_LPR_INT_EN(enable) | CAP_HPR_INT_EN(enable) | PWM_IN_SEL(channel_sel), + pc->base + pc->data->regs.int_en); +} + +static int rockchip_pwm_get_capture_result_v4(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_capture *capture_res) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u64 tmp; + + tmp = readl_relaxed(pc->base + pc->data->regs.hpr); + tmp *= pc->data->prescaler * NSEC_PER_SEC; + capture_res->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate); + + tmp = readl_relaxed(pc->base + pc->data->regs.lpr); + tmp *= pc->data->prescaler * NSEC_PER_SEC; + capture_res->period = DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate) + capture_res->duty_cycle; + + if (!capture_res->duty_cycle || !capture_res->period) + return -EINVAL; + + writel_relaxed(0, pc->base + pc->data->regs.hpr); + writel_relaxed(0, pc->base + pc->data->regs.lpr); + + return 0; +} + +static u8 rockchip_pwm_get_capture_cnt(struct rockchip_pwm_chip *pc) +{ + return pc->capture_cnt; +} + +static int rockchip_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_capture *capture_res, unsigned long timeout_ms) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + struct pwm_state curstate; + u8 capture_cnt; + int ret = 0; + + if (!pc->data->funcs.set_capture || !pc->data->funcs.get_capture_result) { + dev_err(chip->dev, "Unsupported capture mode\n"); + return -EINVAL; + } + + pwm_get_state(pwm, &curstate); + if (curstate.enabled) { + dev_err(chip->dev, "Failed to enable capture mode because PWM%d is busy\n", + pc->channel_id); + return -EBUSY; + } + + ret = clk_enable(pc->pclk); + if (ret) + return ret; + + pc->data->funcs.set_capture(chip, pwm, true); + ret = pc->data->funcs.enable(chip, pwm, true); + if (ret) { + dev_err(chip->dev, "Failed to enable capture mode\n"); + goto err_disable_pclk; + } + + ret = readx_poll_timeout(rockchip_pwm_get_capture_cnt, pc, capture_cnt, + capture_cnt > 3, 0, timeout_ms * 1000); + if (!ret) { + dev_err(chip->dev, "Failed to wait for LPR/HPR interrupt\n"); + ret = -ETIMEDOUT; + } else { + ret = pc->data->funcs.get_capture_result(chip, pwm, capture_res); + if (ret) + dev_err(chip->dev, "Failed to get capture result\n"); + } + + pc->data->funcs.enable(chip, pwm, false); + pc->data->funcs.set_capture(chip, pwm, false); + +err_disable_pclk: + clk_disable(pc->pclk); + + return ret; +} + +static int rockchip_pwm_set_counter_v4(struct pwm_chip *chip, struct pwm_device *pwm, + bool enable) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u32 arbiter = 0; + u32 channel_sel = 0; + u32 val; + + if (enable) { + arbiter = BIT(pc->channel_id) << COUNTER_READ_LOCK_SHIFT | + BIT(pc->channel_id) << COUNTER_GRANT_SHIFT, + channel_sel = pc->channel_id; + } + + writel_relaxed(arbiter, pc->base + COUNTER_ARBITER); + if (enable) { + val = readl_relaxed(pc->base + COUNTER_ARBITER); + if (!(val & arbiter)) + return -EINVAL; + } + + writel_relaxed(COUNTER_EN(enable) | COUNTER_CHANNEL_SEL(channel_sel), + pc->base + COUNTER_CTRL); + + return 0; +} + int rockchip_pwm_set_counter(struct pwm_device *pwm, bool enable) { struct pwm_chip *chip; @@ -467,6 +934,25 @@ err_disable_pclk: } EXPORT_SYMBOL_GPL(rockchip_pwm_set_counter); +static int rockchip_pwm_get_counter_result_v4(struct pwm_chip *chip, struct pwm_device *pwm, + unsigned long *counter_res, bool is_clear) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u64 low, high; + + low = readl_relaxed(pc->base + COUNTER_LOW); + high = readl_relaxed(pc->base + COUNTER_HIGH); + + *counter_res = (high << 32) | low; + if (!*counter_res) + return -EINVAL; + + if (is_clear) + writel_relaxed(COUNTER_CLR(true), pc->base + COUNTER_CTRL); + + return 0; +} + int rockchip_pwm_get_counter_result(struct pwm_device *pwm, unsigned long *counter_res, bool is_clear) { @@ -504,6 +990,61 @@ err_disable_pclk: } EXPORT_SYMBOL_GPL(rockchip_pwm_get_counter_result); +static int rockchip_pwm_set_freq_meter_v4(struct pwm_chip *chip, struct pwm_device *pwm, + bool enable, unsigned long delay_ms) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u64 div = 0; + u64 timer_val = 0; + u32 arbiter = 0; + u32 channel_sel = 0; + u32 val; + + if (enable) { + arbiter = BIT(pc->channel_id) << FREQ_READ_LOCK_SHIFT | + BIT(pc->channel_id) << FREQ_GRANT_SHIFT; + channel_sel = pc->channel_id; + + div = (u64)pc->clk_rate * delay_ms; + timer_val = DIV_ROUND_CLOSEST_ULL(div, MSEC_PER_SEC); + } + + writel_relaxed(arbiter, pc->base + FREQ_ARBITER); + if (enable) { + val = readl_relaxed(pc->base + FREQ_ARBITER); + if (!(val & arbiter)) + return -EINVAL; + } + + writel_relaxed(FREQ_INT_EN(enable), pc->base + pc->data->regs.int_en); + writel_relaxed(timer_val, pc->base + FREQ_TIMER_VALUE); + writel_relaxed(FREQ_EN(enable) | FREQ_CHANNEL_SEL(channel_sel), + pc->base + FREQ_CTRL); + + return 0; +} + +static int rockchip_pwm_get_freq_meter_result_v4(struct pwm_chip *chip, struct pwm_device *pwm, + unsigned long delay_ms, unsigned long *freq_hz) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + int ret; + u32 val; + + ret = readl_relaxed_poll_timeout(pc->base + pc->data->regs.intsts, val, val & FREQ_INT, + 0, delay_ms * 1000); + if (!ret) { + dev_err(chip->dev, "failed to wait for freq_meter interrupt\n"); + return -ETIMEDOUT; + } + + *freq_hz = readl_relaxed(pc->base + FREQ_RESULT_VALUE); + if (!*freq_hz) + return -EINVAL; + + return 0; +} + int rockchip_pwm_set_freq_meter(struct pwm_device *pwm, unsigned long delay_ms, unsigned long *freq_hz) { @@ -554,6 +1095,78 @@ int rockchip_pwm_set_freq_meter(struct pwm_device *pwm, unsigned long delay_ms, } EXPORT_SYMBOL_GPL(rockchip_pwm_set_freq_meter); +static int rockchip_pwm_global_ctrl_v4(struct pwm_chip *chip, struct pwm_device *pwm, + enum rockchip_pwm_global_ctrl_cmd cmd) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u32 arbiter = 0; + u32 val = 0; + + switch (cmd) { + case PWM_GLOBAL_CTRL_JOIN: + writel_relaxed(PWM_GLOBAL_JOIN_EN(true), pc->base + pc->data->regs.enable); + writel_relaxed(CLK_GLOBAL_SEL(true), pc->base + pc->data->regs.clk_ctrl); + break; + case PWM_GLOBAL_CTRL_EXIT: + writel_relaxed(PWM_GLOBAL_JOIN_EN(false), pc->base + pc->data->regs.enable); + writel_relaxed(CLK_GLOBAL_SEL(false), pc->base + pc->data->regs.clk_ctrl); + break; + case PWM_GLOBAL_CTRL_GRANT: + arbiter = BIT(pc->channel_id) << GLOBAL_READ_LOCK_SHIFT | + BIT(pc->channel_id) << GLOBAL_GRANT_SHIFT; + + writel_relaxed(arbiter, pc->base + GLOBAL_ARBITER); + val = readl_relaxed(pc->base + GLOBAL_ARBITER); + if (!(val & arbiter)) { + dev_err(chip->dev, "Failed to abtain global ctrl arbitration for PWM%d\n", + pc->channel_id); + return -EINVAL; + } + + pc->global_ctrl_grant = true; + break; + case PWM_GLOBAL_CTRL_RECLAIM: + writel_relaxed(0, pc->base + GLOBAL_ARBITER); + + pc->global_ctrl_grant = false; + break; + case PWM_GLOBAL_CTRL_UPDATE: + if (!pc->global_ctrl_grant) { + dev_err(chip->dev, "CMD %d: get global ctrl arbitration first for PWM%d\n", + cmd, pc->channel_id); + return -EINVAL; + } + + writel_relaxed(GLOBAL_PWM_UPDATE_EN(true), pc->base + GLOBAL_CTRL); + break; + case PWM_GLOBAL_CTRL_ENABLE: + if (!pc->global_ctrl_grant) { + dev_err(chip->dev, "CMD %d: get global ctrl arbitration first for PWM%d\n", + cmd, pc->channel_id); + return -EINVAL; + } + + writel_relaxed(PWM_CLK_EN(true), pc->base + pc->data->regs.enable); + writel_relaxed(GLOBAL_PWM_EN(true), pc->base + GLOBAL_CTRL); + break; + case PWM_GLOBAL_CTRL_DISABLE: + if (!pc->global_ctrl_grant) { + dev_err(chip->dev, "CMD %d: get global ctrl arbitration first for PWM%d\n", + cmd, pc->channel_id); + return -EINVAL; + } + + writel_relaxed(PWM_CLK_EN(false), pc->base + pc->data->regs.enable); + writel_relaxed(GLOBAL_PWM_EN(false), pc->base + GLOBAL_CTRL); + break; + default: + dev_err(chip->dev, "Unsupported global ctrl cmd %d\n", cmd); + return -EINVAL; + } + + return 0; +} + int rockchip_pwm_global_ctrl(struct pwm_device *pwm, enum rockchip_pwm_global_ctrl_cmd cmd) { struct pwm_chip *chip; @@ -597,6 +1210,143 @@ err_disable_pclk: } EXPORT_SYMBOL_GPL(rockchip_pwm_global_ctrl); +static int rockchip_pwm_set_wave_table_v4(struct pwm_chip *chip, struct pwm_device *pwm, + struct rockchip_pwm_wave_table *table_config, + enum rockchip_pwm_wave_table_width_mode width_mode) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u64 table_val = 0; + u64 div = 0; + u32 arbiter = 0; + u32 val; + u16 table_max; + int i; + + if (width_mode == PWM_WAVE_TABLE_16BITS_WIDTH) + table_max = pc->data->wave_table_max / 2; + else + table_max = pc->data->wave_table_max; + + if (!table_config->table || + table_config->offset > table_max || table_config->len > table_max) { + dev_err(chip->dev, "The wave table to set is out of range for PWM%d\n", + pc->channel_id); + return -EINVAL; + } + + arbiter = BIT(pc->channel_id) << WAVE_MEM_GRANT_SHIFT | + BIT(pc->channel_id) << WAVE_MEM_READ_LOCK_SHIFT; + writel_relaxed(arbiter, pc->base + WAVE_MEM_ARBITER); + + val = readl_relaxed(pc->base + WAVE_MEM_ARBITER); + if (!(val & arbiter)) { + dev_err(chip->dev, "Failed to abtain wave memory arbitration for PWM%d\n", + pc->channel_id); + return -EINVAL; + } + + if (width_mode == PWM_WAVE_TABLE_16BITS_WIDTH) { + for (i = 0; i < table_config->len; i++) { + div = (u64)pc->clk_rate * table_config->table[i]; + table_val = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); + writel_relaxed(table_val & 0xff, + pc->base + WAVE_MEM + (table_config->offset + i) * 2 * 4); + if (readl_poll_timeout(pc->base + WAVE_MEM_STATUS, + val, (val & BIT(WAVE_MEM_STATUS_SHIFT)), + 1000, 10 * 1000)) { + dev_err(chip->dev, + "Wait for wave mem(offset 0x%08x) to update failed\n", + (table_config->offset + i) * 2 * 4); + return -ETIMEDOUT; + } + + writel_relaxed((table_val >> 8) & 0xff, + pc->base + WAVE_MEM + + ((table_config->offset + i) * 2 + 1) * 4); + if (readl_poll_timeout(pc->base + WAVE_MEM_STATUS, + val, (val & BIT(WAVE_MEM_STATUS_SHIFT)), + 1000, 10 * 1000)) { + dev_err(chip->dev, + "Wait for wave mem(offset 0x%08x) to update failed\n", + ((table_config->offset + i) * 2 + 1) * 4); + return -ETIMEDOUT; + } + } + } else { + for (i = 0; i < table_config->len; i++) { + div = (u64)pc->clk_rate * table_config->table[i]; + table_val = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); + writel_relaxed(table_val, + pc->base + WAVE_MEM + (table_config->offset + i) * 4); + if (readl_poll_timeout(pc->base + WAVE_MEM_STATUS, + val, (val & BIT(WAVE_MEM_STATUS_SHIFT)), + 1000, 10 * 1000)) { + dev_err(chip->dev, + "Wait for wave mem(offset 0x%08x) to update failed\n", + (table_config->offset + i) * 4); + return -ETIMEDOUT; + } + } + } + + writel_relaxed(0, pc->base + WAVE_MEM_ARBITER); + + return 0; +} + +static int rockchip_pwm_set_wave_v4(struct pwm_chip *chip, struct pwm_device *pwm, + struct rockchip_pwm_wave_config *config) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u32 ctrl = 0; + u32 max_val = 0; + u32 min_val = 0; + u32 offset = 0; + u32 middle = 0; + u32 rpt = 0; + u8 factor = 0; + + if (config->enable) { + /* + * If the width mode is 16-bits mode, two 8-bits table units + * are combined into one 16-bits unit. + */ + if (config->width_mode == PWM_WAVE_TABLE_16BITS_WIDTH) + factor = 2; + else + factor = 1; + + ctrl = WAVE_DUTY_EN(config->duty_en) | + WAVE_PERIOD_EN(config->period_en) | + WAVE_WIDTH_MODE(config->width_mode) | + WAVE_UPDATE_MODE(config->update_mode); + max_val = config->duty_max * factor << WAVE_DUTY_MAX_SHIFT | + config->period_max * factor << WAVE_PERIOD_MAX_SHIFT; + min_val = config->duty_min * factor << WAVE_DUTY_MIN_SHIFT | + config->period_min * factor << WAVE_PERIOD_MIN_SHIFT; + offset = config->offset * factor << WAVE_OFFSET_SHIFT; + middle = config->middle * factor << WAVE_MIDDLE_SHIFT; + + rpt = config->rpt << FIRST_DIMENSIONAL_SHIFT; + } else { + ctrl = WAVE_DUTY_EN(false) | WAVE_PERIOD_EN(false); + } + + writel_relaxed(ctrl, pc->base + WAVE_CTRL); + writel_relaxed(max_val, pc->base + WAVE_MAX); + writel_relaxed(min_val, pc->base + WAVE_MIN); + writel_relaxed(offset, pc->base + WAVE_OFFSET); + writel_relaxed(middle, pc->base + WAVE_MIDDLE); + + writel_relaxed(rpt, pc->base + pc->data->regs.rpt); + writel_relaxed(WAVE_MAX_INT_EN(config->enable) | WAVE_MIDDLE_INT_EN(config->enable), + pc->base + pc->data->regs.int_en); + + pc->wave_en = config->enable; + + return 0; +} + int rockchip_pwm_set_wave(struct pwm_device *pwm, struct rockchip_pwm_wave_config *config) { struct pwm_chip *chip; @@ -704,12 +1454,14 @@ static inline void rockchip_pwm_debugfs_deinit(struct rockchip_pwm_chip *pc) #endif static const struct pwm_ops rockchip_pwm_ops = { - .get_state = rockchip_pwm_get_state, + .capture = rockchip_pwm_capture, .apply = rockchip_pwm_apply, + .get_state = rockchip_pwm_get_state, .owner = THIS_MODULE, }; static const struct rockchip_pwm_data pwm_data_v1 = { + .main_version = 0x01, .regs = { .version = 0x5c, .duty = 0x04, @@ -731,6 +1483,7 @@ static const struct rockchip_pwm_data pwm_data_v1 = { }; static const struct rockchip_pwm_data pwm_data_v2 = { + .main_version = 0x02, .regs = { .version = 0x5c, .duty = 0x08, @@ -753,6 +1506,7 @@ static const struct rockchip_pwm_data pwm_data_v2 = { }; static const struct rockchip_pwm_data pwm_data_vop = { + .main_version = 0x02, .regs = { .version = 0x5c, .duty = 0x08, @@ -775,6 +1529,7 @@ static const struct rockchip_pwm_data pwm_data_vop = { }; static const struct rockchip_pwm_data pwm_data_v3 = { + .main_version = 0x03, .regs = { .version = 0x5c, .duty = 0x08, @@ -797,6 +1552,47 @@ static const struct rockchip_pwm_data pwm_data_v3 = { }, }; +static const struct rockchip_pwm_data pwm_data_v4 = { + .main_version = 0x04, + .regs = { + .version = 0x0, + .enable = 0x4, + .clk_ctrl = 0x8, + .ctrl = 0xc, + .period = 0x10, + .duty = 0x14, + .offset = 0x18, + .rpt = 0x1c, + .hpr = 0x2c, + .lpr = 0x30, + .intsts = 0x70, + .int_en = 0x74, + .int_mask = 0x78, + }, + .prescaler = 1, + .supports_polarity = true, + .supports_lock = true, + .vop_pwm = false, + .oneshot_cnt_max = 0x10000, + .oneshot_rpt_max = 0x10000, + .wave_table_max = 0x300, + .enable_conf = PWM_ENABLE_V4, + .funcs = { + .enable = rockchip_pwm_enable_v4, + .config = rockchip_pwm_config_v4, + .set_capture = rockchip_pwm_set_capture_v4, + .get_capture_result = rockchip_pwm_get_capture_result_v4, + .set_counter = rockchip_pwm_set_counter_v4, + .get_counter_result = rockchip_pwm_get_counter_result_v4, + .set_freq_meter = rockchip_pwm_set_freq_meter_v4, + .get_freq_meter_result = rockchip_pwm_get_freq_meter_result_v4, + .global_ctrl = rockchip_pwm_global_ctrl_v4, + .set_wave_table = rockchip_pwm_set_wave_table_v4, + .set_wave = rockchip_pwm_set_wave_v4, + .irq_handler = rockchip_pwm_irq_v4, + }, +}; + static const struct of_device_id rockchip_pwm_dt_ids[] = { { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, @@ -818,7 +1614,7 @@ static int rockchip_pwm_probe(struct platform_device *pdev) const struct of_device_id *id; struct rockchip_pwm_chip *pc; struct resource *r; - u32 enable_conf, ctrl; + u32 enable_conf, ctrl, version; bool enabled; int ret, count; @@ -876,13 +1672,6 @@ static int rockchip_pwm_probe(struct platform_device *pdev) goto err_clk; } - pc->channel_id = rockchip_pwm_get_channel_id(pdev->dev.of_node->full_name); - if (pc->channel_id < 0 || pc->channel_id >= PWM_MAX_CHANNEL_NUM) { - dev_err(&pdev->dev, "Channel id is out of range: %d\n", pc->channel_id); - ret = -EINVAL; - goto err_pclk; - } - pc->pinctrl = devm_pinctrl_get(&pdev->dev); if (IS_ERR(pc->pinctrl)) { dev_err(&pdev->dev, "Get pinctrl failed!\n"); @@ -905,20 +1694,54 @@ static int rockchip_pwm_probe(struct platform_device *pdev) pc->chip.base = of_alias_get_id(pdev->dev.of_node, "pwm"); pc->chip.npwm = 1; pc->clk_rate = clk_get_rate(pc->clk); + pc->main_version = pc->data->main_version; + if (pc->main_version >= 4) { + version = readl_relaxed(pc->base + pc->data->regs.version); + pc->channel_id = (version & CHANNLE_INDEX_MASK) >> CHANNLE_INDEX_SHIFT; + pc->freq_meter_support = !!(version & FREQ_METER_SUPPORT); + pc->counter_support = !!(version & COUNTER_SUPPORT); + pc->wave_support = !!(version & WAVE_SUPPORT); + } else { + pc->channel_id = rockchip_pwm_get_channel_id(pdev->dev.of_node->full_name); + } + if (pc->channel_id < 0 || pc->channel_id >= PWM_MAX_CHANNEL_NUM) { + dev_err(&pdev->dev, "Channel id is out of range: %d\n", pc->channel_id); + ret = -EINVAL; + goto err_pclk; + } - if (IS_ENABLED(CONFIG_PWM_ROCKCHIP_ONESHOT) && pc->data->funcs.irq_handler) { - pc->irq = platform_get_irq_optional(pdev, 0); - if (pc->irq < 0) { - dev_warn(&pdev->dev, - "Can't get oneshot mode irq and oneshot interrupt is unsupported\n"); - } else { - ret = devm_request_irq(&pdev->dev, pc->irq, pc->data->funcs.irq_handler, - IRQF_NO_SUSPEND | IRQF_SHARED, - "rk_pwm_oneshot_irq", pc); - if (ret) { - dev_err(&pdev->dev, "Claim oneshot IRQ failed\n"); + if (pc->data->funcs.irq_handler) { + if (pc->main_version >= 4) { + pc->irq = platform_get_irq(pdev, 0); + if (pc->irq < 0) { + dev_err(&pdev->dev, "Get irq failed\n"); + ret = pc->irq; goto err_pclk; } + + ret = devm_request_irq(&pdev->dev, pc->irq, pc->data->funcs.irq_handler, + IRQF_NO_SUSPEND, "rk_pwm_irq", pc); + if (ret) { + dev_err(&pdev->dev, "Claim IRQ failed\n"); + goto err_pclk; + } + } else { + if (IS_ENABLED(CONFIG_PWM_ROCKCHIP_ONESHOT)) { + pc->irq = platform_get_irq_optional(pdev, 0); + if (pc->irq < 0) { + dev_warn(&pdev->dev, + "Can't get oneshot mode irq and oneshot interrupt is unsupported\n"); + } else { + ret = devm_request_irq(&pdev->dev, pc->irq, + pc->data->funcs.irq_handler, + IRQF_NO_SUSPEND | IRQF_SHARED, + "rk_pwm_oneshot_irq", pc); + if (ret) { + dev_err(&pdev->dev, "Claim oneshot IRQ failed\n"); + goto err_pclk; + } + } + } } } @@ -928,7 +1751,10 @@ static int rockchip_pwm_probe(struct platform_device *pdev) } enable_conf = pc->data->enable_conf; - ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); + if (pc->main_version >= 4) + ctrl = readl_relaxed(pc->base + pc->data->regs.enable); + else + ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); enabled = (ctrl & enable_conf) == enable_conf; pc->center_aligned = diff --git a/include/linux/pwm-rockchip.h b/include/linux/pwm-rockchip.h index 32d1bbfa1fdb..60e42aaba7a1 100644 --- a/include/linux/pwm-rockchip.h +++ b/include/linux/pwm-rockchip.h @@ -32,7 +32,7 @@ enum rockchip_pwm_global_ctrl_cmd { * struct rockchip_pwm_wave_table - wave table config object * @offset: the offset of wave table to set * @len: the length of wave table to set - * @table: the values of wave table to set (in nanoseconds) + * @table: the values of wave table to set * @ */ struct rockchip_pwm_wave_table {